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@ -1,6 +1,6 @@ |
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MICROWIND 2.0 |
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* |
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* Rule File for CMOS 0.12µm |
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* Rule File for CMOS 0.2µm (modified on 0.12µm version) |
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* |
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* Date : 27 Apr 99 created by Etienne Sicard |
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* 04 Jan 00 smaller dt |
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@ -9,8 +9,9 @@ MICROWIND 2.0 |
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* 20 Apr 01 various lowK, 4 types of MOS |
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* 10 Dec 01 Bsim4 model, gatek |
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* 02 Jun 03 Bsim4 pmos model |
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* 22 Apr 20 modified by iotcat for assignment purpose |
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NAME CMOS 0.12µm - 6 Metal |
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NAME CMOS 0.2µm - 1 Metal |
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lambda = 0.2 (Lambda is set to half the gate size) |
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metalLayers = 1 (Number of metal layers) |
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@ -52,12 +53,8 @@ r306 = 4 (width of drain and source diff) |
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r307 = 2 (extra gate poly) |
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r310 = 16 (Minimum poly surface lambda2) |
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* |
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* Poly 2 |
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* |
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r311 = 2 (poly2 width) |
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r312 = 2 (poly2 spacing) |
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* |
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* Contact |
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* |
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r401 = 2 (contact width) |
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r402 = 4 (contact spacing) |
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r403 = 1 (metal border for contact) |
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@ -68,64 +65,19 @@ r407 = 1 (poly2 border for contact) |
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* |
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* metal |
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r501 = 3 (metal width) |
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r502 = 4 (metal spacing) |
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r502 = 3 (metal spacing) |
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r510 = 16 (minimum surface) |
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* via |
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r601 = 2 (Via width) |
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r602 = 4 (Spacing) |
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r604 = 1 (border of metal) |
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r605 = 1 (border of metal2) |
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* metal 2 |
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r701 = 3 (Metal 2 width) |
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r702 = 4 |
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r710 = 16 (minimum surface) |
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* via 2 |
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r801 = 2 (Via width) |
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r802 = 4 (Spacing) |
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r804 = 1 (border of metal2) |
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r805 = 1 (border of metal3) |
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* metal 3 |
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r901 = 3 (width) |
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r902 = 4 (spacing) |
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r910 = 16 (Minimum surface) |
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* via 3 |
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ra01 = 2 (Via width) |
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ra02 = 4 (Spacing) |
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ra04 = 1 (border of metal3) |
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ra05 = 1 (border of metal4) |
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* metal 4 |
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rb01 = 3 (width) |
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rb02 = 4 (spacing) |
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rb10 = 16 (Minimum surface) |
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* via 4 |
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rc01 = 2 (Via width) |
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rc02 = 4 (Spacing) |
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rc04 = 1 (border of metal4) |
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rc05 = 3 (border of metal5) |
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* metal 5 |
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rd01 = 8 (width) |
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rd02 = 8 (spacing) |
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rd10 = 64 (Minimum surface) |
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* via 5 |
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re01 = 5 (Via width) |
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re02 = 5 (Spacing) |
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re04 = 2 (border of metal5) |
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re05 = 2 (border of metal6) |
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* metal 6 |
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rf01 = 8 (width) |
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rf02 = 8 (spacing) |
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rf10 = 144 (minimum surface) |
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* |
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* Pad rules |
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* |
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rp01 = 1330 (Pad width 80µm) |
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rp02 = 1330 (Pad spacing 80µm) |
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rp01 = 1330 (Pad width 80µm) |
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rp02 = 1330 (Pad spacing 80µm) |
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rp03 = 40 (Border of Vias) |
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rp04 = 40 (Border of metals) |
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rp05 = 200 (to unrelated active areas) |
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* |
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* Thickness of conductors for process aspect |
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* All in µm |
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* All in µm |
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* |
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* P++ epitaxial |
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thepi = 1.0 |
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@ -196,8 +148,8 @@ rev5 = 1 |
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* |
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* Parasitic capacitances |
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* |
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cpoOxyde= 15000 (Surface capacitance Poly/Thin oxyde aF/µm2) |
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cedram = 150000 (embedded Dram surface capacitance aF/µm2) |
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cpoOxyde= 15000 (Surface capacitance Poly/Thin oxyde aF/µm2) |
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cedram = 150000 (embedded Dram surface capacitance aF/µm2) |
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cpobody = 400 (No lineic capa) |
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cp2body = 400 |
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cmebody = 200 (Strong value due to upper and lower capa) |
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@ -227,7 +179,7 @@ cm6m5 = 100 |
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* |
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* Lateral Crosstalk |
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* |
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cmextk = 30 (Lineic capacitance for crosstalk coupling in aF/µm) |
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cmextk = 30 (Lineic capacitance for crosstalk coupling in aF/µm) |
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cm2xtk = 30 (C is computed using Cx=cmextk*l/spacing) |
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cm3xtk = 30 |
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cm4xtk = 30 |
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@ -240,7 +192,7 @@ cdnpwell = 350 (n+/psub) |
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cdpnwell = 300 (p+/nwell) |
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cnwell = 250 (nwell/psub) |
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cpwell = 100 (pwell/nsub) |
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cldn = 100 (Lineic capacitance N+/P- aF/µm) |
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cldn = 100 (Lineic capacitance N+/P- aF/µm) |
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cldp = 100 (Idem for P+/N-) |
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* |
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* MOS definition |
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@ -403,5 +355,5 @@ hvdd = 2.5 |
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temperature = 27 |
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riseTime = 0.025 |
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* |
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* End CMOS 0.12µm |
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* End CMOS 0.2µm |
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* |
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