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[IBIS ver] 2.1 |
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[File name] default.ibs |
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[File Rev] 03/22/02 |
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[Date] 03/22/0 |
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[Source] Microwind2 |
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[Notes] This file describes the IBIS model |
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| to control the Microwind floorplan |
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| |
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[Copyright] Etienne SICARD |
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[Component] BENCH01 |
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[Manufacturer] INSA |
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[Package] |
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R_pkg 1 |
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L_pkg 5nH |
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C_pkg 2pF |
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| |
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[Pin] signal_name model_name |
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1 A in1 |
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2 B in1 |
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3 C in1 |
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4 VDD1 power |
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5 VSS1 gnd |
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6 Clk in1 |
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7 D in1 |
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8 nand2 out1 |
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9 nor2 out1 |
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10 VDD2 power |
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11 VSS2 gnd |
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12 carry out1 |
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13 nor4 out1 |
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14 or3 out1 |
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15 Q out1 |
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16 VDD3 power |
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17 VSS3 gnd |
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18 sum out1 |
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19 carry out1 |
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20 carryBuff out1 |
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21 xorb out1 |
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22 abuf out1 |
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[END] |
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@ -0,0 +1,407 @@ |
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MICROWIND 2.0 |
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* |
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* Rule File for CMOS 0.12µm |
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* |
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* Date : 27 Apr 99 created by Etienne Sicard |
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* 04 Jan 00 smaller dt |
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* 03 Avr 01 2d cross-section |
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* 17 Apr 01 update params, add high voltage, tox, level3 |
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* 20 Apr 01 various lowK, 4 types of MOS |
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* 10 Dec 01 Bsim4 model, gatek |
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* 02 Jun 03 Bsim4 pmos model |
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* |
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NAME CMOS 0.12µm - 6 Metal |
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* |
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lambda = 0.2 (Lambda is set to half the gate size) |
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metalLayers = 1 (Number of metal layers) |
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edram = 0 (Embedded DRAM process) |
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salicide = 0 (Enable salicide 1=enable 0= disable) |
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* |
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* Dielectrics |
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* |
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lowK = 3.1 (inter-metal oxide permittivity) |
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gateK = 5.0 (HighK gate dielectric) |
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* |
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* Gate oxide thickness is defined in l3tox (Level3), b4toxe (Bsim4) |
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* 2nm for core, 6nm for 2.5V I/O and analog |
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* |
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* Design rules associated to each layer |
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* |
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* Well |
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* |
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r101 = 10 (well width) |
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r102 = 11 (well spacing) |
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* |
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* Diffusion |
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* |
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r201 = 4 (diffusion width) |
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r202 = 4 (diffusion spacing) |
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r203 = 3 (border of nwell on diffp) |
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r204 = 5 (nwell to next diffn) |
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r205 = 8 (diffn to diffp) |
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r210 = 16 (Minimum diff surface lambda2) |
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* |
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* Poly |
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* |
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r301 = 2 (poly width) |
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r302 = 2 (gate length) |
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r303 = 4 (high voltage gate length) |
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r304 = 3 (poly spacing) |
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r305 = 1 (spacing poly and unrelated diff) |
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r306 = 4 (width of drain and source diff) |
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r307 = 2 (extra gate poly) |
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r310 = 16 (Minimum poly surface lambda2) |
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* |
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* Poly 2 |
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* |
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r311 = 2 (poly2 width) |
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r312 = 2 (poly2 spacing) |
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* |
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* Contact |
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r401 = 2 (contact width) |
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r402 = 4 (contact spacing) |
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r403 = 1 (metal border for contact) |
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r404 = 1 (poly border for contact) |
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r405 = 1 (diff border for contact) |
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r406 = 2 (contact to gate) |
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r407 = 1 (poly2 border for contact) |
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* |
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* metal |
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r501 = 3 (metal width) |
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r502 = 4 (metal spacing) |
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r510 = 16 (minimum surface) |
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* via |
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r601 = 2 (Via width) |
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r602 = 4 (Spacing) |
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r604 = 1 (border of metal) |
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r605 = 1 (border of metal2) |
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* metal 2 |
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r701 = 3 (Metal 2 width) |
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r702 = 4 |
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r710 = 16 (minimum surface) |
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* via 2 |
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r801 = 2 (Via width) |
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r802 = 4 (Spacing) |
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r804 = 1 (border of metal2) |
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r805 = 1 (border of metal3) |
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* metal 3 |
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r901 = 3 (width) |
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r902 = 4 (spacing) |
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r910 = 16 (Minimum surface) |
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* via 3 |
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ra01 = 2 (Via width) |
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ra02 = 4 (Spacing) |
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ra04 = 1 (border of metal3) |
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ra05 = 1 (border of metal4) |
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* metal 4 |
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rb01 = 3 (width) |
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rb02 = 4 (spacing) |
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rb10 = 16 (Minimum surface) |
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* via 4 |
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rc01 = 2 (Via width) |
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rc02 = 4 (Spacing) |
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rc04 = 1 (border of metal4) |
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rc05 = 3 (border of metal5) |
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* metal 5 |
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rd01 = 8 (width) |
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rd02 = 8 (spacing) |
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rd10 = 64 (Minimum surface) |
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* via 5 |
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re01 = 5 (Via width) |
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re02 = 5 (Spacing) |
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re04 = 2 (border of metal5) |
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re05 = 2 (border of metal6) |
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* metal 6 |
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rf01 = 8 (width) |
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rf02 = 8 (spacing) |
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rf10 = 144 (minimum surface) |
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* |
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* Pad rules |
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* |
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rp01 = 1330 (Pad width 80µm) |
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rp02 = 1330 (Pad spacing 80µm) |
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rp03 = 40 (Border of Vias) |
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rp04 = 40 (Border of metals) |
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rp05 = 200 (to unrelated active areas) |
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* |
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* Thickness of conductors for process aspect |
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* All in µm |
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* |
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* P++ epitaxial |
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thepi = 1.0 |
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heepi = -4.0 |
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* |
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* Shallow tretch isolation |
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thsti = 0.8 |
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hesti = -0.8 |
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* |
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* Poly |
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thpoly = 0.20 |
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hepoly = 0.01 |
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* |
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* Poly2 |
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thp2 = 0.2 |
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hep2 = 0.22 |
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* |
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* Diffusions |
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thdn = 0.4 |
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thdp = 0.4 |
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thnw = 1.0 |
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* |
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* Metallisation |
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thme = 0.40 |
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heme = 1.1 |
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thm2 = 0.40 |
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hem2 = 2.0 |
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thm3 = 0.40 |
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hem3 = 2.9 |
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thm4 = 0.40 |
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hem4 = 3.8 |
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thm5 = 0.8 |
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hem5 = 4.8 |
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thm6 = 0.8 |
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hem6 = 6.0 |
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thpass = 0.3 |
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hepass = 7.0 |
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thnit = 0.2 |
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henit = 7.3 |
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* |
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* Resistances Copper |
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* Unit is ohm/square |
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* |
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repo = 4 |
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repu = 40 |
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r2po = 4 |
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r2pu = 40 |
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redn = 25 |
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reun = 250 |
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redp = 30 |
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reup = 300 |
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rep2 = 4 |
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reme = 0.05 |
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rem2 = 0.05 |
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rem3 = 0.05 |
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rem4 = 0.05 |
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rem5 = 0.03 |
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rem6 = 0.03 |
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* |
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* Resistances vias: unit is ohm/via |
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reco = 20 |
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revi = 2 |
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rev2 = 2 |
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rev3 = 2 |
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rev4 = 1 |
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rev5 = 1 |
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* |
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* |
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* Parasitic capacitances |
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* |
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cpoOxyde= 15000 (Surface capacitance Poly/Thin oxyde aF/µm2) |
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cedram = 150000 (embedded Dram surface capacitance aF/µm2) |
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cpobody = 400 (No lineic capa) |
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cp2body = 400 |
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cmebody = 200 (Strong value due to upper and lower capa) |
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cm2body = 180 (to metal grid i.e 2*Cg) |
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cm3body = 160 |
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cm4body = 140 |
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cm5body = 120 |
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cm6body = 100 |
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cgsn = 500 ( Gate/source capa of nMOS) |
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cgsp = 500 |
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cmelineic = 0 |
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cm2lineic = 0 |
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cm3lineic = 0 |
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cm4lineic = 0 |
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cm5lineic = 0 |
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cm6lineic = 0 |
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* |
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* Vertical crosstalk |
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* |
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cmepoly = 60 |
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cp2poly = 1700 |
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cm2me = 100 |
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cm3m2 = 100 |
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cm4m3 = 100 |
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cm5m4 = 100 |
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cm6m5 = 100 |
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* |
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* Lateral Crosstalk |
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* |
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cmextk = 30 (Lineic capacitance for crosstalk coupling in aF/µm) |
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cm2xtk = 30 (C is computed using Cx=cmextk*l/spacing) |
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cm3xtk = 30 |
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cm4xtk = 30 |
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cm5xtk = 40 |
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cm6xtk = 40 |
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* |
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* Junction capacitances |
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* |
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cdnpwell = 350 (n+/psub) |
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cdpnwell = 300 (p+/nwell) |
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cnwell = 250 (nwell/psub) |
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cpwell = 100 (pwell/nsub) |
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cldn = 100 (Lineic capacitance N+/P- aF/µm) |
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cldp = 100 (Idem for P+/N-) |
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* |
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* MOS definition |
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* |
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MOS1 low leakage |
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MOS2 high speed |
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MOS3 high voltage |
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* |
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* Nmos Model 3 parameters |
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* |
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NMOS |
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l3vto = 0.4 |
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l3u0 = 0.06 |
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l3tox = 2e-9 |
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l3vmax = 120e3 |
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l3gamma = 0.4 |
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l3theta = 0.5 |
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l3kappa = 0.06 |
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l3phi = 0.2 |
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l3ld = 8e-9 |
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l3nss = 0.06 |
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* |
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* high speed |
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l3v2to = 0.3 |
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l3u2 = 0.06 |
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l3t2ox = 2e-9 |
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* |
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* high voltage |
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l3v3to = 0.7 |
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l3u3 = 0.06 |
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l3t3ox = 5e-9 |
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* |
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* Pmos Model 3 |
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* |
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PMOS |
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l3vto = -0.45 |
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l3u0 = 0.02 |
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l3tox = 2.0e-9 |
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l3vmax = 110e3 |
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l3gamma = 0.4 |
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l3theta = 0.3 |
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l3kappa = 0.06 |
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l3phi = 0.2 |
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l3ld = 8e-9 |
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l3nss = 0.06 |
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* |
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* high speed |
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l3v2to = -0.3 |
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l3u2 = 0.02 |
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l3t2ox = 2.0e-9 |
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* |
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* high voltage |
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l3v3to = -0.7 |
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l3u3 = 0.02 |
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l3t3ox = 5e-9 |
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* |
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* BSIM4 parameters |
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* |
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* Nmos |
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* |
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NMOS |
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b4vtho = 0.4 |
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b4k1 = 0.45 |
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b4k2 = 0.1 |
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b4xj = 1.7e-7 |
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b4toxe = 2.0e-9 |
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b4ndep = 1.8e17 |
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b4d0vt = 2.3 |
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b4d1vt = 0.54 |
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b4vfb = -0.9 |
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b4u0 = 0.05 |
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b4voff = 0.05 |
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b4ua = 3e-15 |
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b4uc = -0.047e-15 |
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b4vsat = 100e3 |
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b4pscbe1 =230e6 |
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b4ute = -1.8 |
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b4kt1 = -0.06 |
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b4lint = 0.01e-6 |
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b4wint = 0.02e-6 |
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b4xj = 1.5e-7 |
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b4nfact = 1.6 |
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b4ndep = 1.7e17 |
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b4pclm = 1.1 |
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* |
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* high speed |
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b4v2to = 0.3 |
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b4l2int = 0.02e-6 |
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b4t2ox = 2.0e-9 |
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* |
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* high voltage |
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b4v3to = 0.7 |
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b4t3ox = 5e-9 |
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* |
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* Pmos BSIM4 |
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* |
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PMOS |
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b4vtho = 0.45 |
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b4k1 = 0.45 |
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b4k2 = 0.1 |
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b4xj = 1.7e-7 |
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b4toxe = 2e-9 |
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b4ndep = 1.8e17 |
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b4d0vt = 2.3 |
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b4d1vt = 0.54 |
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b4vfb = -0.9 |
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b4u0 = 0.018 |
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b4ua = 1.5e-15 |
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b4voff = 0.05 |
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b4uc = -0.047e-15 |
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b4vsat = 60e3 |
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b4pscbe1 =230e6 |
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b4ute = -1.8 |
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b4kt1 = -0.06 |
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b4lint = 0.01e-6 |
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b4nfact = 1.6 |
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b4wint = 0.02e-6 |
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b4xj = 1.5e-7 |
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b4ndep = 1.7e17 |
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b4pclm = 0.7 |
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* |
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* high speed |
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b4v2to = 0.3 |
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b4l2int = 0.02e-6 |
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b4t2ox = 2e-9 |
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* |
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* high voltage |
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b4v3to = 0.7 |
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b4t3ox = 5e-9 |
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* |
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* CIF Layers |
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* MicroWind layer, CIF layer, overetch |
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* |
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cif nwell 1 0.0 |
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cif diffp 17 0.5 |
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cif diffn 16 0.5 |
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cif aarea 2 0.5 |
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cif poly 13 0.0 |
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cif contact 19 0.025 |
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cif metal 23 0.0125 |
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cif via 25 0.0125 |
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cif metal2 27 0.0125 |
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cif via2 32 0.0125 |
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cif metal3 34 0.0125 |
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cif via3 35 0.0125 |
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cif metal4 36 0.0125 |
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cif via4 52 0.0125 |
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cif metal5 53 0.0 |
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cif via5 54 0.0 |
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cif metal6 55 0.0 |
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cif passiv 31 0.0 |
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cif text 94 0.0 |
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* |
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* |
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* MicroWind simulation parameters |
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* |
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deltaT = 0.30e-12 (Minimum simulation interval dT) |
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vdd = 4 |
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hvdd = 2.5 |
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temperature = 27 |
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riseTime = 0.025 |
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* |
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* End CMOS 0.12µm |
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* |
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@ -0,0 +1,67 @@ |
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VERSION 2020/4/22 11:59:38 |
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FIG #C:\Users\ushio\Desktop\dd\nor.MSK |
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BB(177,57,213,100) |
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SIMU #5.00 |
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REC(177,74,26,22,NW) |
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REC(185,96,18,2,NW) |
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REC(208,82,4,2,NW) |
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REC(208,90,4,2,DP) |
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REC(195,77,5,16,DP) |
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REC(187,77,6,16,DP) |
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REC(180,77,5,16,DP) |
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REC(208,86,4,2,DN) |
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REC(195,65,5,4,DN) |
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REC(187,65,6,4,DN) |
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REC(180,65,5,4,DN) |
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REC(181,78,2,2,CO) |
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REC(197,84,2,2,CO) |
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REC(189,95,2,2,CO) |
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REC(197,66,2,2,CO) |
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REC(197,90,2,2,CO) |
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REC(181,66,2,2,CO) |
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REC(197,78,2,2,CO) |
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REC(181,90,2,2,CO) |
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REC(189,66,2,2,CO) |
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REC(209,78,2,2,CO) |
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REC(181,84,2,2,CO) |
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REC(177,71,8,2,PO) |
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REC(185,63,2,32,PO) |
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REC(208,94,4,2,PO) |
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REC(195,70,9,2,PO) |
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REC(193,63,2,32,PO) |
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REC(177,94,15,4,ME) |
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REC(180,77,4,17,ME) |
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REC(188,65,4,8,ME) |
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REC(196,77,4,16,ME) |
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REC(177,57,27,4,ME) |
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REC(188,73,16,4,ME) |
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REC(180,61,4,8,ME) |
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REC(208,98,4,2,ME) |
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REC(196,61,4,8,ME) |
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REC(193,77,2,16,DP) |
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REC(185,77,2,16,DP) |
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REC(193,65,2,4,DN) |
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REC(185,65,2,4,DN) |
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TITLE 179 97 #Vdd |
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$1 1000 0 |
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TITLE 190 59 #Vss |
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$0 1000 0 |
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TITLE 178 72 #A |
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$c 1000 0 0.2250 0.2500 0.4750 0.5000 |
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TITLE 203 71 #B |
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$c 1000 0 0.4750 0.5000 0.9750 1.0000 |
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TITLE 203 75 #OUTPUT |
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$v 1000 0 |
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TITLE 213 95 #Polysilicon |
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$- 1000 0 |
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TITLE 213 99 #Metal |
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$- 1000 0 |
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TITLE 213 87 #N+ Diffusion |
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$- 1000 0 |
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TITLE 213 79 #Contact |
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$- 1000 0 |
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TITLE 213 91 #P+ Diffusion |
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$- 1000 0 |
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TITLE 213 83 #N Well |
||||
$- 1000 0 |
||||
FFIG C:\Users\ushio\Desktop\dd\nor.MSK |
||||
Loading…
Reference in new issue