From 8962599cdeb6470922f1dc4912661577225c3f23 Mon Sep 17 00:00:00 2001 From: iotcat Date: Tue, 5 May 2020 18:40:14 +0800 Subject: [PATCH] archieved --- Exp28/YL_7448.vwf | 367 +++ Exp28/YL_7448.vwf.temp | 367 +++ Exp28/YL_dec7748.bdf | 403 +++ Exp28/YL_dec7748.qpf | 30 + Exp28/YL_dec7748.qsf | 60 + Exp28/YL_dec7748.qws | Bin 0 -> 2010 bytes Exp28/db/YL_dec7748.(0).cnf.cdb | Bin 0 -> 1001 bytes Exp28/db/YL_dec7748.(0).cnf.hdb | Bin 0 -> 663 bytes Exp28/db/YL_dec7748.(1).cnf.cdb | Bin 0 -> 2091 bytes Exp28/db/YL_dec7748.(1).cnf.hdb | Bin 0 -> 1228 bytes Exp28/db/YL_dec7748.asm.qmsg | 6 + Exp28/db/YL_dec7748.asm.rdb | Bin 0 -> 1528 bytes Exp28/db/YL_dec7748.asm_labs.ddb | Bin 0 -> 7166 bytes Exp28/db/YL_dec7748.cbx.xml | 5 + Exp28/db/YL_dec7748.cmp.bpm | Bin 0 -> 629 bytes Exp28/db/YL_dec7748.cmp.cdb | Bin 0 -> 4212 bytes Exp28/db/YL_dec7748.cmp.hdb | Bin 0 -> 9986 bytes Exp28/db/YL_dec7748.cmp.idb | Bin 0 -> 1463 bytes Exp28/db/YL_dec7748.cmp.kpt | Bin 0 -> 225 bytes Exp28/db/YL_dec7748.cmp.logdb | 1 + Exp28/db/YL_dec7748.cmp.rdb | Bin 0 -> 18447 bytes Exp28/db/YL_dec7748.cmp0.ddb | Bin 0 -> 50938 bytes Exp28/db/YL_dec7748.cmp1.ddb | Bin 0 -> 50267 bytes Exp28/db/YL_dec7748.cmp2.ddb | Bin 0 -> 40962 bytes Exp28/db/YL_dec7748.cmp_merge.kpt | Bin 0 -> 229 bytes Exp28/db/YL_dec7748.db_info | 3 + Exp28/db/YL_dec7748.eds_overflow | 1 + Exp28/db/YL_dec7748.fit.qmsg | 46 + Exp28/db/YL_dec7748.hier_info | 36 + Exp28/db/YL_dec7748.hif | Bin 0 -> 404 bytes Exp28/db/YL_dec7748.ipinfo | Bin 0 -> 177 bytes Exp28/db/YL_dec7748.lpc.html | 18 + Exp28/db/YL_dec7748.lpc.rdb | Bin 0 -> 413 bytes Exp28/db/YL_dec7748.lpc.txt | 5 + Exp28/db/YL_dec7748.map.ammdb | Bin 0 -> 137 bytes Exp28/db/YL_dec7748.map.bpm | Bin 0 -> 605 bytes Exp28/db/YL_dec7748.map.cdb | Bin 0 -> 2592 bytes Exp28/db/YL_dec7748.map.hdb | Bin 0 -> 9524 bytes Exp28/db/YL_dec7748.map.kpt | Bin 0 -> 227 bytes Exp28/db/YL_dec7748.map.logdb | 1 + Exp28/db/YL_dec7748.map.qmsg | 11 + Exp28/db/YL_dec7748.map.rdb | Bin 0 -> 1327 bytes Exp28/db/YL_dec7748.map_bb.cdb | Bin 0 -> 1790 bytes Exp28/db/YL_dec7748.map_bb.hdb | Bin 0 -> 8451 bytes Exp28/db/YL_dec7748.map_bb.logdb | 1 + Exp28/db/YL_dec7748.pre_map.hdb | Bin 0 -> 10096 bytes Exp28/db/YL_dec7748.pti_db_list.ddb | Bin 0 -> 191 bytes .../YL_dec7748.root_partition.map.reg_db.cdb | Bin 0 -> 215 bytes Exp28/db/YL_dec7748.routing.rdb | Bin 0 -> 6386 bytes Exp28/db/YL_dec7748.rtlv.hdb | Bin 0 -> 10058 bytes Exp28/db/YL_dec7748.rtlv_sg.cdb | Bin 0 -> 2657 bytes Exp28/db/YL_dec7748.rtlv_sg_swap.cdb | Bin 0 -> 607 bytes Exp28/db/YL_dec7748.sgdiff.cdb | Bin 0 -> 2800 bytes Exp28/db/YL_dec7748.sgdiff.hdb | Bin 0 -> 9775 bytes Exp28/db/YL_dec7748.sim.hdb | Bin 0 -> 4639 bytes Exp28/db/YL_dec7748.sim.qmsg | 10 + Exp28/db/YL_dec7748.sim.rdb | Bin 0 -> 2597 bytes Exp28/db/YL_dec7748.sim.vwf | 437 +++ Exp28/db/YL_dec7748.sld_design_entry.sci | Bin 0 -> 216 bytes Exp28/db/YL_dec7748.sld_design_entry_dsc.sci | Bin 0 -> 216 bytes Exp28/db/YL_dec7748.smart_action.txt | 1 + Exp28/db/YL_dec7748.sta.qmsg | 34 + Exp28/db/YL_dec7748.sta.rdb | Bin 0 -> 3881 bytes Exp28/db/YL_dec7748.sta_cmp.7_slow.tdb | Bin 0 -> 2666 bytes Exp28/db/YL_dec7748.syn_hier_info | 0 Exp28/db/YL_dec7748.tis_db_list.ddb | Bin 0 -> 191 bytes Exp28/db/YL_dec7748.vpr.ammdb | Bin 0 -> 257 bytes Exp28/db/logic_util_heursitic.dat | Bin 0 -> 968 bytes Exp28/db/prev_cmp_YL_dec7748.qmsg | 5 + Exp28/incremental_db/README | 11 + .../compiled_partitions/YL_dec7748.db_info | 3 + .../YL_dec7748.root_partition.cmp.ammdb | Bin 0 -> 218 bytes .../YL_dec7748.root_partition.cmp.cdb | Bin 0 -> 2900 bytes .../YL_dec7748.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../YL_dec7748.root_partition.cmp.hdb | Bin 0 -> 9681 bytes .../YL_dec7748.root_partition.cmp.kpt | Bin 0 -> 219 bytes .../YL_dec7748.root_partition.cmp.logdb | 1 + .../YL_dec7748.root_partition.cmp.rcfdb | Bin 0 -> 1518 bytes .../YL_dec7748.root_partition.map.cdb | Bin 0 -> 2605 bytes .../YL_dec7748.root_partition.map.dpi | Bin 0 -> 872 bytes .../YL_dec7748.root_partition.map.hbdb.cdb | Bin 0 -> 1299 bytes ...YL_dec7748.root_partition.map.hbdb.hb_info | Bin 0 -> 46 bytes .../YL_dec7748.root_partition.map.hbdb.hdb | Bin 0 -> 9220 bytes .../YL_dec7748.root_partition.map.hbdb.sig | 1 + .../YL_dec7748.root_partition.map.hdb | Bin 0 -> 9463 bytes .../YL_dec7748.root_partition.map.kpt | Bin 0 -> 230 bytes Exp28/output_files/YL_dec7748.asm.rpt | 130 + Exp28/output_files/YL_dec7748.done | 1 + Exp28/output_files/YL_dec7748.fit.rpt | 1165 ++++++++ Exp28/output_files/YL_dec7748.fit.smsg | 8 + Exp28/output_files/YL_dec7748.fit.summary | 16 + Exp28/output_files/YL_dec7748.flow.rpt | 122 + Exp28/output_files/YL_dec7748.jdi | 8 + Exp28/output_files/YL_dec7748.map.rpt | 258 ++ Exp28/output_files/YL_dec7748.map.summary | 14 + Exp28/output_files/YL_dec7748.pin | 554 ++++ Exp28/output_files/YL_dec7748.pof | Bin 0 -> 2097373 bytes Exp28/output_files/YL_dec7748.sim.rpt | 179 ++ Exp28/output_files/YL_dec7748.sof | Bin 0 -> 476065 bytes Exp28/output_files/YL_dec7748.sta.rpt | 444 +++ Exp28/output_files/YL_dec7748.sta.summary | 5 + Exp28/simulation/qsim/YL_dec7748.sim.vwf | 437 +++ Exp28_Decoder/7segment.bsf | 85 + Exp28_Decoder/YL_7SegmentDecoder.bdf | 1195 ++++++++ Exp28_Decoder/YL_7SegmentDecoder.qpf | 30 + Exp28_Decoder/YL_7SegmentDecoder.qsf | 83 + Exp28_Decoder/YL_7SegmentDecoder.qws | Bin 0 -> 5671 bytes Exp28_Decoder/YL_7SegmentDecoder.tdf | 28 + Exp28_Decoder/YL_7SegmentDecoder.vwf | 394 +++ Exp28_Decoder/YL_7SegmentDecoder.vwf.temp | 371 +++ Exp28_Decoder/YL_7SegmentDecoder2.bdf | 160 ++ Exp28_Decoder/YL_7SegmentDecoder2.vwf | 361 +++ Exp28_Decoder/YL_7SegmentDecoder3.vwf | 336 +++ Exp28_Decoder/YL_7SegmentDecoder3.vwf.temp | 321 +++ Exp28_Decoder/YL_7segment_sign.tdf | 25 + Exp28_Decoder/YL_7segment_sign.tdf.bak | 28 + Exp28_Decoder/YL_Cascade.bdf | 1199 ++++++++ Exp28_Decoder/YL_cascade.vwf | 539 ++++ Exp28_Decoder/YL_dec_counter.tdf | 25 + Exp28_Decoder/YL_dec_counter.tdf.bak | 25 + Exp28_Decoder/YL_sec_cnt.tdf | 17 + Exp28_Decoder/YL_sec_cnt.tdf.bak | 17 + .../db/YL_7SegmentDecoder.(0).cnf.cdb | Bin 0 -> 1608 bytes .../db/YL_7SegmentDecoder.(0).cnf.hdb | Bin 0 -> 998 bytes .../db/YL_7SegmentDecoder.(1).cnf.cdb | Bin 0 -> 2418 bytes .../db/YL_7SegmentDecoder.(1).cnf.hdb | Bin 0 -> 515 bytes .../db/YL_7SegmentDecoder.(2).cnf.cdb | Bin 0 -> 2419 bytes .../db/YL_7SegmentDecoder.(2).cnf.hdb | Bin 0 -> 514 bytes .../db/YL_7SegmentDecoder.(3).cnf.cdb | Bin 0 -> 2056 bytes .../db/YL_7SegmentDecoder.(3).cnf.hdb | Bin 0 -> 593 bytes .../db/YL_7SegmentDecoder.(4).cnf.cdb | Bin 0 -> 2823 bytes .../db/YL_7SegmentDecoder.(4).cnf.hdb | Bin 0 -> 620 bytes .../db/YL_7SegmentDecoder.(5).cnf.cdb | Bin 0 -> 2055 bytes .../db/YL_7SegmentDecoder.(5).cnf.hdb | Bin 0 -> 591 bytes Exp28_Decoder/db/YL_7SegmentDecoder.asm.qmsg | 6 + Exp28_Decoder/db/YL_7SegmentDecoder.asm.rdb | Bin 0 -> 1540 bytes .../db/YL_7SegmentDecoder.asm_labs.ddb | Bin 0 -> 8213 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cbx.xml | 5 + Exp28_Decoder/db/YL_7SegmentDecoder.cmp.bpm | Bin 0 -> 706 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp.cdb | Bin 0 -> 16235 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp.hdb | Bin 0 -> 13556 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp.idb | Bin 0 -> 6388 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp.kpt | Bin 0 -> 230 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp.logdb | 1 + Exp28_Decoder/db/YL_7SegmentDecoder.cmp.rdb | Bin 0 -> 20718 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp0.ddb | Bin 0 -> 77958 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp1.ddb | Bin 0 -> 76438 bytes Exp28_Decoder/db/YL_7SegmentDecoder.cmp2.ddb | Bin 0 -> 45260 bytes .../db/YL_7SegmentDecoder.cmp_merge.kpt | Bin 0 -> 234 bytes Exp28_Decoder/db/YL_7SegmentDecoder.db_info | 3 + Exp28_Decoder/db/YL_7SegmentDecoder.eda.qmsg | 5 + .../db/YL_7SegmentDecoder.eds_overflow | 1 + Exp28_Decoder/db/YL_7SegmentDecoder.fit.qmsg | 47 + Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.cdb | Bin 0 -> 7587 bytes Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.hdb | Bin 0 -> 15557 bytes .../db/YL_7SegmentDecoder.fnsim.qmsg | 16 + Exp28_Decoder/db/YL_7SegmentDecoder.hier_info | 237 ++ Exp28_Decoder/db/YL_7SegmentDecoder.hif | Bin 0 -> 619 bytes Exp28_Decoder/db/YL_7SegmentDecoder.ipinfo | Bin 0 -> 177 bytes Exp28_Decoder/db/YL_7SegmentDecoder.lpc.html | 98 + Exp28_Decoder/db/YL_7SegmentDecoder.lpc.rdb | Bin 0 -> 527 bytes Exp28_Decoder/db/YL_7SegmentDecoder.lpc.txt | 11 + Exp28_Decoder/db/YL_7SegmentDecoder.map.ammdb | Bin 0 -> 137 bytes Exp28_Decoder/db/YL_7SegmentDecoder.map.bpm | Bin 0 -> 681 bytes Exp28_Decoder/db/YL_7SegmentDecoder.map.cdb | Bin 0 -> 5726 bytes Exp28_Decoder/db/YL_7SegmentDecoder.map.hdb | Bin 0 -> 12971 bytes Exp28_Decoder/db/YL_7SegmentDecoder.map.kpt | Bin 0 -> 1009 bytes Exp28_Decoder/db/YL_7SegmentDecoder.map.logdb | 1 + Exp28_Decoder/db/YL_7SegmentDecoder.map.qmsg | 18 + Exp28_Decoder/db/YL_7SegmentDecoder.map.rdb | Bin 0 -> 1335 bytes .../db/YL_7SegmentDecoder.map_bb.cdb | Bin 0 -> 1842 bytes .../db/YL_7SegmentDecoder.map_bb.hdb | Bin 0 -> 10326 bytes .../db/YL_7SegmentDecoder.map_bb.logdb | 1 + Exp28_Decoder/db/YL_7SegmentDecoder.pplq.rdb | Bin 0 -> 246 bytes .../db/YL_7SegmentDecoder.pre_map.hdb | Bin 0 -> 12897 bytes .../db/YL_7SegmentDecoder.pti_db_list.ddb | Bin 0 -> 191 bytes ...gmentDecoder.root_partition.map.reg_db.cdb | Bin 0 -> 223 bytes .../db/YL_7SegmentDecoder.routing.rdb | Bin 0 -> 6137 bytes Exp28_Decoder/db/YL_7SegmentDecoder.rpp.qmsg | 4 + Exp28_Decoder/db/YL_7SegmentDecoder.rtlv.hdb | Bin 0 -> 12789 bytes .../db/YL_7SegmentDecoder.rtlv_sg.cdb | Bin 0 -> 8061 bytes .../db/YL_7SegmentDecoder.rtlv_sg_swap.cdb | Bin 0 -> 880 bytes .../db/YL_7SegmentDecoder.sgate_sm.rvd | Bin 0 -> 245 bytes .../db/YL_7SegmentDecoder.sgdiff.cdb | Bin 0 -> 5352 bytes .../db/YL_7SegmentDecoder.sgdiff.hdb | Bin 0 -> 12848 bytes Exp28_Decoder/db/YL_7SegmentDecoder.sim.hdb | Bin 0 -> 5315 bytes Exp28_Decoder/db/YL_7SegmentDecoder.sim.qmsg | 10 + Exp28_Decoder/db/YL_7SegmentDecoder.sim.rdb | Bin 0 -> 5290 bytes Exp28_Decoder/db/YL_7SegmentDecoder.sim.vwf | 809 ++++++ Exp28_Decoder/db/YL_7SegmentDecoder.simfam | 2 + .../YL_7SegmentDecoder.sld_design_entry.sci | Bin 0 -> 216 bytes ...L_7SegmentDecoder.sld_design_entry_dsc.sci | Bin 0 -> 216 bytes .../db/YL_7SegmentDecoder.smart_action.txt | 1 + Exp28_Decoder/db/YL_7SegmentDecoder.sta.qmsg | 30 + Exp28_Decoder/db/YL_7SegmentDecoder.sta.rdb | Bin 0 -> 12896 bytes .../db/YL_7SegmentDecoder.syn_hier_info | 0 .../db/YL_7SegmentDecoder.tis_db_list.ddb | Bin 0 -> 191 bytes Exp28_Decoder/db/YL_7SegmentDecoder.vpr.ammdb | Bin 0 -> 364 bytes Exp28_Decoder/db/logic_util_heursitic.dat | Bin 0 -> 5588 bytes .../db/prev_cmp_YL_7SegmentDecoder.qmsg | 114 + Exp28_Decoder/dec_count.bsf | 71 + Exp28_Decoder/incremental_db/README | 11 + .../YL_7SegmentDecoder.db_info | 3 + ...L_7SegmentDecoder.root_partition.cmp.ammdb | Bin 0 -> 341 bytes .../YL_7SegmentDecoder.root_partition.cmp.cdb | Bin 0 -> 7948 bytes .../YL_7SegmentDecoder.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../YL_7SegmentDecoder.root_partition.cmp.hdb | Bin 0 -> 13146 bytes .../YL_7SegmentDecoder.root_partition.cmp.kpt | Bin 0 -> 219 bytes ...L_7SegmentDecoder.root_partition.cmp.logdb | 1 + ...L_7SegmentDecoder.root_partition.cmp.rcfdb | Bin 0 -> 6741 bytes .../YL_7SegmentDecoder.root_partition.map.cdb | Bin 0 -> 5730 bytes .../YL_7SegmentDecoder.root_partition.map.dpi | Bin 0 -> 1038 bytes ...SegmentDecoder.root_partition.map.hbdb.cdb | Bin 0 -> 1299 bytes ...entDecoder.root_partition.map.hbdb.hb_info | Bin 0 -> 46 bytes ...SegmentDecoder.root_partition.map.hbdb.hdb | Bin 0 -> 12662 bytes ...SegmentDecoder.root_partition.map.hbdb.sig | 1 + .../YL_7SegmentDecoder.root_partition.map.hdb | Bin 0 -> 13098 bytes .../YL_7SegmentDecoder.root_partition.map.kpt | Bin 0 -> 1007 bytes .../output_files/YL_7SegmentDecoder.asm.rpt | 130 + .../output_files/YL_7SegmentDecoder.done | 1 + .../output_files/YL_7SegmentDecoder.eda.rpt | 96 + .../output_files/YL_7SegmentDecoder.fit.rpt | 1365 +++++++++ .../output_files/YL_7SegmentDecoder.fit.smsg | 8 + .../YL_7SegmentDecoder.fit.summary | 16 + .../output_files/YL_7SegmentDecoder.flow.rpt | 128 + .../output_files/YL_7SegmentDecoder.jdi | 8 + .../output_files/YL_7SegmentDecoder.map.rpt | 276 ++ .../YL_7SegmentDecoder.map.summary | 14 + .../output_files/YL_7SegmentDecoder.pin | 554 ++++ .../output_files/YL_7SegmentDecoder.pof | Bin 0 -> 2097373 bytes .../output_files/YL_7SegmentDecoder.sim.rpt | 486 ++++ .../output_files/YL_7SegmentDecoder.sof | Bin 0 -> 476081 bytes .../output_files/YL_7SegmentDecoder.sta.rpt | 1149 ++++++++ .../YL_7SegmentDecoder.sta.summary | 29 + Exp28_Decoder/output_files/YL_adder.done | 1 + Exp28_Decoder/sec_cnt.bsf | 43 + .../modelsim/YL_7SegmentDecoder.sft | 5 + .../simulation/modelsim/YL_7SegmentDecoder.vo | 2504 +++++++++++++++++ .../modelsim/YL_7SegmentDecoder_fast.vo | 2504 +++++++++++++++++ .../modelsim/YL_7SegmentDecoder_modelsim.xrf | 136 + .../modelsim/YL_7SegmentDecoder_v.sdo | 1797 ++++++++++++ .../modelsim/YL_7SegmentDecoder_v_fast.sdo | 1797 ++++++++++++ .../simulation/qsim/YL_7SegmentDecoder.do | 10 + .../qsim/YL_7SegmentDecoder.sim.vwf | 809 ++++++ .../simulation/qsim/YL_7SegmentDecoder.vo | 603 ++++ .../simulation/qsim/YL_7SegmentDecoder.vt | 394 +++ .../simulation/qsim/YL_7SegmentDecoder_v.sdo | 252 ++ YL_adder/YL_adde.vwf | 1005 +++++++ YL_adder/YL_adde.vwf.temp | 862 ++++++ YL_adder/YL_adder.bdf | 1868 ++++++++++++ YL_adder/YL_adder.qpf | 30 + YL_adder/YL_adder.qsf | 95 + YL_adder/YL_adder.qws | Bin 0 -> 6154 bytes YL_adder/YL_encoder.tdf.bak | 36 + YL_adder/db/YL_adder.(0).cnf.cdb | Bin 0 -> 2326 bytes YL_adder/db/YL_adder.(0).cnf.hdb | Bin 0 -> 1754 bytes YL_adder/db/YL_adder.(1).cnf.cdb | Bin 0 -> 1230 bytes YL_adder/db/YL_adder.(1).cnf.hdb | Bin 0 -> 820 bytes YL_adder/db/YL_adder.(2).cnf.cdb | Bin 0 -> 1968 bytes YL_adder/db/YL_adder.(2).cnf.hdb | Bin 0 -> 1247 bytes YL_adder/db/YL_adder.(3).cnf.cdb | Bin 0 -> 2421 bytes YL_adder/db/YL_adder.(3).cnf.hdb | Bin 0 -> 510 bytes YL_adder/db/YL_adder.(4).cnf.cdb | Bin 0 -> 3039 bytes YL_adder/db/YL_adder.(4).cnf.hdb | Bin 0 -> 509 bytes YL_adder/db/YL_adder.(5).cnf.cdb | Bin 0 -> 855 bytes YL_adder/db/YL_adder.(5).cnf.hdb | Bin 0 -> 475 bytes YL_adder/db/YL_adder.(6).cnf.cdb | Bin 0 -> 1097 bytes YL_adder/db/YL_adder.(6).cnf.hdb | Bin 0 -> 498 bytes YL_adder/db/YL_adder.(7).cnf.cdb | Bin 0 -> 939 bytes YL_adder/db/YL_adder.(7).cnf.hdb | Bin 0 -> 445 bytes YL_adder/db/YL_adder.analyze_file.qmsg | 5 + YL_adder/db/YL_adder.asm.qmsg | 6 + YL_adder/db/YL_adder.asm.rdb | Bin 0 -> 1530 bytes YL_adder/db/YL_adder.asm_labs.ddb | Bin 0 -> 7755 bytes YL_adder/db/YL_adder.cbx.xml | 5 + YL_adder/db/YL_adder.cmp.bpm | Bin 0 -> 824 bytes YL_adder/db/YL_adder.cmp.cdb | Bin 0 -> 8467 bytes YL_adder/db/YL_adder.cmp.hdb | Bin 0 -> 13200 bytes YL_adder/db/YL_adder.cmp.idb | Bin 0 -> 2731 bytes YL_adder/db/YL_adder.cmp.kpt | Bin 0 -> 221 bytes YL_adder/db/YL_adder.cmp.logdb | 1 + YL_adder/db/YL_adder.cmp.rdb | Bin 0 -> 21331 bytes YL_adder/db/YL_adder.cmp0.ddb | Bin 0 -> 61636 bytes YL_adder/db/YL_adder.cmp1.ddb | Bin 0 -> 60924 bytes YL_adder/db/YL_adder.cmp2.ddb | Bin 0 -> 43710 bytes YL_adder/db/YL_adder.cmp_merge.kpt | Bin 0 -> 226 bytes YL_adder/db/YL_adder.db_info | 3 + YL_adder/db/YL_adder.eda.qmsg | 5 + YL_adder/db/YL_adder.eds_overflow | 1 + YL_adder/db/YL_adder.fit.qmsg | 46 + YL_adder/db/YL_adder.fnsim.cdb | Bin 0 -> 5936 bytes YL_adder/db/YL_adder.fnsim.hdb | Bin 0 -> 16964 bytes YL_adder/db/YL_adder.fnsim.qmsg | 25 + YL_adder/db/YL_adder.hier_info | 265 ++ YL_adder/db/YL_adder.hif | Bin 0 -> 774 bytes YL_adder/db/YL_adder.ipinfo | Bin 0 -> 177 bytes YL_adder/db/YL_adder.lpc.html | 98 + YL_adder/db/YL_adder.lpc.rdb | Bin 0 -> 532 bytes YL_adder/db/YL_adder.lpc.txt | 11 + YL_adder/db/YL_adder.map.ammdb | Bin 0 -> 137 bytes YL_adder/db/YL_adder.map.bpm | Bin 0 -> 803 bytes YL_adder/db/YL_adder.map.cdb | Bin 0 -> 3981 bytes YL_adder/db/YL_adder.map.hdb | Bin 0 -> 12469 bytes YL_adder/db/YL_adder.map.kpt | Bin 0 -> 396 bytes YL_adder/db/YL_adder.map.logdb | 1 + YL_adder/db/YL_adder.map.qmsg | 29 + YL_adder/db/YL_adder.map.rdb | Bin 0 -> 1328 bytes YL_adder/db/YL_adder.map_bb.cdb | Bin 0 -> 1997 bytes YL_adder/db/YL_adder.map_bb.hdb | Bin 0 -> 10855 bytes YL_adder/db/YL_adder.map_bb.logdb | 1 + YL_adder/db/YL_adder.pplq.rdb | Bin 0 -> 246 bytes YL_adder/db/YL_adder.pre_map.hdb | Bin 0 -> 14432 bytes YL_adder/db/YL_adder.pti_db_list.ddb | Bin 0 -> 191 bytes .../db/YL_adder.root_partition.map.reg_db.cdb | Bin 0 -> 213 bytes YL_adder/db/YL_adder.routing.rdb | Bin 0 -> 5891 bytes YL_adder/db/YL_adder.rtlv.hdb | Bin 0 -> 14362 bytes YL_adder/db/YL_adder.rtlv_sg.cdb | Bin 0 -> 10003 bytes YL_adder/db/YL_adder.rtlv_sg_swap.cdb | Bin 0 -> 1262 bytes YL_adder/db/YL_adder.sgdiff.cdb | Bin 0 -> 5000 bytes YL_adder/db/YL_adder.sgdiff.hdb | Bin 0 -> 13464 bytes YL_adder/db/YL_adder.sim.hdb | Bin 0 -> 5313 bytes YL_adder/db/YL_adder.sim.qmsg | 14 + YL_adder/db/YL_adder.sim.rdb | Bin 0 -> 3946 bytes YL_adder/db/YL_adder.sim.vwf | 1103 ++++++++ YL_adder/db/YL_adder.simfam | 2 + YL_adder/db/YL_adder.sld_design_entry.sci | Bin 0 -> 216 bytes YL_adder/db/YL_adder.sld_design_entry_dsc.sci | Bin 0 -> 216 bytes YL_adder/db/YL_adder.smart_action.txt | 1 + YL_adder/db/YL_adder.sta.qmsg | 31 + YL_adder/db/YL_adder.sta.rdb | Bin 0 -> 6425 bytes YL_adder/db/YL_adder.syn_hier_info | 0 YL_adder/db/YL_adder.tis_db_list.ddb | Bin 0 -> 191 bytes YL_adder/db/YL_adder.vpr.ammdb | Bin 0 -> 337 bytes YL_adder/db/logic_util_heursitic.dat | Bin 0 -> 2772 bytes YL_adder/db/prev_cmp_YL_adder.qmsg | 125 + YL_adder/encoder.bsf | 71 + YL_adder/encoder.tdf | 36 + YL_adder/incremental_db/README | 11 + .../compiled_partitions/YL_adder.db_info | 3 + .../YL_adder.root_partition.cmp.ammdb | Bin 0 -> 330 bytes .../YL_adder.root_partition.cmp.cdb | Bin 0 -> 4980 bytes .../YL_adder.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../YL_adder.root_partition.cmp.hdb | Bin 0 -> 12613 bytes .../YL_adder.root_partition.cmp.kpt | Bin 0 -> 219 bytes .../YL_adder.root_partition.cmp.logdb | 1 + .../YL_adder.root_partition.cmp.rcfdb | Bin 0 -> 3608 bytes .../YL_adder.root_partition.map.cdb | Bin 0 -> 4006 bytes .../YL_adder.root_partition.map.dpi | Bin 0 -> 1402 bytes .../YL_adder.root_partition.map.hbdb.cdb | Bin 0 -> 1299 bytes .../YL_adder.root_partition.map.hbdb.hb_info | Bin 0 -> 46 bytes .../YL_adder.root_partition.map.hbdb.hdb | Bin 0 -> 12166 bytes .../YL_adder.root_partition.map.hbdb.sig | 1 + .../YL_adder.root_partition.map.hdb | Bin 0 -> 12784 bytes .../YL_adder.root_partition.map.kpt | Bin 0 -> 398 bytes YL_adder/operator.bsf | 92 + YL_adder/operator.tdf | 21 + YL_adder/operator.tdf.bak | 5 + YL_adder/output_files/YL_adder.asm.rpt | 130 + YL_adder/output_files/YL_adder.done | 1 + YL_adder/output_files/YL_adder.eda.rpt | 96 + YL_adder/output_files/YL_adder.fit.rpt | 1325 +++++++++ YL_adder/output_files/YL_adder.fit.smsg | 8 + YL_adder/output_files/YL_adder.fit.summary | 16 + YL_adder/output_files/YL_adder.flow.rpt | 128 + YL_adder/output_files/YL_adder.jdi | 8 + YL_adder/output_files/YL_adder.map.rpt | 299 ++ YL_adder/output_files/YL_adder.map.summary | 14 + YL_adder/output_files/YL_adder.pin | 554 ++++ YL_adder/output_files/YL_adder.pof | Bin 0 -> 2097373 bytes YL_adder/output_files/YL_adder.sim.rpt | 335 +++ YL_adder/output_files/YL_adder.sof | Bin 0 -> 476061 bytes YL_adder/output_files/YL_adder.sta.rpt | 667 +++++ YL_adder/output_files/YL_adder.sta.summary | 13 + YL_adder/overflow.bsf | 57 + YL_adder/overflow.tdf | 12 + YL_adder/segment.bsf | 85 + YL_adder/segment.tdf | 28 + YL_adder/sign.bsf | 85 + YL_adder/sign.tdf | 25 + YL_adder/simulation/modelsim/YL_adder.sft | 5 + YL_adder/simulation/modelsim/YL_adder.vo | 1747 ++++++++++++ YL_adder/simulation/modelsim/YL_adder_fast.vo | 1747 ++++++++++++ .../simulation/modelsim/YL_adder_modelsim.xrf | 75 + YL_adder/simulation/modelsim/YL_adder_v.sdo | 765 +++++ .../simulation/modelsim/YL_adder_v_fast.sdo | 765 +++++ YL_adder/simulation/qsim/YL_adder.do | 10 + YL_adder/simulation/qsim/YL_adder.sim.vwf | 1103 ++++++++ YL_adder/simulation/qsim/YL_adder.vo | 1561 ++++++++++ YL_adder/simulation/qsim/YL_adder.vt | 758 +++++ YL_adder/simulation/qsim/YL_adder_v.sdo | 690 +++++ YL_dec_counter/YL_DecCounter.vwf | 327 +++ YL_dec_counter/YL_DecCounter.vwf.temp | 326 +++ YL_dec_counter/YL_dec_counter.bdf | 101 + YL_dec_counter/YL_dec_counter.qpf | 30 + YL_dec_counter/YL_dec_counter.qsf | 64 + YL_dec_counter/YL_dec_counter.qws | Bin 0 -> 2320 bytes YL_dec_counter/YL_dec_counter.tdf | 25 + YL_dec_counter/YL_dec_counter.tdf.bak | 0 YL_dec_counter/db/YL_dec_counter.(0).cnf.cdb | Bin 0 -> 935 bytes YL_dec_counter/db/YL_dec_counter.(0).cnf.hdb | Bin 0 -> 727 bytes YL_dec_counter/db/YL_dec_counter.(1).cnf.cdb | Bin 0 -> 2104 bytes YL_dec_counter/db/YL_dec_counter.(1).cnf.hdb | Bin 0 -> 590 bytes YL_dec_counter/db/YL_dec_counter.asm.qmsg | 6 + YL_dec_counter/db/YL_dec_counter.asm.rdb | Bin 0 -> 1528 bytes YL_dec_counter/db/YL_dec_counter.asm_labs.ddb | Bin 0 -> 6618 bytes YL_dec_counter/db/YL_dec_counter.cbx.xml | 5 + YL_dec_counter/db/YL_dec_counter.cmp.bpm | Bin 0 -> 619 bytes YL_dec_counter/db/YL_dec_counter.cmp.cdb | Bin 0 -> 5779 bytes YL_dec_counter/db/YL_dec_counter.cmp.hdb | Bin 0 -> 10548 bytes YL_dec_counter/db/YL_dec_counter.cmp.idb | Bin 0 -> 2216 bytes YL_dec_counter/db/YL_dec_counter.cmp.kpt | Bin 0 -> 225 bytes YL_dec_counter/db/YL_dec_counter.cmp.logdb | 1 + YL_dec_counter/db/YL_dec_counter.cmp.rdb | Bin 0 -> 19516 bytes YL_dec_counter/db/YL_dec_counter.cmp0.ddb | Bin 0 -> 51925 bytes YL_dec_counter/db/YL_dec_counter.cmp1.ddb | Bin 0 -> 51628 bytes YL_dec_counter/db/YL_dec_counter.cmp2.ddb | Bin 0 -> 41174 bytes .../db/YL_dec_counter.cmp_merge.kpt | Bin 0 -> 230 bytes YL_dec_counter/db/YL_dec_counter.db_info | 3 + YL_dec_counter/db/YL_dec_counter.eda.qmsg | 5 + YL_dec_counter/db/YL_dec_counter.eds_overflow | 1 + YL_dec_counter/db/YL_dec_counter.fit.qmsg | 45 + YL_dec_counter/db/YL_dec_counter.fnsim.cdb | Bin 0 -> 2998 bytes YL_dec_counter/db/YL_dec_counter.fnsim.hdb | Bin 0 -> 10451 bytes YL_dec_counter/db/YL_dec_counter.fnsim.qmsg | 9 + YL_dec_counter/db/YL_dec_counter.hier_info | 30 + YL_dec_counter/db/YL_dec_counter.hif | Bin 0 -> 451 bytes YL_dec_counter/db/YL_dec_counter.ipinfo | Bin 0 -> 177 bytes YL_dec_counter/db/YL_dec_counter.lpc.html | 34 + YL_dec_counter/db/YL_dec_counter.lpc.rdb | Bin 0 -> 450 bytes YL_dec_counter/db/YL_dec_counter.lpc.txt | 7 + YL_dec_counter/db/YL_dec_counter.map.ammdb | Bin 0 -> 137 bytes YL_dec_counter/db/YL_dec_counter.map.bpm | Bin 0 -> 594 bytes YL_dec_counter/db/YL_dec_counter.map.cdb | Bin 0 -> 3066 bytes YL_dec_counter/db/YL_dec_counter.map.hdb | Bin 0 -> 9719 bytes YL_dec_counter/db/YL_dec_counter.map.kpt | Bin 0 -> 409 bytes YL_dec_counter/db/YL_dec_counter.map.logdb | 1 + YL_dec_counter/db/YL_dec_counter.map.qmsg | 11 + YL_dec_counter/db/YL_dec_counter.map.rdb | Bin 0 -> 1332 bytes YL_dec_counter/db/YL_dec_counter.map_bb.cdb | Bin 0 -> 1796 bytes YL_dec_counter/db/YL_dec_counter.map_bb.hdb | Bin 0 -> 8613 bytes YL_dec_counter/db/YL_dec_counter.map_bb.logdb | 1 + YL_dec_counter/db/YL_dec_counter.pre_map.hdb | Bin 0 -> 9739 bytes .../db/YL_dec_counter.pti_db_list.ddb | Bin 0 -> 191 bytes ..._dec_counter.root_partition.map.reg_db.cdb | Bin 0 -> 219 bytes YL_dec_counter/db/YL_dec_counter.routing.rdb | Bin 0 -> 4746 bytes YL_dec_counter/db/YL_dec_counter.rtlv.hdb | Bin 0 -> 9707 bytes YL_dec_counter/db/YL_dec_counter.rtlv_sg.cdb | Bin 0 -> 2500 bytes .../db/YL_dec_counter.rtlv_sg_swap.cdb | Bin 0 -> 560 bytes YL_dec_counter/db/YL_dec_counter.sgdiff.cdb | Bin 0 -> 2968 bytes YL_dec_counter/db/YL_dec_counter.sgdiff.hdb | Bin 0 -> 9742 bytes YL_dec_counter/db/YL_dec_counter.sim.hdb | Bin 0 -> 4782 bytes YL_dec_counter/db/YL_dec_counter.sim.qmsg | 10 + YL_dec_counter/db/YL_dec_counter.sim.rdb | Bin 0 -> 2869 bytes YL_dec_counter/db/YL_dec_counter.sim.vwf | 348 +++ YL_dec_counter/db/YL_dec_counter.simfam | 2 + .../db/YL_dec_counter.sld_design_entry.sci | Bin 0 -> 216 bytes .../YL_dec_counter.sld_design_entry_dsc.sci | Bin 0 -> 216 bytes .../db/YL_dec_counter.smart_action.txt | 1 + YL_dec_counter/db/YL_dec_counter.sta.qmsg | 30 + YL_dec_counter/db/YL_dec_counter.sta.rdb | Bin 0 -> 7969 bytes .../db/YL_dec_counter.syn_hier_info | 0 .../db/YL_dec_counter.tis_db_list.ddb | Bin 0 -> 191 bytes YL_dec_counter/db/YL_dec_counter.vpr.ammdb | Bin 0 -> 258 bytes YL_dec_counter/db/logic_util_heursitic.dat | Bin 0 -> 1320 bytes .../db/prev_cmp_YL_dec_counter.qmsg | 4 + YL_dec_counter/dec_count.bsf | 71 + YL_dec_counter/incremental_db/README | 11 + .../YL_dec_counter.db_info | 3 + .../YL_dec_counter.root_partition.cmp.ammdb | Bin 0 -> 260 bytes .../YL_dec_counter.root_partition.cmp.cdb | Bin 0 -> 3721 bytes .../YL_dec_counter.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../YL_dec_counter.root_partition.cmp.hdb | Bin 0 -> 9882 bytes .../YL_dec_counter.root_partition.cmp.kpt | Bin 0 -> 219 bytes .../YL_dec_counter.root_partition.cmp.logdb | 1 + .../YL_dec_counter.root_partition.cmp.rcfdb | Bin 0 -> 1856 bytes .../YL_dec_counter.root_partition.map.cdb | Bin 0 -> 2962 bytes .../YL_dec_counter.root_partition.map.dpi | Bin 0 -> 803 bytes ...YL_dec_counter.root_partition.map.hbdb.cdb | Bin 0 -> 1300 bytes ...ec_counter.root_partition.map.hbdb.hb_info | Bin 0 -> 46 bytes ...YL_dec_counter.root_partition.map.hbdb.hdb | Bin 0 -> 9396 bytes ...YL_dec_counter.root_partition.map.hbdb.sig | 1 + .../YL_dec_counter.root_partition.map.hdb | Bin 0 -> 9604 bytes .../YL_dec_counter.root_partition.map.kpt | Bin 0 -> 412 bytes .../output_files/YL_dec_counter.asm.rpt | 130 + .../output_files/YL_dec_counter.done | 1 + .../output_files/YL_dec_counter.eda.rpt | 92 + .../output_files/YL_dec_counter.fit.rpt | 1191 ++++++++ .../output_files/YL_dec_counter.fit.smsg | 8 + .../output_files/YL_dec_counter.fit.summary | 16 + .../output_files/YL_dec_counter.flow.rpt | 128 + .../output_files/YL_dec_counter.jdi | 8 + .../output_files/YL_dec_counter.map.rpt | 259 ++ .../output_files/YL_dec_counter.map.summary | 14 + .../output_files/YL_dec_counter.pin | 554 ++++ .../output_files/YL_dec_counter.pof | Bin 0 -> 2097373 bytes .../output_files/YL_dec_counter.sim.rpt | 211 ++ .../output_files/YL_dec_counter.sof | Bin 0 -> 476073 bytes .../output_files/YL_dec_counter.sta.rpt | 677 +++++ .../output_files/YL_dec_counter.sta.summary | 29 + .../simulation/modelsim/YL_dec_counter.sft | 1 + .../simulation/modelsim/YL_dec_counter.vo | 681 +++++ .../modelsim/YL_dec_counter_modelsim.xrf | 32 + .../simulation/qsim/YL_dec_counter.do | 10 + .../simulation/qsim/YL_dec_counter.sim.vwf | 348 +++ .../simulation/qsim/YL_dec_counter.vo | 681 +++++ .../simulation/qsim/YL_dec_counter.vt | 306 ++ YL_pulsar/YL_pulsar.bdf | 162 ++ YL_pulsar/YL_pulsar.qpf | 30 + YL_pulsar/YL_pulsar.qsf | 66 + YL_pulsar/YL_pulsar.qws | Bin 0 -> 3046 bytes YL_pulsar/YL_pulsar.tdf | 35 + YL_pulsar/YL_pulsar.tdf.bak | 0 YL_pulsar/YL_pulsar.vwf | 191 ++ YL_pulsar/YL_pulsar.vwf.temp | 224 ++ YL_pulsar/db/YL_pulsar.(0).cnf.cdb | Bin 0 -> 845 bytes YL_pulsar/db/YL_pulsar.(0).cnf.hdb | Bin 0 -> 587 bytes YL_pulsar/db/YL_pulsar.(1).cnf.cdb | Bin 0 -> 1659 bytes YL_pulsar/db/YL_pulsar.(1).cnf.hdb | Bin 0 -> 521 bytes YL_pulsar/db/YL_pulsar.analyze_file.qmsg | 5 + YL_pulsar/db/YL_pulsar.asm.qmsg | 6 + YL_pulsar/db/YL_pulsar.asm.rdb | Bin 0 -> 1524 bytes YL_pulsar/db/YL_pulsar.asm_labs.ddb | Bin 0 -> 6455 bytes YL_pulsar/db/YL_pulsar.cbx.xml | 5 + YL_pulsar/db/YL_pulsar.cmp.bpm | Bin 0 -> 560 bytes YL_pulsar/db/YL_pulsar.cmp.cdb | Bin 0 -> 3782 bytes YL_pulsar/db/YL_pulsar.cmp.hdb | Bin 0 -> 10002 bytes YL_pulsar/db/YL_pulsar.cmp.idb | Bin 0 -> 1393 bytes YL_pulsar/db/YL_pulsar.cmp.kpt | Bin 0 -> 222 bytes YL_pulsar/db/YL_pulsar.cmp.logdb | 1 + YL_pulsar/db/YL_pulsar.cmp.rdb | Bin 0 -> 19345 bytes YL_pulsar/db/YL_pulsar.cmp0.ddb | Bin 0 -> 47094 bytes YL_pulsar/db/YL_pulsar.cmp1.ddb | Bin 0 -> 46670 bytes YL_pulsar/db/YL_pulsar.cmp2.ddb | Bin 0 -> 40309 bytes YL_pulsar/db/YL_pulsar.cmp_merge.kpt | Bin 0 -> 227 bytes YL_pulsar/db/YL_pulsar.db_info | 3 + YL_pulsar/db/YL_pulsar.eda.qmsg | 5 + YL_pulsar/db/YL_pulsar.eds_overflow | 1 + YL_pulsar/db/YL_pulsar.fit.qmsg | 46 + YL_pulsar/db/YL_pulsar.fnsim.cdb | Bin 0 -> 3138 bytes YL_pulsar/db/YL_pulsar.fnsim.hdb | Bin 0 -> 10113 bytes YL_pulsar/db/YL_pulsar.fnsim.qmsg | 9 + YL_pulsar/db/YL_pulsar.hier_info | 21 + YL_pulsar/db/YL_pulsar.hif | Bin 0 -> 428 bytes YL_pulsar/db/YL_pulsar.ipinfo | Bin 0 -> 177 bytes YL_pulsar/db/YL_pulsar.lpc.html | 34 + YL_pulsar/db/YL_pulsar.lpc.rdb | Bin 0 -> 449 bytes YL_pulsar/db/YL_pulsar.lpc.txt | 7 + YL_pulsar/db/YL_pulsar.map.ammdb | Bin 0 -> 137 bytes YL_pulsar/db/YL_pulsar.map.bpm | Bin 0 -> 537 bytes YL_pulsar/db/YL_pulsar.map.cdb | Bin 0 -> 2429 bytes YL_pulsar/db/YL_pulsar.map.hdb | Bin 0 -> 9336 bytes YL_pulsar/db/YL_pulsar.map.kpt | Bin 0 -> 666 bytes YL_pulsar/db/YL_pulsar.map.logdb | 1 + YL_pulsar/db/YL_pulsar.map.qmsg | 13 + YL_pulsar/db/YL_pulsar.map.rdb | Bin 0 -> 1318 bytes YL_pulsar/db/YL_pulsar.map_bb.cdb | Bin 0 -> 1731 bytes YL_pulsar/db/YL_pulsar.map_bb.hdb | Bin 0 -> 8526 bytes YL_pulsar/db/YL_pulsar.map_bb.logdb | 1 + YL_pulsar/db/YL_pulsar.pplq.rdb | Bin 0 -> 246 bytes YL_pulsar/db/YL_pulsar.pre_map.hdb | Bin 0 -> 9518 bytes YL_pulsar/db/YL_pulsar.pti_db_list.ddb | Bin 0 -> 191 bytes .../YL_pulsar.root_partition.map.reg_db.cdb | Bin 0 -> 325 bytes YL_pulsar/db/YL_pulsar.routing.rdb | Bin 0 -> 4475 bytes YL_pulsar/db/YL_pulsar.rpp.qmsg | 4 + YL_pulsar/db/YL_pulsar.rtlv.hdb | Bin 0 -> 9456 bytes YL_pulsar/db/YL_pulsar.rtlv_sg.cdb | Bin 0 -> 2053 bytes YL_pulsar/db/YL_pulsar.rtlv_sg_swap.cdb | Bin 0 -> 505 bytes YL_pulsar/db/YL_pulsar.sgate.rvd | Bin 0 -> 1569 bytes YL_pulsar/db/YL_pulsar.sgate_sm.rvd | Bin 0 -> 1989 bytes YL_pulsar/db/YL_pulsar.sgdiff.cdb | Bin 0 -> 2149 bytes YL_pulsar/db/YL_pulsar.sgdiff.hdb | Bin 0 -> 9593 bytes YL_pulsar/db/YL_pulsar.sim.hdb | Bin 0 -> 4764 bytes YL_pulsar/db/YL_pulsar.sim.qmsg | 11 + YL_pulsar/db/YL_pulsar.sim.rdb | Bin 0 -> 2553 bytes YL_pulsar/db/YL_pulsar.sim.vwf | 207 ++ YL_pulsar/db/YL_pulsar.simfam | 2 + YL_pulsar/db/YL_pulsar.sld_design_entry.sci | Bin 0 -> 216 bytes .../db/YL_pulsar.sld_design_entry_dsc.sci | Bin 0 -> 216 bytes YL_pulsar/db/YL_pulsar.smart_action.txt | 1 + YL_pulsar/db/YL_pulsar.smp_dump.txt | 7 + YL_pulsar/db/YL_pulsar.sta.qmsg | 30 + YL_pulsar/db/YL_pulsar.sta.rdb | Bin 0 -> 6303 bytes YL_pulsar/db/YL_pulsar.syn_hier_info | 0 YL_pulsar/db/YL_pulsar.tis_db_list.ddb | Bin 0 -> 191 bytes YL_pulsar/db/YL_pulsar.vpr.ammdb | Bin 0 -> 258 bytes YL_pulsar/db/logic_util_heursitic.dat | Bin 0 -> 704 bytes YL_pulsar/db/prev_cmp_YL_pulsar.qmsg | 11 + YL_pulsar/incremental_db/README | 11 + .../compiled_partitions/YL_pulsar.db_info | 3 + .../YL_pulsar.root_partition.cmp.ammdb | Bin 0 -> 266 bytes .../YL_pulsar.root_partition.cmp.cdb | Bin 0 -> 2791 bytes .../YL_pulsar.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../YL_pulsar.root_partition.cmp.hdb | Bin 0 -> 9506 bytes .../YL_pulsar.root_partition.cmp.kpt | Bin 0 -> 219 bytes .../YL_pulsar.root_partition.cmp.logdb | 1 + .../YL_pulsar.root_partition.cmp.rcfdb | Bin 0 -> 1074 bytes .../YL_pulsar.root_partition.map.cdb | Bin 0 -> 2299 bytes .../YL_pulsar.root_partition.map.dpi | Bin 0 -> 776 bytes .../YL_pulsar.root_partition.map.hbdb.cdb | Bin 0 -> 1299 bytes .../YL_pulsar.root_partition.map.hbdb.hb_info | Bin 0 -> 46 bytes .../YL_pulsar.root_partition.map.hbdb.hdb | Bin 0 -> 9017 bytes .../YL_pulsar.root_partition.map.hbdb.sig | 1 + .../YL_pulsar.root_partition.map.hdb | Bin 0 -> 9310 bytes .../YL_pulsar.root_partition.map.kpt | Bin 0 -> 647 bytes YL_pulsar/output_files/YL_pulsar.asm.rpt | 130 + YL_pulsar/output_files/YL_pulsar.done | 1 + YL_pulsar/output_files/YL_pulsar.eda.rpt | 92 + YL_pulsar/output_files/YL_pulsar.fit.rpt | 1138 ++++++++ YL_pulsar/output_files/YL_pulsar.fit.smsg | 8 + YL_pulsar/output_files/YL_pulsar.fit.summary | 16 + YL_pulsar/output_files/YL_pulsar.flow.rpt | 128 + YL_pulsar/output_files/YL_pulsar.jdi | 8 + YL_pulsar/output_files/YL_pulsar.map.rpt | 286 ++ YL_pulsar/output_files/YL_pulsar.map.summary | 14 + YL_pulsar/output_files/YL_pulsar.pin | 554 ++++ YL_pulsar/output_files/YL_pulsar.pof | Bin 0 -> 2097373 bytes YL_pulsar/output_files/YL_pulsar.sim.rpt | 174 ++ YL_pulsar/output_files/YL_pulsar.sof | Bin 0 -> 476063 bytes YL_pulsar/output_files/YL_pulsar.sta.rpt | 511 ++++ YL_pulsar/output_files/YL_pulsar.sta.summary | 29 + YL_pulsar/pulsar.bsf | 57 + YL_pulsar/simulation/modelsim/YL_pulsar.sft | 1 + YL_pulsar/simulation/modelsim/YL_pulsar.vo | 332 +++ .../modelsim/YL_pulsar_modelsim.xrf | 18 + YL_pulsar/simulation/qsim/YL_pulsar.do | 10 + YL_pulsar/simulation/qsim/YL_pulsar.sim.vwf | 207 ++ YL_pulsar/simulation/qsim/YL_pulsar.vo | 332 +++ YL_pulsar/simulation/qsim/YL_pulsar.vt | 270 ++ YL_pushcounter/7segment.bsf | 85 + YL_pushcounter/YL_7segment.tdf | 28 + YL_pushcounter/YL_counter.tdf | 25 + YL_pushcounter/YL_counter.tdf.bak | 25 + YL_pushcounter/YL_pushcounter.bdf | 828 ++++++ YL_pushcounter/YL_pushcounter.qpf | 30 + YL_pushcounter/YL_pushcounter.qsf | 74 + YL_pushcounter/YL_pushcounter.qws | Bin 0 -> 6568 bytes YL_pushcounter/YL_pushcounter.tdf | 35 + YL_pushcounter/YL_pushcounter.vwf | 499 ++++ YL_pushcounter/db/YL_pushcounter.(0).cnf.cdb | Bin 0 -> 1470 bytes YL_pushcounter/db/YL_pushcounter.(0).cnf.hdb | Bin 0 -> 987 bytes YL_pushcounter/db/YL_pushcounter.(1).cnf.cdb | Bin 0 -> 2102 bytes YL_pushcounter/db/YL_pushcounter.(1).cnf.hdb | Bin 0 -> 590 bytes YL_pushcounter/db/YL_pushcounter.(2).cnf.cdb | Bin 0 -> 1659 bytes YL_pushcounter/db/YL_pushcounter.(2).cnf.hdb | Bin 0 -> 519 bytes YL_pushcounter/db/YL_pushcounter.(3).cnf.cdb | Bin 0 -> 2421 bytes YL_pushcounter/db/YL_pushcounter.(3).cnf.hdb | Bin 0 -> 526 bytes YL_pushcounter/db/YL_pushcounter.asm.qmsg | 6 + YL_pushcounter/db/YL_pushcounter.asm.rdb | Bin 0 -> 1529 bytes YL_pushcounter/db/YL_pushcounter.asm_labs.ddb | Bin 0 -> 7111 bytes YL_pushcounter/db/YL_pushcounter.cbx.xml | 5 + YL_pushcounter/db/YL_pushcounter.cmp.bpm | Bin 0 -> 683 bytes YL_pushcounter/db/YL_pushcounter.cmp.cdb | Bin 0 -> 7807 bytes YL_pushcounter/db/YL_pushcounter.cmp.hdb | Bin 0 -> 11076 bytes YL_pushcounter/db/YL_pushcounter.cmp.idb | Bin 0 -> 2995 bytes YL_pushcounter/db/YL_pushcounter.cmp.kpt | Bin 0 -> 226 bytes YL_pushcounter/db/YL_pushcounter.cmp.logdb | 1 + YL_pushcounter/db/YL_pushcounter.cmp.rdb | Bin 0 -> 19391 bytes YL_pushcounter/db/YL_pushcounter.cmp0.ddb | Bin 0 -> 58223 bytes YL_pushcounter/db/YL_pushcounter.cmp1.ddb | Bin 0 -> 57683 bytes YL_pushcounter/db/YL_pushcounter.cmp2.ddb | Bin 0 -> 42645 bytes .../db/YL_pushcounter.cmp_merge.kpt | Bin 0 -> 230 bytes YL_pushcounter/db/YL_pushcounter.db_info | 3 + YL_pushcounter/db/YL_pushcounter.eds_overflow | 1 + YL_pushcounter/db/YL_pushcounter.fit.qmsg | 46 + YL_pushcounter/db/YL_pushcounter.hier_info | 126 + YL_pushcounter/db/YL_pushcounter.hif | Bin 0 -> 595 bytes YL_pushcounter/db/YL_pushcounter.ipinfo | Bin 0 -> 177 bytes YL_pushcounter/db/YL_pushcounter.lpc.html | 66 + YL_pushcounter/db/YL_pushcounter.lpc.rdb | Bin 0 -> 500 bytes YL_pushcounter/db/YL_pushcounter.lpc.txt | 9 + YL_pushcounter/db/YL_pushcounter.map.ammdb | Bin 0 -> 137 bytes YL_pushcounter/db/YL_pushcounter.map.bpm | Bin 0 -> 665 bytes YL_pushcounter/db/YL_pushcounter.map.cdb | Bin 0 -> 3716 bytes YL_pushcounter/db/YL_pushcounter.map.hdb | Bin 0 -> 10462 bytes YL_pushcounter/db/YL_pushcounter.map.kpt | Bin 0 -> 784 bytes YL_pushcounter/db/YL_pushcounter.map.logdb | 1 + YL_pushcounter/db/YL_pushcounter.map.qmsg | 17 + YL_pushcounter/db/YL_pushcounter.map.rdb | Bin 0 -> 1328 bytes YL_pushcounter/db/YL_pushcounter.map_bb.cdb | Bin 0 -> 1872 bytes YL_pushcounter/db/YL_pushcounter.map_bb.hdb | Bin 0 -> 9071 bytes YL_pushcounter/db/YL_pushcounter.map_bb.logdb | 1 + YL_pushcounter/db/YL_pushcounter.pplq.rdb | Bin 0 -> 246 bytes YL_pushcounter/db/YL_pushcounter.pre_map.hdb | Bin 0 -> 10876 bytes .../db/YL_pushcounter.pti_db_list.ddb | Bin 0 -> 191 bytes ..._pushcounter.root_partition.map.reg_db.cdb | Bin 0 -> 330 bytes YL_pushcounter/db/YL_pushcounter.routing.rdb | Bin 0 -> 5171 bytes YL_pushcounter/db/YL_pushcounter.rtlv.hdb | Bin 0 -> 10813 bytes YL_pushcounter/db/YL_pushcounter.rtlv_sg.cdb | Bin 0 -> 6157 bytes .../db/YL_pushcounter.rtlv_sg_swap.cdb | Bin 0 -> 806 bytes YL_pushcounter/db/YL_pushcounter.sgdiff.cdb | Bin 0 -> 3364 bytes YL_pushcounter/db/YL_pushcounter.sgdiff.hdb | Bin 0 -> 10649 bytes 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YL_pushcounter/db/YL_pushcounter.map.qmsg create mode 100644 YL_pushcounter/db/YL_pushcounter.map.rdb create mode 100644 YL_pushcounter/db/YL_pushcounter.map_bb.cdb create mode 100644 YL_pushcounter/db/YL_pushcounter.map_bb.hdb create mode 100644 YL_pushcounter/db/YL_pushcounter.map_bb.logdb create mode 100644 YL_pushcounter/db/YL_pushcounter.pplq.rdb create mode 100644 YL_pushcounter/db/YL_pushcounter.pre_map.hdb create mode 100644 YL_pushcounter/db/YL_pushcounter.pti_db_list.ddb create mode 100644 YL_pushcounter/db/YL_pushcounter.root_partition.map.reg_db.cdb create mode 100644 YL_pushcounter/db/YL_pushcounter.routing.rdb create mode 100644 YL_pushcounter/db/YL_pushcounter.rtlv.hdb create mode 100644 YL_pushcounter/db/YL_pushcounter.rtlv_sg.cdb create mode 100644 YL_pushcounter/db/YL_pushcounter.rtlv_sg_swap.cdb create mode 100644 YL_pushcounter/db/YL_pushcounter.sgdiff.cdb create mode 100644 YL_pushcounter/db/YL_pushcounter.sgdiff.hdb create mode 100644 YL_pushcounter/db/YL_pushcounter.sim.hdb create mode 100644 YL_pushcounter/db/YL_pushcounter.sim.qmsg create mode 100644 YL_pushcounter/db/YL_pushcounter.sim.rdb create mode 100644 YL_pushcounter/db/YL_pushcounter.sim.vwf create mode 100644 YL_pushcounter/db/YL_pushcounter.sld_design_entry.sci create mode 100644 YL_pushcounter/db/YL_pushcounter.sld_design_entry_dsc.sci create mode 100644 YL_pushcounter/db/YL_pushcounter.smart_action.txt create mode 100644 YL_pushcounter/db/YL_pushcounter.smp_dump.txt create mode 100644 YL_pushcounter/db/YL_pushcounter.sta.qmsg create mode 100644 YL_pushcounter/db/YL_pushcounter.sta.rdb create mode 100644 YL_pushcounter/db/YL_pushcounter.sta_cmp.7_slow.tdb create mode 100644 YL_pushcounter/db/YL_pushcounter.syn_hier_info create mode 100644 YL_pushcounter/db/YL_pushcounter.tis_db_list.ddb create mode 100644 YL_pushcounter/db/YL_pushcounter.vpr.ammdb create mode 100644 YL_pushcounter/db/logic_util_heursitic.dat create mode 100644 YL_pushcounter/db/prev_cmp_YL_pushcounter.qmsg create mode 100644 YL_pushcounter/dec_count.bsf create mode 100644 YL_pushcounter/incremental_db/README create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.db_info create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.ammdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.cdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.dfp create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.hdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.kpt create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.logdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.rcfdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.cdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.dpi create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.hbdb.cdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.hbdb.hb_info create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.hbdb.hdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.hbdb.sig create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.hdb create mode 100644 YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.map.kpt create mode 100644 YL_pushcounter/output_files/YL_pushcounter.asm.rpt create mode 100644 YL_pushcounter/output_files/YL_pushcounter.done create mode 100644 YL_pushcounter/output_files/YL_pushcounter.fit.rpt create mode 100644 YL_pushcounter/output_files/YL_pushcounter.fit.smsg create mode 100644 YL_pushcounter/output_files/YL_pushcounter.fit.summary create mode 100644 YL_pushcounter/output_files/YL_pushcounter.flow.rpt create mode 100644 YL_pushcounter/output_files/YL_pushcounter.jdi create mode 100644 YL_pushcounter/output_files/YL_pushcounter.map.rpt create mode 100644 YL_pushcounter/output_files/YL_pushcounter.map.summary create mode 100644 YL_pushcounter/output_files/YL_pushcounter.pin create mode 100644 YL_pushcounter/output_files/YL_pushcounter.pof create mode 100644 YL_pushcounter/output_files/YL_pushcounter.sim.rpt create mode 100644 YL_pushcounter/output_files/YL_pushcounter.sof create mode 100644 YL_pushcounter/output_files/YL_pushcounter.sta.rpt create mode 100644 YL_pushcounter/output_files/YL_pushcounter.sta.summary create mode 100644 YL_pushcounter/pulsar.bsf create mode 100644 YL_pushcounter/simulation/qsim/YL_pushcounter.sim.vwf diff --git a/Exp28/YL_7448.vwf b/Exp28/YL_7448.vwf new file mode 100644 index 0000000..cbbfa5c --- /dev/null +++ b/Exp28/YL_7448.vwf @@ -0,0 +1,367 @@ +/* Simulator = Quartus II Simulator */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("INPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("INPUT_A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_C") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28/YL_7448.vwf.temp b/Exp28/YL_7448.vwf.temp new file mode 100644 index 0000000..cbbfa5c --- /dev/null +++ b/Exp28/YL_7448.vwf.temp @@ -0,0 +1,367 @@ +/* Simulator = Quartus II Simulator */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("INPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("INPUT_A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_C") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28/YL_dec7748.bdf b/Exp28/YL_dec7748.bdf new file mode 100644 index 0000000..598cdec --- /dev/null +++ b/Exp28/YL_dec7748.bdf @@ -0,0 +1,403 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 320 240 488 256) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "INPUT_A" (rect 5 0 52 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 320 256 488 272) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "INPUT_B" (rect 5 0 51 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 320 272 488 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+(connector + (pt 536 312) + (pt 536 328) +) +(connector + (pt 536 328) + (pt 536 344) +) +(junction (pt 536 312)) +(junction (pt 536 328)) diff --git a/Exp28/YL_dec7748.qpf b/Exp28/YL_dec7748.qpf new file mode 100644 index 0000000..a328293 --- /dev/null +++ b/Exp28/YL_dec7748.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:51:11 May 03, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "15:51:11 May 03, 2020" + +# Revisions + +PROJECT_REVISION = "YL_dec7748" diff --git a/Exp28/YL_dec7748.qsf b/Exp28/YL_dec7748.qsf new file mode 100644 index 0000000..da4e843 --- /dev/null +++ b/Exp28/YL_dec7748.qsf @@ -0,0 +1,60 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:51:11 May 03, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# YL_dec7748_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY YL_dec7748 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:51:11 MAY 03, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name BDF_FILE YL_dec7748.bdf +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_7448.vwf +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf" \ No newline at end of file diff --git a/Exp28/YL_dec7748.qws b/Exp28/YL_dec7748.qws new file mode 100644 index 0000000000000000000000000000000000000000..4e7223ce5277e5a5f9f4da8235404e2414863298 GIT binary patch literal 2010 zcmds%&1w@-7>3`Ox`-QbDd-}INEOm##+1~GMT~V-5JVS(P|{?gA+;$@%@NXe$p_{?6y)8BLJZN_CQPi?lfT~g@e5Rk_ zC)EP@17xeJsLZ#ZIjn4}iRYL9$a90J>-cvB_P<8#_CEux=mqgss7RS;>mlL-cmkHn zSO#1Lt8p*megUeCg-r7*aiavU1~1Xh@l`X5@cjYU1N6fi`Q_>GDUcHb$Z_U&2Ly-W zJ(h<+MtpirWx}_Q=rEzJ1aq8|=6v;l4@j3kn6qqLI2V2X^f7ppz92qJ7ANuW2K*ba z2#wMBHTeE=CoA+Qp%?B`GxRToX?LRQTs^JZT+JwfRqAR_ zQwpJ>Jgd9B2#abOk!42a^Nq(H$RH zKdA}ByfaKHIxsY$7`Sc|$kMKh9(`v!Pu2aLt>Y(8(oOa%=LYF#VebuYMoXwabUjJu gy{$n1ALHi?k34>VZ)j#NQRVBz78Zs7X)qD%7Y!>_J^%m! literal 0 HcmV?d00001 diff --git a/Exp28/db/YL_dec7748.(0).cnf.cdb b/Exp28/db/YL_dec7748.(0).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..97d1077542c8424eed9d73ce548afc3420d89175 GIT binary patch literal 1001 zcmVc4=c}AW&grYalToQ%WFLWnv&jWNCD1Z*Eo#00000004gi00000 z003M900000008L&00000004La)K*JN!$1&Dd|=gse?q)?EhwJ0sSgU$inM3XA}FZf zF+W)^zP0Q3O){HlY-`$z(vj)ze);CHvy+Y9d*6qyM^W^Nv8sX|B*rYpUoA(t{(vuz z?-&U$@&~dC?ew}Qz3y2<0FoADR{V@}z#y%5Vees0zLjeB&0sQ}{r-&hNwA+}|E7SM zgE;C>Q~={(x(XNv)0MzDI0!YE(%6$85*!(Z}HZE&m*X23$DP!Z-^Tw}jW=F_A&}%H;pVVd4etrRm3+W$MiYwvi z|3C0I^uxoDcLGVd5qqwLKeEvvFHml91&Ys5N}sBHuT=R3zzyJVYdXLw$Gj#f*IJux zI)ki1ck1=sz4ObP+X&1k+JL@-JFU`($}%Q*SJxLzn_sz3xK)uz8WR#YTy>IffWsBa z)C+dF*9O_)wvxgGCkcXx42End9DFm`)1=eZ2T0n<9AP4%iwKi9b1E{Yi)B~v!|#cYR@H!<{(%>2Nx$N7ZE9ngS(3kE^Z?IEBr2q&ngDKyS%&ayLXq1 zP8#hK(b?_MHXP-E(DtM!qN*E4Qg~6Y#R*CPgH%cqo#ZWzBh$coRF&q2XE~xGJ-;GW ztcoc^+lWMboSiEc3TsTJ6fi_3*v0u=nj^pUeBu9kRwSqa`*7f_asy+4y3TP$U<8(< zx*ebvXwAFMJBaaQiv2YoC*sL6l*ilk!eoadQ-I=Heywgqu2~f_5H^|=LCCE5Nzys| z@#fxg23`l0(DiX78Ugw#i(VS-=f}UDbA8{#m)6oW18(=Nd%?O1Kow(_toy;wos5Gq zOfA@}7pDyu-=#FX5iLbKNZg!0eT>3q0Y&gJOAQesF4ae6*u(PDJ^u#1Ot*)r$BQh! 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 1000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("INPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("INPUT_A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_C") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 63.26; + LEVEL 0 FOR 49.803; + LEVEL 1 FOR 100.069; + LEVEL 0 FOR 50.128; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 49.29; + LEVEL 0 FOR 0.582; + LEVEL 1 FOR 99.931; + LEVEL 0 FOR 150.197; + LEVEL 1 FOR 49.803; + LEVEL 0 FOR 99.487; + LEVEL 1 FOR 50.71; + LEVEL 0 FOR 49.803; + LEVEL 1 FOR 86.937; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 261.167; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 49.3; + LEVEL 0 FOR 0.7; + LEVEL 1 FOR 99.794; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 50.206; + LEVEL 0 FOR 149.3; + LEVEL 1 FOR 189.533; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 111.414; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 249.297; + LEVEL 0 FOR 0.582; + LEVEL 1 FOR 100.121; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 49.879; + LEVEL 0 FOR 199.418; + LEVEL 1 FOR 100.703; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 38.586; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 61.576; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 49.765; + LEVEL 1 FOR 100.114; + LEVEL 0 FOR 50.121; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 49.879; + LEVEL 1 FOR 50.121; + } + LEVEL 0 FOR 49.765; + LEVEL 1 FOR 88.659; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 61.915; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 49.923; + LEVEL 1 FOR 50.077; + } + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 38.085; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 61.165; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 49.802; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 150.198; + LEVEL 0 FOR 49.802; + LEVEL 1 FOR 50.198; + LEVEL 0 FOR 138.835; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.907; + LEVEL 1 FOR 250.227; + LEVEL 0 FOR 49.773; + LEVEL 1 FOR 350.227; + LEVEL 0 FOR 149.773; + LEVEL 1 FOR 89.093; + } +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28/db/YL_dec7748.sld_design_entry.sci b/Exp28/db/YL_dec7748.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/Exp28/db/YL_dec7748.sld_design_entry_dsc.sci b/Exp28/db/YL_dec7748.sld_design_entry_dsc.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/Exp28/db/YL_dec7748.smart_action.txt b/Exp28/db/YL_dec7748.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/Exp28/db/YL_dec7748.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/Exp28/db/YL_dec7748.sta.qmsg b/Exp28/db/YL_dec7748.sta.qmsg new file mode 100644 index 0000000..4d12c0e --- /dev/null +++ b/Exp28/db/YL_dec7748.sta.qmsg @@ -0,0 +1,34 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588496429018 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 17:00:28 2020 " "Processing started: Sun May 03 17:00:28 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_dec7748 -c YL_dec7748 " "Command: quartus_sta YL_dec7748 -c YL_dec7748" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588496429176 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588496429471 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588496429510 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588496429510 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_dec7748.sdc " "Synopsys Design Constraints File file not found: 'YL_dec7748.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588496429605 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588496429606 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1588496429606 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1588496429607 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588496429609 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1588496429623 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588496429626 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429627 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429653 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429656 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429661 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429666 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429668 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588496429680 ""} +{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588496429682 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588496429695 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1588496429695 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1588496429698 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429702 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429704 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429708 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429711 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429716 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588496429726 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588496429761 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588496429761 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4541 " "Peak virtual memory: 4541 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588496429837 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 17:00:29 2020 " "Processing ended: Sun May 03 17:00:29 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""} diff --git a/Exp28/db/YL_dec7748.sta.rdb b/Exp28/db/YL_dec7748.sta.rdb new file mode 100644 index 0000000000000000000000000000000000000000..202c4f1734d9d9380eca742082454f6ac83f042b GIT binary patch literal 3881 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Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.sof + 6. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sun May 03 17:00:27 2020 ; +; Revision Name ; YL_dec7748 ; +; Top-level Entity Name ; YL_dec7748 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.sof ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.pof ; ++-----------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.sof ; ++----------------+--------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------------------------------------+ +; Device ; EP2C20F484C7 ; +; JTAG usercode ; 0x001B207A ; +; Checksum ; 0x001B207A ; ++----------------+--------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.pof ; ++--------------------+----------------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+----------------------------------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1DD9CD2A ; +; Compression Ratio ; 3 ; ++--------------------+----------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 17:00:24 2020 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748 +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4558 megabytes + Info: Processing ended: Sun May 03 17:00:27 2020 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/Exp28/output_files/YL_dec7748.done b/Exp28/output_files/YL_dec7748.done new file mode 100644 index 0000000..ce23195 --- /dev/null +++ b/Exp28/output_files/YL_dec7748.done @@ -0,0 +1 @@ +Sun May 03 17:00:30 2020 diff --git a/Exp28/output_files/YL_dec7748.fit.rpt b/Exp28/output_files/YL_dec7748.fit.rpt new file mode 100644 index 0000000..9f48006 --- /dev/null +++ b/Exp28/output_files/YL_dec7748.fit.rpt @@ -0,0 +1,1165 @@ +Fitter report for YL_dec7748 +Sun May 03 17:00:23 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. Output Pin Default Load For Reported TCO + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Non-Global High Fan-Out Signals + 20. Other Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. Fitter Device Options + 26. Operating Settings and Conditions + 27. Fitter Messages + 28. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Sun May 03 17:00:23 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_dec7748 ; +; Top-level Entity Name ; YL_dec7748 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 7 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 7 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 18,752 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 11 / 315 ( 3 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C20F484C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 22 ( 0.00 % ) ; +; -- Achieved ; 0 / 22 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 19 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.pin. + + ++--------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 7 / 18,752 ( < 1 % ) ; +; -- Combinational with no register ; 7 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 5 ; +; -- 3 input functions ; 2 ; +; -- <=2 input functions ; 0 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 7 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 19,649 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 18,752 ( 0 % ) ; +; -- I/O registers ; 0 / 897 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 1,172 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 11 / 315 ( 3 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; ; ; +; Global signals ; 0 ; +; M4Ks ; 0 / 52 ( 0 % ) ; +; Total block memory bits ; 0 / 239,616 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 0 / 16 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 7 ; +; Highest non-global fan-out ; 7 ; +; Total fan-out ; 33 ; +; Average fan-out ; 1.57 ; ++---------------------------------------------+----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 7 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; -- Combinational with no register ; 7 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 5 ; 0 ; +; -- 3 input functions ; 2 ; 0 ; +; -- <=2 input functions ; 0 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 7 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 18752 ( 0 % ) ; 0 / 18752 ( 0 % ) ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 1172 ( < 1 % ) ; 0 / 1172 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 11 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; 0 / 52 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 33 ; 0 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 4 ; 0 ; +; -- Output Ports ; 7 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; INPUT_A ; H12 ; 4 ; 31 ; 27 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_B ; AA10 ; 8 ; 22 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_C ; F12 ; 4 ; 31 ; 27 ; 2 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_D ; AB13 ; 7 ; 29 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; OUTPUT_A ; B14 ; 4 ; 29 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_B ; AA13 ; 7 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_C ; Y13 ; 7 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_D ; AA11 ; 8 ; 24 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_E ; R11 ; 8 ; 20 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_F ; AB12 ; 7 ; 29 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_G ; T12 ; 7 ; 31 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 0 / 41 ( 0 % ) ; 3.3V ; -- ; +; 2 ; 2 / 33 ( 6 % ) ; 3.3V ; -- ; +; 3 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; +; 4 ; 3 / 40 ( 8 % ) ; 3.3V ; -- ; +; 5 ; 0 / 39 ( 0 % ) ; 3.3V ; -- ; +; 6 ; 1 / 36 ( 3 % ) ; 3.3V ; -- ; +; 7 ; 5 / 40 ( 13 % ) ; 3.3V ; -- ; +; 8 ; 3 / 43 ( 7 % ) ; 3.3V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 306 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A8 ; 304 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A9 ; 298 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A10 ; 293 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A11 ; 287 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 265 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 251 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 249 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 82 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA4 ; 85 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA5 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA6 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA7 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 120 ; 8 ; INPUT_B ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA11 ; 122 ; 8 ; OUTPUT_D ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 130 ; 7 ; OUTPUT_B ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 144 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 83 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB4 ; 84 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB5 ; 88 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB6 ; 96 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB7 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB12 ; 127 ; 7 ; OUTPUT_F ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB13 ; 129 ; 7 ; INPUT_D ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 305 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B8 ; 303 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B9 ; 297 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B10 ; 292 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B11 ; 286 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B14 ; 278 ; 4 ; OUTPUT_A ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 264 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B18 ; 250 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C7 ; 315 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; 310 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C10 ; 296 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C14 ; 260 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D2 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D5 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D6 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 302 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 289 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 267 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 259 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; 255 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; 266 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E15 ; 256 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F4 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 276 ; 4 ; INPUT_C ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; F13 ; 269 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 268 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 262 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 261 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 252 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H2 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; H4 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H6 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 274 ; 4 ; INPUT_A ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; H13 ; 263 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H14 ; 257 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H15 ; 253 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J1 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J2 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; 258 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M1 ; 41 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M2 ; 42 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P6 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 187 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R1 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R2 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R5 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R6 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R7 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R8 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R10 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R11 ; 116 ; 8 ; OUTPUT_E ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; R21 ; 190 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R22 ; 191 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T1 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T2 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T3 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T5 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T6 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T7 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T8 ; 90 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T12 ; 131 ; 7 ; OUTPUT_G ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T15 ; 147 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 188 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T22 ; 189 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U1 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U2 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U3 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U4 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U8 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U21 ; 182 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U22 ; 183 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V9 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 180 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 181 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W2 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W7 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W8 ; 100 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W9 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W21 ; 174 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; 175 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y3 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y4 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y5 ; 86 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y6 ; 87 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y7 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y13 ; 133 ; 7 ; OUTPUT_C ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y21 ; 178 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 179 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+--------------+ +; |YL_dec7748 ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; |YL_dec7748 ; work ; +; |7448:inst| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |YL_dec7748|7448:inst ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++----------+----------+---------------+---------------+-----------------------+-----+ +; OUTPUT_A ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_B ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_C ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_D ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_E ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_F ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_G ; Output ; -- ; -- ; -- ; -- ; +; INPUT_B ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_D ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_C ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_A ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; ++----------+----------+---------------+---------------+-----------------------+-----+ + + ++-----------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------+-------------------+---------+ +; INPUT_B ; ; ; +; - 7448:inst|69~0 ; 0 ; 6 ; +; - 7448:inst|68~0 ; 0 ; 6 ; +; - 7448:inst|70 ; 0 ; 6 ; +; - 7448:inst|67~0 ; 0 ; 6 ; +; - 7448:inst|71 ; 0 ; 6 ; +; - 7448:inst|66~0 ; 0 ; 6 ; +; - 7448:inst|72 ; 0 ; 6 ; +; INPUT_D ; ; ; +; - 7448:inst|69~0 ; 0 ; 6 ; +; - 7448:inst|68~0 ; 0 ; 6 ; +; - 7448:inst|70 ; 0 ; 6 ; +; - 7448:inst|66~0 ; 0 ; 6 ; +; - 7448:inst|72 ; 0 ; 6 ; +; INPUT_C ; ; ; +; - 7448:inst|69~0 ; 0 ; 6 ; +; - 7448:inst|68~0 ; 0 ; 6 ; +; - 7448:inst|70 ; 0 ; 6 ; +; - 7448:inst|67~0 ; 0 ; 6 ; +; - 7448:inst|71 ; 0 ; 6 ; +; - 7448:inst|66~0 ; 0 ; 6 ; +; - 7448:inst|72 ; 0 ; 6 ; +; INPUT_A ; ; ; +; - 7448:inst|69~0 ; 0 ; 6 ; +; - 7448:inst|68~0 ; 0 ; 6 ; +; - 7448:inst|70 ; 0 ; 6 ; +; - 7448:inst|67~0 ; 0 ; 6 ; +; - 7448:inst|71 ; 0 ; 6 ; +; - 7448:inst|66~0 ; 0 ; 6 ; +; - 7448:inst|72 ; 0 ; 6 ; ++-----------------------+-------------------+---------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------+----------------+ +; Name ; Fan-Out ; ++----------------+----------------+ +; INPUT_A ; 7 ; +; INPUT_C ; 7 ; +; INPUT_B ; 7 ; +; INPUT_D ; 5 ; +; 7448:inst|72 ; 1 ; +; 7448:inst|66~0 ; 1 ; +; 7448:inst|71 ; 1 ; +; 7448:inst|67~0 ; 1 ; +; 7448:inst|70 ; 1 ; +; 7448:inst|68~0 ; 1 ; +; 7448:inst|69~0 ; 1 ; ++----------------+----------------+ + + ++-----------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-----------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-----------------------+ +; Block interconnects ; 11 / 54,004 ( < 1 % ) ; +; C16 interconnects ; 4 / 2,100 ( < 1 % ) ; +; C4 interconnects ; 16 / 36,000 ( < 1 % ) ; +; Global clocks ; 0 / 16 ( 0 % ) ; +; Local interconnects ; 0 / 18,752 ( 0 % ) ; +; R24 interconnects ; 0 / 1,900 ( 0 % ) ; +; R4 interconnects ; 8 / 46,920 ( < 1 % ) ; ++-----------------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 1) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 7.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 4.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP2C20F484C7 for design "YL_dec7748" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP2C15AF484C7 is compatible + Info (176445): Device EP2C35F484C7 is compatible + Info (176445): Device EP2C50F484C7 is compatible +Info (169124): Fitter converted 3 user pins into dedicated programming pins + Info (169125): Pin ~ASDO~ is reserved at location C4 + Info (169125): Pin ~nCSO~ is reserved at location C3 + Info (169125): Pin ~LVDS91p/nCEO~ is reserved at location W20 +Critical Warning (169085): No exact pin location assignment(s) for 11 pins of 11 total pins + Info (169086): Pin OUTPUT_A not assigned to an exact location on the device + Info (169086): Pin OUTPUT_B not assigned to an exact location on the device + Info (169086): Pin OUTPUT_C not assigned to an exact location on the device + Info (169086): Pin OUTPUT_D not assigned to an exact location on the device + Info (169086): Pin OUTPUT_E not assigned to an exact location on the device + Info (169086): Pin OUTPUT_F not assigned to an exact location on the device + Info (169086): Pin OUTPUT_G not assigned to an exact location on the device + Info (169086): Pin INPUT_B not assigned to an exact location on the device + Info (169086): Pin INPUT_D not assigned to an exact location on the device + Info (169086): Pin INPUT_C not assigned to an exact location on the device + Info (169086): Pin INPUT_A not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_dec7748.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 4 input, 7 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X25_Y0 to location X37_Y13 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. +Info (306004): Started post-fitting delay annotation +Warning (306006): Found 7 output pins without output pin load capacitance assignment + Info (306007): Pin "OUTPUT_A" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_B" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_C" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_D" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_E" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_F" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_G" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info (306005): Delay annotation completed successfully +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 4848 megabytes + Info: Processing ended: Sun May 03 17:00:23 2020 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:06 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.fit.smsg. + + diff --git a/Exp28/output_files/YL_dec7748.fit.smsg b/Exp28/output_files/YL_dec7748.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/Exp28/output_files/YL_dec7748.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/Exp28/output_files/YL_dec7748.fit.summary b/Exp28/output_files/YL_dec7748.fit.summary new file mode 100644 index 0000000..5b3da90 --- /dev/null +++ b/Exp28/output_files/YL_dec7748.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Sun May 03 17:00:23 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_dec7748 +Top-level Entity Name : YL_dec7748 +Family : Cyclone II +Device : EP2C20F484C7 +Timing Models : Final +Total logic elements : 7 / 18,752 ( < 1 % ) + Total combinational functions : 7 / 18,752 ( < 1 % ) + Dedicated logic registers : 0 / 18,752 ( 0 % ) +Total registers : 0 +Total pins : 11 / 315 ( 3 % ) +Total virtual pins : 0 +Total memory bits : 0 / 239,616 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/Exp28/output_files/YL_dec7748.flow.rpt b/Exp28/output_files/YL_dec7748.flow.rpt new file mode 100644 index 0000000..9489ce6 --- /dev/null +++ b/Exp28/output_files/YL_dec7748.flow.rpt @@ -0,0 +1,122 @@ +Flow report for YL_dec7748 +Sun May 03 17:00:29 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Sun May 03 17:00:27 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_dec7748 ; +; Top-level Entity Name ; YL_dec7748 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 7 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 7 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 18,752 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 11 / 315 ( 3 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 05/03/2020 17:00:14 ; +; Main task ; Compilation ; +; Revision Name ; YL_dec7748 ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 345052807169.158849641411336 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4593 MB ; 00:00:01 ; +; Fitter ; 00:00:07 ; 1.0 ; 4848 MB ; 00:00:06 ; +; Assembler ; 00:00:03 ; 1.0 ; 4558 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4541 MB ; 00:00:01 ; +; Total ; 00:00:13 ; -- ; -- ; 00:00:10 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off YL_dec7748 -c YL_dec7748 +quartus_fit --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748 +quartus_asm --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748 +quartus_sta YL_dec7748 -c YL_dec7748 + + + diff --git a/Exp28/output_files/YL_dec7748.jdi b/Exp28/output_files/YL_dec7748.jdi new file mode 100644 index 0000000..ba81ec7 --- /dev/null +++ b/Exp28/output_files/YL_dec7748.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp28/output_files/YL_dec7748.map.rpt b/Exp28/output_files/YL_dec7748.map.rpt new file mode 100644 index 0000000..58f47b8 --- /dev/null +++ b/Exp28/output_files/YL_dec7748.map.rpt @@ -0,0 +1,258 @@ +Analysis & Synthesis report for YL_dec7748 +Sun May 03 17:00:15 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sun May 03 17:00:15 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_dec7748 ; +; Top-level Entity Name ; YL_dec7748 ; +; Family ; Cyclone II ; +; Total logic elements ; 7 ; +; Total combinational functions ; 7 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 11 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; YL_dec7748 ; YL_dec7748 ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+ +; YL_dec7748.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_dec7748.bdf ; ; +; 7448.bdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/others/maxplus2/7448.bdf ; ; ++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+ + + ++-------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------+ +; Resource ; Usage ; ++---------------------------------------------+---------+ +; Estimated Total logic elements ; 7 ; +; ; ; +; Total combinational functions ; 7 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 5 ; +; -- 3 input functions ; 2 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 7 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 11 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; INPUT_B ; +; Maximum fan-out ; 7 ; +; Total fan-out ; 33 ; +; Average fan-out ; 1.83 ; ++---------------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+ +; |YL_dec7748 ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; |YL_dec7748 ; work ; +; |7448:inst| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_dec7748|7448:inst ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 17:00:13 2020 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_dec7748 -c YL_dec7748 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file yl_dec7748.bdf + Info (12023): Found entity 1: YL_dec7748 +Info (12127): Elaborating entity "YL_dec7748" for the top level hierarchy +Info (12128): Elaborating entity "7448" for hierarchy "7448:inst" +Info (12130): Elaborated megafunction instantiation "7448:inst" +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 4 input pins + Info (21059): Implemented 7 output pins + Info (21061): Implemented 7 logic cells +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4604 megabytes + Info: Processing ended: Sun May 03 17:00:15 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/Exp28/output_files/YL_dec7748.map.summary b/Exp28/output_files/YL_dec7748.map.summary new file mode 100644 index 0000000..f5fd4aa --- /dev/null +++ b/Exp28/output_files/YL_dec7748.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Sun May 03 17:00:15 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_dec7748 +Top-level Entity Name : YL_dec7748 +Family : Cyclone II +Total logic elements : 7 + Total combinational functions : 7 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 11 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/Exp28/output_files/YL_dec7748.pin b/Exp28/output_files/YL_dec7748.pin new file mode 100644 index 0000000..2eeff8b --- /dev/null +++ b/Exp28/output_files/YL_dec7748.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "YL_dec7748" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +GND* : A11 : : : : 3 : +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +GND* : AA3 : : : : 8 : +GND* : AA4 : : : : 8 : +GND* : AA5 : : : : 8 : +GND* : AA6 : : : : 8 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +INPUT_B : AA10 : input : 3.3-V LVTTL : : 8 : N +OUTPUT_D : AA11 : output : 3.3-V LVTTL : : 8 : N +GND* : AA12 : : : : 7 : +OUTPUT_B : AA13 : output : 3.3-V LVTTL : : 7 : N +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +GND* : AB3 : : : : 8 : +GND* : AB4 : : : : 8 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +OUTPUT_F : AB12 : output : 3.3-V LVTTL : : 7 : N +INPUT_D : AB13 : input : 3.3-V LVTTL : : 7 : N +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +GND* : B11 : : : : 3 : +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +OUTPUT_A : B14 : output : 3.3-V LVTTL : : 4 : N +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +GND* : B17 : : : : 4 : +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 2 : +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +GND* : C7 : : : : 3 : +GND : C8 : gnd : : : : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +GND* : C14 : : : : 4 : +GND : C15 : gnd : : : : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +GND* : C21 : : : : 5 : +GND* : C22 : : : : 5 : +GND* : D1 : : : : 2 : +GND* : D2 : : : : 2 : +GND* : D3 : : : : 2 : +GND* : D4 : : : : 2 : +GND* : D5 : : : : 2 : +GND* : D6 : : : : 2 : +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +GND* : D9 : : : : 3 : +GND : D10 : gnd : : : : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +GND* : D14 : : : : 4 : +GND* : D15 : : : : 4 : +GND* : D16 : : : : 4 : +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +GND* : D20 : : : : 5 : +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +GND* : E14 : : : : 4 : +GND* : E15 : : : : 4 : +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +GND* : F1 : : : : 2 : +GND* : F2 : : : : 2 : +GND* : F3 : : : : 2 : +GND* : F4 : : : : 2 : +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +INPUT_C : F12 : input : 3.3-V LVTTL : : 4 : N +GND* : F13 : : : : 4 : +GND* : F14 : : : : 4 : +GND* : F15 : : : : 4 : +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +GND* : G3 : : : : 2 : +GND : G4 : gnd : : : : +GND* : G5 : : : : 2 : +GND* : G6 : : : : 2 : +GND* : G7 : : : : 3 : +GND* : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +GND* : G15 : : : : 4 : +GND* : G16 : : : : 4 : +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +GND* : H4 : : : : 2 : +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +INPUT_A : H12 : input : 3.3-V LVTTL : : 4 : N +GND* : H13 : : : : 4 : +GND* : H14 : : : : 4 : +GND* : H15 : : : : 4 : +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +GND* : J1 : : : : 2 : +GND* : J2 : : : : 2 : +NC : J3 : : : : : +GND* : J4 : : : : 2 : +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +GND* : J14 : : : : 4 : +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +GND+ : L1 : : : : 2 : +GND+ : L2 : : : : 2 : +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +GND* : L8 : : : : 2 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +GND+ : L21 : : : : 5 : +GND+ : L22 : : : : 5 : +GND+ : M1 : : : : 1 : +GND+ : M2 : : : : 1 : +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +GND+ : M22 : : : : 6 : +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +GND* : P5 : : : : 1 : +GND* : P6 : : : : 1 : +VCCIO1 : P7 : power : : 3.3V : 1 : +GND* : P8 : : : : 8 : +GND* : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +GND* : P18 : : : : 6 : +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +GND* : R1 : : : : 1 : +GND* : R2 : : : : 1 : +GND : R3 : gnd : : : : +NC : R4 : : : : : +GND* : R5 : : : : 1 : +GND* : R6 : : : : 1 : +GND* : R7 : : : : 1 : +GND* : R8 : : : : 1 : +GND* : R9 : : : : 8 : +GND* : R10 : : : : 8 : +OUTPUT_E : R11 : output : 3.3-V LVTTL : : 8 : N +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +GND* : T1 : : : : 1 : +GND* : T2 : : : : 1 : +GND* : T3 : : : : 1 : +VCCIO1 : T4 : power : : 3.3V : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 8 : +GND* : T8 : : : : 8 : +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +OUTPUT_G : T12 : output : 3.3-V LVTTL : : 7 : N +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +GND* : T15 : : : : 7 : +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +GND* : U8 : : : : 8 : +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND : V3 : gnd : : : : +GND* : V4 : : : : 1 : +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +GND* : V8 : : : : 8 : +GND* : V9 : : : : 8 : +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +VCCIO8 : W6 : power : : 3.3V : 8 : +GND* : W7 : : : : 8 : +GND* : W8 : : : : 8 : +GND* : W9 : : : : 8 : +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +GND* : Y1 : : : : 1 : +GND* : Y2 : : : : 1 : +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +GND* : Y5 : : : : 8 : +GND* : Y6 : : : : 8 : +GND* : Y7 : : : : 8 : +GND : Y8 : gnd : : : : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power : : 3.3V : 7 : +OUTPUT_C : Y13 : output : 3.3-V LVTTL : : 7 : N +GND* : Y14 : : : : 7 : +GND : Y15 : gnd : : : : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 6 : +GND* : Y19 : : : : 6 : +GND* : Y20 : : : : 6 : +GND* : Y21 : : : : 6 : +GND* : Y22 : : : : 6 : diff --git a/Exp28/output_files/YL_dec7748.pof b/Exp28/output_files/YL_dec7748.pof new file mode 100644 index 0000000000000000000000000000000000000000..96f89a55355c765e0f24bbd181dab1b5b03b6668 GIT binary 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Legal Notice + 2. Simulator Summary + 3. Simulator Settings + 4. Simulation Waveforms + 5. Coverage Summary + 6. Complete 1/0-Value Coverage + 7. Missing 1-Value Coverage + 8. Missing 0-Value Coverage + 9. Simulator INI Usage + 10. Simulator Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------+ +; Simulator Summary ; ++-----------------------------+--------------+ +; Type ; Value ; ++-----------------------------+--------------+ +; Simulation Start Time ; 0 ps ; +; Simulation End Time ; 1.0 us ; +; Simulation Netlist Size ; 18 nodes ; +; Simulation Coverage ; 100.00 % ; +; Total Number of Transitions ; 224 ; +; Simulation Breakpoints ; 0 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Simulator Settings ; ++--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+ +; Simulation mode ; Timing ; Timing ; +; Start time ; 0 ns ; 0 ns ; +; Simulation results format ; VWF ; ; +; Vector input source ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf ; ; +; Add pins automatically to simulation output waveforms ; On ; On ; +; Check outputs ; Off ; Off ; +; Report simulation coverage ; On ; On ; +; Display complete 1/0 value coverage report ; On ; On ; +; Display missing 1-value coverage report ; On ; On ; +; Display missing 0-value coverage report ; On ; On ; +; Detect setup and hold time violations ; Off ; Off ; +; Detect glitches ; Off ; Off ; +; Disable timing delays in Timing Simulation ; Off ; Off ; +; Generate Signal Activity File ; Off ; Off ; +; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ; +; Group bus channels in simulation results ; Off ; Off ; +; Preserve fewer signal transitions to reduce memory requirements ; On ; On ; +; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ; +; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ; +; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ; +; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ; ++--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+ + + ++----------------------+ +; Simulation Waveforms ; ++----------------------+ +Waveform report data cannot be output to ASCII. +Please use Quartus II 64-Bit to view the waveform report data. + + ++--------------------------------------------------------------------+ +; Coverage Summary ; ++-----------------------------------------------------+--------------+ +; Type ; Value ; ++-----------------------------------------------------+--------------+ +; Total coverage as a percentage ; 100.00 % ; +; Total nodes checked ; 18 ; +; Total output ports checked ; 18 ; +; Total output ports with complete 1/0-value coverage ; 18 ; +; Total output ports with no 1/0-value coverage ; 0 ; +; Total output ports with no 1-value coverage ; 0 ; +; Total output ports with no 0-value coverage ; 0 ; ++-----------------------------------------------------+--------------+ + + +The following table displays output ports that toggle between 1 and 0 during simulation. ++----------------------------------------------------------------------------+ +; Complete 1/0-Value Coverage ; ++----------------------------+----------------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++----------------------------+----------------------------+------------------+ +; |YL_dec7748|7448:inst|69~0 ; |YL_dec7748|7448:inst|69~0 ; combout ; +; |YL_dec7748|7448:inst|68~0 ; |YL_dec7748|7448:inst|68~0 ; combout ; +; |YL_dec7748|7448:inst|70 ; |YL_dec7748|7448:inst|70 ; combout ; +; |YL_dec7748|7448:inst|67~0 ; |YL_dec7748|7448:inst|67~0 ; combout ; +; |YL_dec7748|7448:inst|71 ; |YL_dec7748|7448:inst|71 ; combout ; +; |YL_dec7748|7448:inst|66~0 ; |YL_dec7748|7448:inst|66~0 ; combout ; +; |YL_dec7748|7448:inst|72 ; |YL_dec7748|7448:inst|72 ; combout ; +; |YL_dec7748|OUTPUT_A ; |YL_dec7748|OUTPUT_A ; padio ; +; |YL_dec7748|OUTPUT_B ; |YL_dec7748|OUTPUT_B ; padio ; +; |YL_dec7748|OUTPUT_C ; |YL_dec7748|OUTPUT_C ; padio ; +; |YL_dec7748|OUTPUT_D ; |YL_dec7748|OUTPUT_D ; padio ; +; |YL_dec7748|OUTPUT_E ; |YL_dec7748|OUTPUT_E ; padio ; +; |YL_dec7748|OUTPUT_F ; |YL_dec7748|OUTPUT_F ; padio ; +; |YL_dec7748|OUTPUT_G ; |YL_dec7748|OUTPUT_G ; padio ; +; |YL_dec7748|INPUT_B ; |YL_dec7748|INPUT_B~corein ; combout ; +; |YL_dec7748|INPUT_D ; |YL_dec7748|INPUT_D~corein ; combout ; +; |YL_dec7748|INPUT_C ; |YL_dec7748|INPUT_C~corein ; combout ; +; |YL_dec7748|INPUT_A ; |YL_dec7748|INPUT_A~corein ; combout ; ++----------------------------+----------------------------+------------------+ + + +The following table displays output ports that do not toggle to 1 during simulation. ++-------------------------------------------------+ +; Missing 1-Value Coverage ; ++-----------+------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++-----------+------------------+------------------+ + + +The following table displays output ports that do not toggle to 0 during simulation. ++-------------------------------------------------+ +; Missing 0-Value Coverage ; ++-----------+------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++-----------+------------------+------------------+ + + ++---------------------+ +; Simulator INI Usage ; ++--------+------------+ +; Option ; Usage ; ++--------+------------+ + + ++--------------------+ +; Simulator Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Simulator + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 17:01:02 2020 +Info: Command: quartus_sim --simulation_results_format=VWF YL_dec7748 -c YL_dec7748 +Info (324025): Using vector source file "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf" +Info (310003): Option to preserve fewer signal transitions to reduce memory requirements is enabled + Info (310004): Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements. +Info (310002): Simulation partitioned into 1 sub-simulations +Info (328053): Simulation coverage is 100.00 % +Info (328052): Number of transitions in simulation is 224 +Info (324045): Vector file YL_dec7748.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. 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06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow Model Fmax Summary + 6. Slow Model Setup Summary + 7. Slow Model Hold Summary + 8. Slow Model Recovery Summary + 9. Slow Model Removal Summary + 10. Slow Model Minimum Pulse Width Summary + 11. Propagation Delay + 12. Minimum Propagation Delay + 13. Fast Model Setup Summary + 14. Fast Model Hold Summary + 15. Fast Model Recovery Summary + 16. Fast Model Removal Summary + 17. Fast Model Minimum Pulse Width Summary + 18. Propagation Delay + 19. Minimum Propagation Delay + 20. Multicorner Timing Analysis Summary + 21. Progagation Delay + 22. Minimum Progagation Delay + 23. Clock Transfers + 24. Report TCCS + 25. Report RSKM + 26. Unconstrained Paths + 27. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; YL_dec7748 ; +; Device Family ; Cyclone II ; +; Device Name ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +--------------------------- +; Slow Model Fmax Summary ; +--------------------------- +No paths to report. + + +---------------------------- +; Slow Model Setup Summary ; +---------------------------- +No paths to report. + + +--------------------------- +; Slow Model Hold Summary ; +--------------------------- +No paths to report. + + +------------------------------- +; Slow Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Slow Model Removal Summary ; +------------------------------ +No paths to report. + + +------------------------------------------ +; Slow Model Minimum Pulse Width Summary ; +------------------------------------------ +No paths to report. + + ++--------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; INPUT_A ; OUTPUT_A ; 13.260 ; 13.260 ; 13.260 ; 13.260 ; +; INPUT_A ; OUTPUT_B ; 11.167 ; 11.167 ; 11.167 ; 11.167 ; +; INPUT_A ; OUTPUT_C ; 11.414 ; ; ; 11.414 ; +; INPUT_A ; OUTPUT_D ; 11.576 ; 11.576 ; 11.576 ; 11.576 ; +; INPUT_A ; OUTPUT_E ; ; 11.915 ; 11.915 ; ; +; INPUT_A ; OUTPUT_F ; ; 11.165 ; 11.165 ; ; +; INPUT_A ; OUTPUT_G ; ; 11.134 ; 11.134 ; ; +; INPUT_B ; OUTPUT_A ; 13.063 ; 13.063 ; 13.063 ; 13.063 ; +; INPUT_B ; OUTPUT_B ; 10.961 ; 10.961 ; 10.961 ; 10.961 ; +; INPUT_B ; OUTPUT_C ; ; 11.208 ; 11.208 ; ; +; INPUT_B ; OUTPUT_D ; 11.341 ; 11.341 ; 11.341 ; 11.341 ; +; INPUT_B ; OUTPUT_E ; 11.754 ; ; ; 11.754 ; +; INPUT_B ; OUTPUT_F ; ; 10.967 ; 10.967 ; ; +; INPUT_B ; OUTPUT_G ; 10.907 ; 10.907 ; 10.907 ; 10.907 ; +; INPUT_C ; OUTPUT_A ; 13.132 ; 13.132 ; 13.132 ; 13.132 ; +; INPUT_C ; OUTPUT_B ; ; 11.046 ; 11.046 ; ; +; INPUT_C ; OUTPUT_C ; 11.293 ; 11.293 ; 11.293 ; 11.293 ; +; INPUT_C ; OUTPUT_D ; 11.455 ; 11.455 ; 11.455 ; 11.455 ; +; INPUT_C ; OUTPUT_E ; ; 11.838 ; 11.838 ; ; +; INPUT_C ; OUTPUT_F ; 11.037 ; ; ; 11.037 ; +; INPUT_C ; OUTPUT_G ; 11.006 ; 11.006 ; 11.006 ; 11.006 ; +; INPUT_D ; OUTPUT_A ; 12.550 ; 12.550 ; 12.550 ; 12.550 ; +; INPUT_D ; OUTPUT_B ; ; 10.467 ; 10.467 ; ; +; INPUT_D ; OUTPUT_C ; ; 10.711 ; 10.711 ; ; +; INPUT_D ; OUTPUT_F ; 10.455 ; ; ; 10.455 ; +; INPUT_D ; OUTPUT_G ; 10.396 ; ; ; 10.396 ; ++------------+-------------+--------+--------+--------+--------+ + + ++--------------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; INPUT_A ; OUTPUT_A ; 13.260 ; 13.260 ; 13.260 ; 13.260 ; +; INPUT_A ; OUTPUT_B ; 11.167 ; 11.167 ; 11.167 ; 11.167 ; +; INPUT_A ; OUTPUT_C ; 11.414 ; ; ; 11.414 ; +; INPUT_A ; OUTPUT_D ; 11.576 ; 11.576 ; 11.576 ; 11.576 ; +; INPUT_A ; OUTPUT_E ; ; 11.915 ; 11.915 ; ; +; INPUT_A ; OUTPUT_F ; ; 11.165 ; 11.165 ; ; +; INPUT_A ; OUTPUT_G ; ; 11.134 ; 11.134 ; ; +; INPUT_B ; OUTPUT_A ; 13.063 ; 13.063 ; 13.063 ; 13.063 ; +; INPUT_B ; OUTPUT_B ; 10.961 ; 10.961 ; 10.961 ; 10.961 ; +; INPUT_B ; OUTPUT_C ; ; 11.208 ; 11.208 ; ; +; INPUT_B ; OUTPUT_D ; 11.341 ; 11.341 ; 11.341 ; 11.341 ; +; INPUT_B ; OUTPUT_E ; 11.754 ; ; ; 11.754 ; +; INPUT_B ; OUTPUT_F ; ; 10.967 ; 10.967 ; ; +; INPUT_B ; OUTPUT_G ; 10.907 ; 10.907 ; 10.907 ; 10.907 ; +; INPUT_C ; OUTPUT_A ; 13.132 ; 13.132 ; 13.132 ; 13.132 ; +; INPUT_C ; OUTPUT_B ; ; 11.046 ; 11.046 ; ; +; INPUT_C ; OUTPUT_C ; 11.293 ; 11.293 ; 11.293 ; 11.293 ; +; INPUT_C ; OUTPUT_D ; 11.455 ; 11.455 ; 11.455 ; 11.455 ; +; INPUT_C ; OUTPUT_E ; ; 11.838 ; 11.838 ; ; +; INPUT_C ; OUTPUT_F ; 11.037 ; ; ; 11.037 ; +; INPUT_C ; OUTPUT_G ; 11.006 ; 11.006 ; 11.006 ; 11.006 ; +; INPUT_D ; OUTPUT_A ; 12.550 ; 12.550 ; 12.550 ; 12.550 ; +; INPUT_D ; OUTPUT_B ; ; 10.467 ; 10.467 ; ; +; INPUT_D ; OUTPUT_C ; ; 10.711 ; 10.711 ; ; +; INPUT_D ; OUTPUT_F ; 10.455 ; ; ; 10.455 ; +; INPUT_D ; OUTPUT_G ; 10.396 ; ; ; 10.396 ; ++------------+-------------+--------+--------+--------+--------+ + + +---------------------------- +; Fast Model Setup Summary ; +---------------------------- +No paths to report. + + +--------------------------- +; Fast Model Hold Summary ; +--------------------------- +No paths to report. + + +------------------------------- +; Fast Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Fast Model Removal Summary ; +------------------------------ +No paths to report. + + +------------------------------------------ +; Fast Model Minimum Pulse Width Summary ; +------------------------------------------ +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; INPUT_A ; OUTPUT_A ; 6.571 ; 6.571 ; 6.571 ; 6.571 ; +; INPUT_A ; OUTPUT_B ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; +; INPUT_A ; OUTPUT_C ; 5.804 ; ; ; 5.804 ; +; INPUT_A ; OUTPUT_D ; 5.915 ; 5.915 ; 5.915 ; 5.915 ; +; INPUT_A ; OUTPUT_E ; ; 5.997 ; 5.997 ; ; +; INPUT_A ; OUTPUT_F ; ; 5.727 ; 5.727 ; ; +; INPUT_A ; OUTPUT_G ; ; 5.695 ; 5.695 ; ; +; INPUT_B ; OUTPUT_A ; 6.383 ; 6.383 ; 6.383 ; 6.383 ; +; INPUT_B ; OUTPUT_B ; 5.531 ; 5.531 ; 5.531 ; 5.531 ; +; INPUT_B ; OUTPUT_C ; ; 5.611 ; 5.611 ; ; +; INPUT_B ; OUTPUT_D ; 5.720 ; 5.720 ; 5.720 ; 5.720 ; +; INPUT_B ; OUTPUT_E ; 5.802 ; ; ; 5.802 ; +; INPUT_B ; OUTPUT_F ; ; 5.541 ; 5.541 ; ; +; INPUT_B ; OUTPUT_G ; 5.510 ; 5.510 ; 5.510 ; 5.510 ; +; INPUT_C ; OUTPUT_A ; 6.508 ; 6.508 ; 6.508 ; 6.508 ; +; INPUT_C ; OUTPUT_B ; ; 5.669 ; 5.669 ; ; +; INPUT_C ; OUTPUT_C ; 5.747 ; 5.747 ; 5.747 ; 5.747 ; +; INPUT_C ; OUTPUT_D ; 5.857 ; 5.857 ; 5.857 ; 5.857 ; +; INPUT_C ; OUTPUT_E ; ; 5.940 ; 5.940 ; ; +; INPUT_C ; OUTPUT_F ; 5.661 ; ; ; 5.661 ; +; INPUT_C ; OUTPUT_G ; 5.629 ; 5.629 ; 5.629 ; 5.629 ; +; INPUT_D ; OUTPUT_A ; 6.185 ; 6.185 ; 6.185 ; 6.185 ; +; INPUT_D ; OUTPUT_B ; ; 5.349 ; 5.349 ; ; +; INPUT_D ; OUTPUT_C ; ; 5.434 ; 5.434 ; ; +; INPUT_D ; OUTPUT_F ; 5.338 ; ; ; 5.338 ; +; INPUT_D ; OUTPUT_G ; 5.310 ; ; ; 5.310 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; INPUT_A ; OUTPUT_A ; 6.571 ; 6.571 ; 6.571 ; 6.571 ; +; INPUT_A ; OUTPUT_B ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; +; INPUT_A ; OUTPUT_C ; 5.804 ; ; ; 5.804 ; +; INPUT_A ; OUTPUT_D ; 5.915 ; 5.915 ; 5.915 ; 5.915 ; +; INPUT_A ; OUTPUT_E ; ; 5.997 ; 5.997 ; ; +; INPUT_A ; OUTPUT_F ; ; 5.727 ; 5.727 ; ; +; INPUT_A ; OUTPUT_G ; ; 5.695 ; 5.695 ; ; +; INPUT_B ; OUTPUT_A ; 6.383 ; 6.383 ; 6.383 ; 6.383 ; +; INPUT_B ; OUTPUT_B ; 5.531 ; 5.531 ; 5.531 ; 5.531 ; +; INPUT_B ; OUTPUT_C ; ; 5.611 ; 5.611 ; ; +; INPUT_B ; OUTPUT_D ; 5.720 ; 5.720 ; 5.720 ; 5.720 ; +; INPUT_B ; OUTPUT_E ; 5.802 ; ; ; 5.802 ; +; INPUT_B ; OUTPUT_F ; ; 5.541 ; 5.541 ; ; +; INPUT_B ; OUTPUT_G ; 5.510 ; 5.510 ; 5.510 ; 5.510 ; +; INPUT_C ; OUTPUT_A ; 6.508 ; 6.508 ; 6.508 ; 6.508 ; +; INPUT_C ; OUTPUT_B ; ; 5.669 ; 5.669 ; ; +; INPUT_C ; OUTPUT_C ; 5.747 ; 5.747 ; 5.747 ; 5.747 ; +; INPUT_C ; OUTPUT_D ; 5.857 ; 5.857 ; 5.857 ; 5.857 ; +; INPUT_C ; OUTPUT_E ; ; 5.940 ; 5.940 ; ; +; INPUT_C ; OUTPUT_F ; 5.661 ; ; ; 5.661 ; +; INPUT_C ; OUTPUT_G ; 5.629 ; 5.629 ; 5.629 ; 5.629 ; +; INPUT_D ; OUTPUT_A ; 6.185 ; 6.185 ; 6.185 ; 6.185 ; +; INPUT_D ; OUTPUT_B ; ; 5.349 ; 5.349 ; ; +; INPUT_D ; OUTPUT_C ; ; 5.434 ; 5.434 ; ; +; INPUT_D ; OUTPUT_F ; 5.338 ; ; ; 5.338 ; +; INPUT_D ; OUTPUT_G ; 5.310 ; ; ; 5.310 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++--------------------------------------------------------------+ +; Progagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; INPUT_A ; OUTPUT_A ; 13.260 ; 13.260 ; 13.260 ; 13.260 ; +; INPUT_A ; OUTPUT_B ; 11.167 ; 11.167 ; 11.167 ; 11.167 ; +; INPUT_A ; OUTPUT_C ; 11.414 ; ; ; 11.414 ; +; INPUT_A ; OUTPUT_D ; 11.576 ; 11.576 ; 11.576 ; 11.576 ; +; INPUT_A ; OUTPUT_E ; ; 11.915 ; 11.915 ; ; +; INPUT_A ; OUTPUT_F ; ; 11.165 ; 11.165 ; ; +; INPUT_A ; OUTPUT_G ; ; 11.134 ; 11.134 ; ; +; INPUT_B ; OUTPUT_A ; 13.063 ; 13.063 ; 13.063 ; 13.063 ; +; INPUT_B ; OUTPUT_B ; 10.961 ; 10.961 ; 10.961 ; 10.961 ; +; INPUT_B ; OUTPUT_C ; ; 11.208 ; 11.208 ; ; +; INPUT_B ; OUTPUT_D ; 11.341 ; 11.341 ; 11.341 ; 11.341 ; +; INPUT_B ; OUTPUT_E ; 11.754 ; ; ; 11.754 ; +; INPUT_B ; OUTPUT_F ; ; 10.967 ; 10.967 ; ; +; INPUT_B ; OUTPUT_G ; 10.907 ; 10.907 ; 10.907 ; 10.907 ; +; INPUT_C ; OUTPUT_A ; 13.132 ; 13.132 ; 13.132 ; 13.132 ; +; INPUT_C ; OUTPUT_B ; ; 11.046 ; 11.046 ; ; +; INPUT_C ; OUTPUT_C ; 11.293 ; 11.293 ; 11.293 ; 11.293 ; +; INPUT_C ; OUTPUT_D ; 11.455 ; 11.455 ; 11.455 ; 11.455 ; +; INPUT_C ; OUTPUT_E ; ; 11.838 ; 11.838 ; ; +; INPUT_C ; OUTPUT_F ; 11.037 ; ; ; 11.037 ; +; INPUT_C ; OUTPUT_G ; 11.006 ; 11.006 ; 11.006 ; 11.006 ; +; INPUT_D ; OUTPUT_A ; 12.550 ; 12.550 ; 12.550 ; 12.550 ; +; INPUT_D ; OUTPUT_B ; ; 10.467 ; 10.467 ; ; +; INPUT_D ; OUTPUT_C ; ; 10.711 ; 10.711 ; ; +; INPUT_D ; OUTPUT_F ; 10.455 ; ; ; 10.455 ; +; INPUT_D ; OUTPUT_G ; 10.396 ; ; ; 10.396 ; ++------------+-------------+--------+--------+--------+--------+ + + ++----------------------------------------------------------+ +; Minimum Progagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; INPUT_A ; OUTPUT_A ; 6.571 ; 6.571 ; 6.571 ; 6.571 ; +; INPUT_A ; OUTPUT_B ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; +; INPUT_A ; OUTPUT_C ; 5.804 ; ; ; 5.804 ; +; INPUT_A ; OUTPUT_D ; 5.915 ; 5.915 ; 5.915 ; 5.915 ; +; INPUT_A ; OUTPUT_E ; ; 5.997 ; 5.997 ; ; +; INPUT_A ; OUTPUT_F ; ; 5.727 ; 5.727 ; ; +; INPUT_A ; OUTPUT_G ; ; 5.695 ; 5.695 ; ; +; INPUT_B ; OUTPUT_A ; 6.383 ; 6.383 ; 6.383 ; 6.383 ; +; INPUT_B ; OUTPUT_B ; 5.531 ; 5.531 ; 5.531 ; 5.531 ; +; INPUT_B ; OUTPUT_C ; ; 5.611 ; 5.611 ; ; +; INPUT_B ; OUTPUT_D ; 5.720 ; 5.720 ; 5.720 ; 5.720 ; +; INPUT_B ; OUTPUT_E ; 5.802 ; ; ; 5.802 ; +; INPUT_B ; OUTPUT_F ; ; 5.541 ; 5.541 ; ; +; INPUT_B ; OUTPUT_G ; 5.510 ; 5.510 ; 5.510 ; 5.510 ; +; INPUT_C ; OUTPUT_A ; 6.508 ; 6.508 ; 6.508 ; 6.508 ; +; INPUT_C ; OUTPUT_B ; ; 5.669 ; 5.669 ; ; +; INPUT_C ; OUTPUT_C ; 5.747 ; 5.747 ; 5.747 ; 5.747 ; +; INPUT_C ; OUTPUT_D ; 5.857 ; 5.857 ; 5.857 ; 5.857 ; +; INPUT_C ; OUTPUT_E ; ; 5.940 ; 5.940 ; ; +; INPUT_C ; OUTPUT_F ; 5.661 ; ; ; 5.661 ; +; INPUT_C ; OUTPUT_G ; 5.629 ; 5.629 ; 5.629 ; 5.629 ; +; INPUT_D ; OUTPUT_A ; 6.185 ; 6.185 ; 6.185 ; 6.185 ; +; INPUT_D ; OUTPUT_B ; ; 5.349 ; 5.349 ; ; +; INPUT_D ; OUTPUT_C ; ; 5.434 ; 5.434 ; ; +; INPUT_D ; OUTPUT_F ; 5.338 ; ; ; 5.338 ; +; INPUT_D ; OUTPUT_G ; 5.310 ; ; ; 5.310 ; ++------------+-------------+-------+-------+-------+-------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 4 ; 4 ; +; Unconstrained Input Port Paths ; 26 ; 26 ; +; Unconstrained Output Ports ; 7 ; 7 ; +; Unconstrained Output Port Paths ; 26 ; 26 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 17:00:28 2020 +Info: Command: quartus_sta YL_dec7748 -c YL_dec7748 +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_dec7748.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332001): The selected device family is not supported by the report_metastability command. +Info: Analyzing Fast Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 4541 megabytes + Info: Processing ended: Sun May 03 17:00:29 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/Exp28/output_files/YL_dec7748.sta.summary b/Exp28/output_files/YL_dec7748.sta.summary new file mode 100644 index 0000000..33f7436 --- /dev/null +++ b/Exp28/output_files/YL_dec7748.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/Exp28/simulation/qsim/YL_dec7748.sim.vwf b/Exp28/simulation/qsim/YL_dec7748.sim.vwf new file mode 100644 index 0000000..a042ec7 --- /dev/null +++ b/Exp28/simulation/qsim/YL_dec7748.sim.vwf @@ -0,0 +1,437 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 1000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("INPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("INPUT_A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_C") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 63.26; + LEVEL 0 FOR 49.803; + LEVEL 1 FOR 100.069; + LEVEL 0 FOR 50.128; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 49.29; + LEVEL 0 FOR 0.582; + LEVEL 1 FOR 99.931; + LEVEL 0 FOR 150.197; + LEVEL 1 FOR 49.803; + LEVEL 0 FOR 99.487; + LEVEL 1 FOR 50.71; + LEVEL 0 FOR 49.803; + LEVEL 1 FOR 86.937; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 261.167; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 49.3; + LEVEL 0 FOR 0.7; + LEVEL 1 FOR 99.794; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 50.206; + LEVEL 0 FOR 149.3; + LEVEL 1 FOR 189.533; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 111.414; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 249.297; + LEVEL 0 FOR 0.582; + LEVEL 1 FOR 100.121; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 49.879; + LEVEL 0 FOR 199.418; + LEVEL 1 FOR 100.703; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 38.586; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 61.576; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 49.765; + LEVEL 1 FOR 100.114; + LEVEL 0 FOR 50.121; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 49.879; + LEVEL 1 FOR 50.121; + } + LEVEL 0 FOR 49.765; + LEVEL 1 FOR 88.659; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 61.915; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 49.923; + LEVEL 1 FOR 50.077; + } + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 38.085; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 61.165; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 49.802; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 150.198; + LEVEL 0 FOR 49.802; + LEVEL 1 FOR 50.198; + LEVEL 0 FOR 138.835; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.907; + LEVEL 1 FOR 250.227; + LEVEL 0 FOR 49.773; + LEVEL 1 FOR 350.227; + LEVEL 0 FOR 149.773; + LEVEL 1 FOR 89.093; + } +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/7segment.bsf b/Exp28_Decoder/7segment.bsf new file mode 100644 index 0000000..c9f4ae8 --- /dev/null +++ b/Exp28_Decoder/7segment.bsf @@ -0,0 +1,85 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 144 192) + (text "7segment" (rect 5 0 43 12)(font "Arial" )) + (text "inst" (rect 8 160 20 172)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "i[3..0]" (rect 0 0 21 12)(font "Arial" )) + (text "i[3..0]" (rect 21 27 42 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 128 32) + (output) + (text "a" (rect 0 0 4 12)(font "Arial" )) + (text "a" (rect 103 27 107 39)(font "Arial" )) + (line (pt 128 32)(pt 112 32)(line_width 1)) + ) + (port + (pt 128 48) + (output) + (text "b" (rect 0 0 4 12)(font "Arial" )) + (text "b" (rect 103 43 107 55)(font "Arial" )) + (line (pt 128 48)(pt 112 48)(line_width 1)) + ) + (port + (pt 128 64) + (output) + (text "c" (rect 0 0 4 12)(font "Arial" )) + (text "c" (rect 103 59 107 71)(font "Arial" )) + (line (pt 128 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 128 80) + (output) + (text "d" (rect 0 0 4 12)(font "Arial" )) + (text "d" (rect 103 75 107 87)(font "Arial" )) + (line (pt 128 80)(pt 112 80)(line_width 1)) + ) + (port + (pt 128 96) + (output) + (text "e" (rect 0 0 4 12)(font "Arial" )) + (text "e" (rect 103 91 107 103)(font "Arial" )) + (line (pt 128 96)(pt 112 96)(line_width 1)) + ) + (port + (pt 128 112) + (output) + (text "f" (rect 0 0 3 12)(font "Arial" )) + (text "f" (rect 104 107 107 119)(font "Arial" )) + (line (pt 128 112)(pt 112 112)(line_width 1)) + ) + (port + (pt 128 128) + (output) + (text "g" (rect 0 0 4 12)(font "Arial" )) + (text "g" (rect 103 123 107 135)(font "Arial" )) + (line (pt 128 128)(pt 112 128)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 112 160)(line_width 1)) + ) +) diff --git a/Exp28_Decoder/YL_7SegmentDecoder.bdf b/Exp28_Decoder/YL_7SegmentDecoder.bdf new file mode 100644 index 0000000..d9b456d --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder.bdf @@ -0,0 +1,1195 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect -88 216 80 232) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "ent" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect -160 208 -104 224)) +) +(pin + (input) + (rect -88 232 80 248) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 19 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" 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160 504) +) +(connector + (pt 336 368) + (pt 336 232) +) +(connector + (pt 336 368) + (pt 160 368) +) +(connector + (pt 160 368) + (pt 160 456) +) +(connector + (pt 80 240) + (pt 104 240) +) +(connector + (pt 104 240) + (pt 160 240) +) +(connector + (pt 104 48) + (pt 104 240) +) +(connector + (pt 104 240) + (pt 104 488) +) +(connector + (pt 328 216) + (pt 384 216) + (bus) +) +(connector + (pt 80 224) + (pt 160 224) +) +(connector + (pt 128 472) + (pt 160 472) +) +(connector + (pt 128 144) + (pt 128 208) +) +(connector + (pt 128 208) + (pt 128 472) +) +(junction (pt 104 240)) +(junction (pt 80 256)) +(junction (pt 128 208)) diff --git a/Exp28_Decoder/YL_7SegmentDecoder.qpf b/Exp28_Decoder/YL_7SegmentDecoder.qpf new file mode 100644 index 0000000..a5300f8 --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 17:23:33 May 03, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "17:23:33 May 03, 2020" + +# Revisions + +PROJECT_REVISION = "YL_7SegmentDecoder" diff --git a/Exp28_Decoder/YL_7SegmentDecoder.qsf b/Exp28_Decoder/YL_7SegmentDecoder.qsf new file mode 100644 index 0000000..a2b3be8 --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder.qsf @@ -0,0 +1,83 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 17:23:33 May 03, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# YL_7SegmentDecoder_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY YL_7SegmentDecoder +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:23:33 MAY 03, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_J2 -to OUTPUT_A +set_location_assignment PIN_J1 -to OUTPUT_B +set_location_assignment PIN_H2 -to OUTPUT_C +set_location_assignment PIN_H1 -to OUTPUT_D +set_location_assignment PIN_F2 -to OUTPUT_E +set_location_assignment PIN_F1 -to OUTPUT_F +set_location_assignment PIN_E2 -to OUTPUT_G +set_global_assignment -name SIMULATION_MODE FUNCTIONAL +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF +set_global_assignment -name AHDL_FILE YL_dec_counter.tdf +set_global_assignment -name BDF_FILE YL_7SegmentDecoder.bdf +set_global_assignment -name AHDL_FILE YL_7SegmentDecoder.tdf +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_7SegmentDecoder.vwf +set_global_assignment -name BDF_FILE YL_7SegmentDecoder2.bdf +set_location_assignment PIN_M22 -to clear +set_location_assignment PIN_L1 -to clk +set_location_assignment PIN_L22 -to enc +set_location_assignment PIN_L21 -to ent +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_7SegmentDecoder2.vwf +set_global_assignment -name AHDL_FILE YL_sec_cnt.tdf +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_7SegmentDecoder3.vwf +set_global_assignment -name BDF_FILE YL_Cascade.bdf +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_cascade.vwf +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_cascade.vwf" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Exp28_Decoder/YL_7SegmentDecoder.qws b/Exp28_Decoder/YL_7SegmentDecoder.qws new file mode 100644 index 0000000000000000000000000000000000000000..c4ecd3153e5a706e735eb95a2c7df20012aed90a GIT binary patch literal 5671 zcmeI0O>0v@6o$`DMC(ReiJ(Xjks{>drnjW6n_{Y~g5U>I5K5Zd)Y6ZXBw9tPdvT+< z5nQU7zq2>^3;& zZJBa~6>dkJu{m%G-T~=KxWFrc8e%CPwd;rOd44Ek^{B6J5=;`K)qo1fT$Q-WleP= zQHnTP0g+Z)7r^N1l87X~f>~;9v*@*5jHFSb!(_ZKpFg>Q%)avY9Q$#S)x4$sojgIG zX%eq!x00Azz@$E06A!D7pLrzWWg58;a^EpkoD_R={PN@y+EvO?bQRUa)VM|q=bf^! z_kp6DxrsW$_Xr1rxnk13nR^z(EkQus3-ay3*`bbt7k^d?LpCNXK z99T*5(qDXXKkxkEw)t_F^;;;fiDLOi6=^n0NL2otlkfbi&#eok0s_w;qFz+B6aI9siH-ePsz(3W`7ur^@d=l?&f9Wq1XdZKjq&m+cmUEA>99XFD`eu%v>2g#Bj zi7Ol#qy5%X_aXk5cc6a7)SmxHIEEhGc{uIx$Aa7N&QYno`*FVWL a, b, c, d, e, f, g; + H"0" => 1, 1, 1, 1, 1, 1, 0; + H"1" => 0, 1, 1, 0, 0, 0, 0; + H"2" => 1, 1, 0, 1, 1, 0, 1; + H"3" => 1, 1, 1, 1, 0, 0, 1; + H"4" => 0, 1, 1, 0, 0, 1, 1; + H"5" => 1, 0, 1, 1, 0, 1, 1; + H"6" => 1, 0, 1, 1, 1, 1, 1; + H"7" => 1, 1, 1, 0, 0, 0, 0; + H"8" => 1, 1, 1, 1, 1, 1, 1; + H"9" => 1, 1, 1, 1, 0, 1, 1; + H"A" => 1, 1, 1, 0, 1, 1, 1; + H"B" => 0, 0, 1, 1, 1, 1, 1; + H"C" => 1, 0, 0, 1, 1, 1, 0; + H"D" => 0, 1, 1, 1, 1, 0, 1; + H"E" => 1, 0, 0, 1, 1, 1, 1; + H"F" => 1, 0, 0, 0, 1, 1, 1; + END TABLE; +END; diff --git a/Exp28_Decoder/YL_7SegmentDecoder.vwf b/Exp28_Decoder/YL_7SegmentDecoder.vwf new file mode 100644 index 0000000..9a3ca7d --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder.vwf @@ -0,0 +1,394 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("in") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in"; +} + +SIGNAL("in[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in"; +} + +SIGNAL("in[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in"; +} + +SIGNAL("in[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in"; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("in[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("in[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("in[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("in[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "in"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4; +} + +DISPLAY_LINE +{ + CHANNEL = "in[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/YL_7SegmentDecoder.vwf.temp b/Exp28_Decoder/YL_7SegmentDecoder.vwf.temp new file mode 100644 index 0000000..721d569 --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder.vwf.temp @@ -0,0 +1,371 @@ +/* Simulator = Quartus II Simulator */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("in[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("in[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("in[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("in[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("in[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "in[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/YL_7SegmentDecoder2.bdf b/Exp28_Decoder/YL_7SegmentDecoder2.bdf new file mode 100644 index 0000000..04f8c53 --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder2.bdf @@ -0,0 +1,160 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 120 112 288 128) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "pin_name2" (rect 5 0 58 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 120 128 288 144) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "pin_name3" (rect 5 0 58 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 120 144 288 160) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "pin_name4" (rect 5 0 58 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 112 96 288 112) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "pin_name1" (rect 9 0 62 12)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(symbol + (rect 304 72 464 184) + (text "dec_count" (rect 5 0 55 12)(font "Arial" )) + (text "inst8" (rect 8 96 31 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "enc" (rect 0 0 17 12)(font "Arial" )) + (text "enc" (rect 21 27 38 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "ent" (rect 0 0 15 12)(font "Arial" )) + (text "ent" (rect 21 43 36 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "clk" (rect 0 0 14 12)(font "Arial" )) + (text "clk" (rect 21 59 35 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "clear" (rect 0 0 23 12)(font "Arial" )) + (text "clear" (rect 21 75 44 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 160 32) + (output) + (text "value[3..0]" (rect 0 0 53 12)(font "Arial" )) + (text "value[3..0]" (rect 95 27 148 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 48) + (output) + (text "rco" (rect 0 0 15 12)(font "Arial" )) + (text "rco" (rect 127 43 142 55)(font "Arial" )) + (line (pt 160 48)(pt 144 48)) + ) + (drawing + (rectangle (rect 16 16 144 96)) + ) +) +(connector + (pt 288 104) + (pt 304 104) +) +(connector + (pt 288 120) + (pt 304 120) +) +(connector + (pt 288 136) + (pt 304 136) +) +(connector + (pt 288 152) + (pt 304 152) +) +(connector + (pt 464 120) + (pt 472 120) +) +(connector + (pt 464 104) + (pt 480 104) + (bus) +) diff --git a/Exp28_Decoder/YL_7SegmentDecoder2.vwf b/Exp28_Decoder/YL_7SegmentDecoder2.vwf new file mode 100644 index 0000000..a44cf0f --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder2.vwf @@ -0,0 +1,361 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("enc") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 840.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + } +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("enc") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 680.0; + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 580.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "enc"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/YL_7SegmentDecoder3.vwf b/Exp28_Decoder/YL_7SegmentDecoder3.vwf new file mode 100644 index 0000000..32e90f2 --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder3.vwf @@ -0,0 +1,336 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 3000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 2480.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 440.0; + } +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 150; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1680.0; + LEVEL 0 FOR 560.0; + LEVEL 1 FOR 760.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 2001.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 2001.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 2001.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 2001.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 2001.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 2001.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 2001.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/YL_7SegmentDecoder3.vwf.temp b/Exp28_Decoder/YL_7SegmentDecoder3.vwf.temp new file mode 100644 index 0000000..ad7c06c --- /dev/null +++ b/Exp28_Decoder/YL_7SegmentDecoder3.vwf.temp @@ -0,0 +1,321 @@ +/* Simulator = Quartus II Simulator */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/YL_7segment_sign.tdf b/Exp28_Decoder/YL_7segment_sign.tdf new file mode 100644 index 0000000..7d5dde1 --- /dev/null +++ b/Exp28_Decoder/YL_7segment_sign.tdf @@ -0,0 +1,25 @@ +% 0 1 2 3 4 5 6 7 8 9 A b C d E F % +% % +SUBDESIGN 7segment +( + sign : INPUT; + a, b, c, d, e, f, g : OUTPUT; +) +BEGIN + + DEFAULTS + a = VCC; + b = VCC; + c = VCC; + d = VCC; + e = VCC; + f = VCC; + g = VCC; + END DEFAULTS; + + IF sign THEN + g = GND; + ELSE + g = VCC; + END iF; +END; diff --git a/Exp28_Decoder/YL_7segment_sign.tdf.bak b/Exp28_Decoder/YL_7segment_sign.tdf.bak new file mode 100644 index 0000000..5865cb1 --- /dev/null +++ b/Exp28_Decoder/YL_7segment_sign.tdf.bak @@ -0,0 +1,28 @@ +% 0 1 2 3 4 5 6 7 8 9 A b C d E F % +% % +SUBDESIGN 7segment +( + i[3..0] : INPUT; + a, b, c, d, e, f, g : OUTPUT; +) +BEGIN + TABLE + i[3..0] => a, b, c, d, e, f, g; + H"0" => 1, 1, 1, 1, 1, 1, 0; + H"1" => 0, 1, 1, 0, 0, 0, 0; + H"2" => 1, 1, 0, 1, 1, 0, 1; + H"3" => 1, 1, 1, 1, 0, 0, 1; + H"4" => 0, 1, 1, 0, 0, 1, 1; + H"5" => 1, 0, 1, 1, 0, 1, 1; + H"6" => 1, 0, 1, 1, 1, 1, 1; + H"7" => 1, 1, 1, 0, 0, 0, 0; + H"8" => 1, 1, 1, 1, 1, 1, 1; + H"9" => 1, 1, 1, 1, 0, 1, 1; + H"A" => 1, 1, 1, 0, 1, 1, 1; + H"B" => 0, 0, 1, 1, 1, 1, 1; + H"C" => 1, 0, 0, 1, 1, 1, 0; + H"D" => 0, 1, 1, 1, 1, 0, 1; + H"E" => 1, 0, 0, 1, 1, 1, 1; + H"F" => 1, 0, 0, 0, 1, 1, 1; + END TABLE; +END; diff --git a/Exp28_Decoder/YL_Cascade.bdf b/Exp28_Decoder/YL_Cascade.bdf new file mode 100644 index 0000000..76278db --- /dev/null +++ b/Exp28_Decoder/YL_Cascade.bdf @@ -0,0 +1,1199 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 30000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 26880.0; + LEVEL 1 FOR 640.0; + LEVEL 0 FOR 2480.0; + } +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1500; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 16640.0; + LEVEL 0 FOR 3840.0; + LEVEL 1 FOR 9520.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_A1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_C3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_D4") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_E5") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_F6") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +TRANSITION_LIST("OUTPUT_G7") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 999.0; + LEVEL 0 FOR 29001.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/YL_dec_counter.tdf b/Exp28_Decoder/YL_dec_counter.tdf new file mode 100644 index 0000000..fff354f --- /dev/null +++ b/Exp28_Decoder/YL_dec_counter.tdf @@ -0,0 +1,25 @@ +SUBDESIGN dec_count +( + enc, ent, clk : INPUT; % two enables and the clock % + clear : INPUT; % Synchronous clear % + value[3..0] : OUTPUT; % Four output bits % + rco : OUTPUT; % ripple carry out % +) +VARIABLE + count[3..0] : DFF; % locally define 4 D-Flip-Flops for the count % +BEGIN + count[].clk = clk; % Connect the clock input to the DFF’s clock % + value[] = count[]; % connect the outputs of the DFFs to the outputs % + IF (clear) THEN % if clear is true clear the count i.e. % + count[].d = 0; % load the flipflops with zero % + ELSIF (enc & ent & (count[].q != 11)) THEN + % if both enables are true and the count does not % + count[].d = count[].q + 1; % equal nine then add one to the count value % + ELSIF (enc & ent & (count[].q == 11)) THEN + % if both enables are true and the count does % + count[].d = 0; % equal nine then load the flip flops with zero % + ELSE % with no enable keep the flips flops at the same value % + count[].d = count[].q; + END IF; + rco = ((count[].q == 11) & ent);% generate the rco when the count is nine and ent is true % +END; diff --git a/Exp28_Decoder/YL_dec_counter.tdf.bak b/Exp28_Decoder/YL_dec_counter.tdf.bak new file mode 100644 index 0000000..33f4b64 --- /dev/null +++ b/Exp28_Decoder/YL_dec_counter.tdf.bak @@ -0,0 +1,25 @@ +SUBDESIGN dec_count +( + enc, ent, clk : INPUT; % two enables and the clock % + clear : INPUT; % Synchronous clear % + value[3..0] : OUTPUT; % Four output bits % + rco : OUTPUT; % ripple carry out % +) +VARIABLE + count[3..0] : DFF; % locally define 4 D-Flip-Flops for the count % +BEGIN + count[].clk = clk; % Connect the clock input to the DFF’s clock % + value[] = count[]; % connect the outputs of the DFFs to the outputs % + IF (clear) THEN % if clear is true clear the count i.e. % + count[].d = 0; % load the flipflops with zero % + ELSIF (enc & ent & (count[].q != 9)) THEN + % if both enables are true and the count does not % + count[].d = count[].q + 1; % equal nine then add one to the count value % + ELSIF (enc & ent & (count[].q == 9)) THEN + % if both enables are true and the count does % + count[].d = 0; % equal nine then load the flip flops with zero % + ELSE % with no enable keep the flips flops at the same value % + count[].d = count[].q; + END IF; + rco = ((count[].q == 9) & ent);% generate the rco when the count is nine and ent is true % +END; diff --git a/Exp28_Decoder/YL_sec_cnt.tdf b/Exp28_Decoder/YL_sec_cnt.tdf new file mode 100644 index 0000000..786be19 --- /dev/null +++ b/Exp28_Decoder/YL_sec_cnt.tdf @@ -0,0 +1,17 @@ +SUBDESIGN sec_cnt +( + clk : INPUT; + second : OUTPUT; +) +VARIABLE + count[25..0] : DFF; +BEGIN + count[].clk = clk; + IF ((count[].q == 5)) THEN + count[].d = 0; + second = VCC; + ELSE + count[].d = count[].q + 1; + second = GND; + END IF; +END; \ No newline at end of file diff --git a/Exp28_Decoder/YL_sec_cnt.tdf.bak b/Exp28_Decoder/YL_sec_cnt.tdf.bak new file mode 100644 index 0000000..ec54875 --- /dev/null +++ b/Exp28_Decoder/YL_sec_cnt.tdf.bak @@ -0,0 +1,17 @@ +SUBDESIGN sec_cnt +( +clk : INPUT; +second : OUTPUT; +) +VARIABLE +count[25..0] : DFF; +BEGIN +count[].clk = clk; +IF ((count[].q == 50000000)) THEN +count[].d = 0; +second = VCC; +ELSE +count[].d = count[].q + 1; +second = GND; +END IF; +END; \ No newline at end of file diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.(0).cnf.cdb b/Exp28_Decoder/db/YL_7SegmentDecoder.(0).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..915b76bdad1186ba219cb2722e72c9418bab845f GIT binary patch literal 1608 zcmV-O2DkYU000233jqKC0CNCy073u&09Ivkb7^mGATcv8FfK75LUn0uWFRs#G9WNE zFEKJNGB7bSAX8;>c4=c}AW&grYalToQ%WFLWnv&jWNCD1Z*EN=00000007Vg00000 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z+>9FB@Hq2Ir@QAJ8Z)tbW?>(Ib7>4^ZfBlup02K*A>Y=_G|+b9myZrpp5gcSMKyFY zJkJR_II5Jc?5GSP+O1fiq!go)jVlp1(0W`z8UCJf!y<~j#86QWfSFri?(n69R@V19 zsW8zhpMc;iw3I_}2{k|qVNu_}%KJ87QE=X}CTKw4ShBqzE}^mL3EKndr=wc-8!{{UicE{y;H literal 0 HcmV?d00001 diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.sim.vwf b/Exp28_Decoder/db/YL_7SegmentDecoder.sim.vwf new file mode 100644 index 0000000..cbf6416 --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.sim.vwf @@ -0,0 +1,809 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 30000.0; + SIMULATION_TIME = 30000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 26880.0; + LEVEL 1 FOR 640.0; + LEVEL 0 FOR 2480.0; + } +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1500; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 16640.0; + LEVEL 0 FOR 3840.0; + LEVEL 1 FOR 9520.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 4560.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 490.0; + } +} + +TRANSITION_LIST("OUTPUT_A1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 8640.0; + LEVEL 1 FOR 5280.0; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 2020.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + } + LEVEL 1 FOR 4080.0; + NODE + { + REPEAT = 4; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 240.0; + } + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1200.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 250.0; + } +} + +TRANSITION_LIST("OUTPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 7190.0; + LEVEL 1 FOR 2880.0; + LEVEL 0 FOR 5760.0; + LEVEL 1 FOR 5280.0; + LEVEL 0 FOR 8890.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1320.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 5160.0; + NODE + { + REPEAT = 3; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1320.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1920.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1320.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 730.0; + } +} + +TRANSITION_LIST("OUTPUT_C3") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 2870.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 19680.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 4570.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 45; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 4080.0; + NODE + { + REPEAT = 17; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 840.0; + NODE + { + REPEAT = 6; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 130.0; + } +} + +TRANSITION_LIST("OUTPUT_D4") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + NODE + { + REPEAT = 3; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + } + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 6720.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 2020.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 10; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + LEVEL 0 FOR 360.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 3960.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + NODE + { + REPEAT = 4; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + } + LEVEL 0 FOR 960.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 10.0; + } +} + +TRANSITION_LIST("OUTPUT_E5") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 4320.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 1440.0; + } + LEVEL 0 FOR 8160.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 1460.0; + LEVEL 0 FOR 2020.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + } + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 4200.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1200.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 130.0; + } +} + +TRANSITION_LIST("OUTPUT_F6") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + LEVEL 1 FOR 4320.0; + LEVEL 0 FOR 4320.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 11040.0; + LEVEL 1 FOR 4320.0; + LEVEL 0 FOR 2040.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 230.0; + NODE + { + REPEAT = 11; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 240.0; + } + LEVEL 0 FOR 4440.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 600.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 840.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 130.0; + } +} + +TRANSITION_LIST("OUTPUT_G7") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 2870.0; + LEVEL 0 FOR 7200.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 9600.0; + LEVEL 1 FOR 2880.0; + LEVEL 0 FOR 2900.0; + LEVEL 1 FOR 3110.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.simfam b/Exp28_Decoder/db/YL_7SegmentDecoder.simfam new file mode 100644 index 0000000..37dc84f --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.simfam @@ -0,0 +1,2 @@ +BOF +EOF diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.sld_design_entry.sci b/Exp28_Decoder/db/YL_7SegmentDecoder.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.sld_design_entry_dsc.sci b/Exp28_Decoder/db/YL_7SegmentDecoder.sld_design_entry_dsc.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.smart_action.txt b/Exp28_Decoder/db/YL_7SegmentDecoder.smart_action.txt new file mode 100644 index 0000000..11b531f --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.sta.qmsg b/Exp28_Decoder/db/YL_7SegmentDecoder.sta.qmsg new file mode 100644 index 0000000..8190d63 --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.sta.qmsg @@ -0,0 +1,30 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588514809854 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588514809855 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 22:06:49 2020 " "Processing started: Sun May 03 22:06:49 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588514809855 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588514809855 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588514809856 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588514810018 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588514810232 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588514810321 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588514810321 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_7SegmentDecoder.sdc " "Synopsys Design Constraints File file not found: 'YL_7SegmentDecoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588514810515 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588514810516 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810517 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810517 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588514810522 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588514810545 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588514810554 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.665 " "Worst-case setup slack is -3.665" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.665 -113.278 clk " " -3.665 -113.278 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.445 " "Worst-case hold slack is 0.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.445 0.000 clk " " 0.445 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810572 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810581 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -43.179 clk " " -1.631 -43.179 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588514810659 ""} +{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588514810663 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588514810680 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.854 " "Worst-case setup slack is -0.854" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.854 -24.594 clk " " -0.854 -24.594 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " " 0.215 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810696 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810704 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -35.380 clk " " -1.380 -35.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588514810765 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588514810798 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588514810799 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4545 " "Peak virtual memory: 4545 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514810889 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:06:50 2020 " "Processing ended: Sun May 03 22:06:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""} diff 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Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------------+---------------+-------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4597 MB ; 00:00:02 ; +; Fitter ; 00:00:07 ; 1.0 ; 4840 MB ; 00:00:06 ; +; Assembler ; 00:00:02 ; 1.0 ; 4552 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4545 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4518 MB ; 00:00:01 ; +; Total ; 00:00:13 ; -- ; -- ; 00:00:12 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder +quartus_fit --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder +quartus_asm --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder +quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder +quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder + + + diff --git a/Exp28_Decoder/output_files/YL_7SegmentDecoder.jdi b/Exp28_Decoder/output_files/YL_7SegmentDecoder.jdi new file mode 100644 index 0000000..e92dabd --- /dev/null +++ b/Exp28_Decoder/output_files/YL_7SegmentDecoder.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp28_Decoder/output_files/YL_7SegmentDecoder.map.rpt b/Exp28_Decoder/output_files/YL_7SegmentDecoder.map.rpt new file mode 100644 index 0000000..c792603 --- /dev/null +++ b/Exp28_Decoder/output_files/YL_7SegmentDecoder.map.rpt @@ -0,0 +1,276 @@ +Analysis & Synthesis report for YL_7SegmentDecoder +Sun May 03 22:06:37 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sun May 03 22:06:37 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_7SegmentDecoder ; +; Top-level Entity Name ; YL_7SegmentDecoder ; +; Family ; Cyclone II ; +; Total logic elements ; 71 ; +; Total combinational functions ; 71 ; +; Dedicated logic registers ; 34 ; +; Total registers ; 34 ; +; Total pins ; 17 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; YL_7SegmentDecoder ; YL_7SegmentDecoder ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+---------+ +; YL_dec_counter.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_dec_counter.tdf ; ; +; YL_7SegmentDecoder.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf ; ; +; YL_7SegmentDecoder.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.tdf ; ; +; YL_sec_cnt.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_sec_cnt.tdf ; ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 71 ; +; ; ; +; Total combinational functions ; 71 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 38 ; +; -- 3 input functions ; 4 ; +; -- <=2 input functions ; 29 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 47 ; +; -- arithmetic mode ; 24 ; +; ; ; +; Total registers ; 34 ; +; -- Dedicated logic registers ; 34 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 17 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; clk ; +; Maximum fan-out ; 34 ; +; Total fan-out ; 327 ; +; Average fan-out ; 2.68 ; ++---------------------------------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+ +; |YL_7SegmentDecoder ; 71 (0) ; 34 (0) ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; |YL_7SegmentDecoder ; work ; +; |7segment:inst_12| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_7SegmentDecoder|7segment:inst_12 ; work ; +; |7segment:inst_| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_7SegmentDecoder|7segment:inst_ ; work ; +; |dec_count:inst11| ; 11 (11) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_7SegmentDecoder|dec_count:inst11 ; work ; +; |dec_count:inst8| ; 9 (9) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_7SegmentDecoder|dec_count:inst8 ; work ; +; |sec_cnt:inst10| ; 35 (35) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_7SegmentDecoder|sec_cnt:inst10 ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 34 ; +; Number of registers using Synchronous Clear ; 25 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 22:06:35 2020 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf + Info (12023): Found entity 1: dec_count +Info (12021): Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.bdf + Info (12023): Found entity 1: YL_7SegmentDecoder +Info (12021): Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.tdf + Info (12023): Found entity 1: 7segment +Info (12021): Found 1 design units, including 1 entities, in source file yl_7segmentdecoder2.bdf + Info (12023): Found entity 1: YL_7SegmentDecoder2 +Info (12021): Found 1 design units, including 1 entities, in source file yl_sec_cnt.tdf + Info (12023): Found entity 1: sec_cnt +Info (12021): Found 1 design units, including 1 entities, in source file yl_cascade.bdf + Info (12023): Found entity 1: YL_Cascade +Info (12127): Elaborating entity "YL_7SegmentDecoder" for the top level hierarchy +Info (12128): Elaborating entity "7segment" for hierarchy "7segment:inst_" +Info (12128): Elaborating entity "dec_count" for hierarchy "dec_count:inst8" +Info (12128): Elaborating entity "sec_cnt" for hierarchy "sec_cnt:inst10" +Info (12128): Elaborating entity "dec_count" for hierarchy "dec_count:inst11" +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 88 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 3 input pins + Info (21059): Implemented 14 output pins + Info (21061): Implemented 71 logic cells +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4608 megabytes + Info: Processing ended: Sun May 03 22:06:37 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/Exp28_Decoder/output_files/YL_7SegmentDecoder.map.summary b/Exp28_Decoder/output_files/YL_7SegmentDecoder.map.summary new file mode 100644 index 0000000..91b3ec4 --- /dev/null +++ b/Exp28_Decoder/output_files/YL_7SegmentDecoder.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Sun May 03 22:06:37 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_7SegmentDecoder +Top-level Entity Name : YL_7SegmentDecoder +Family : Cyclone II +Total logic elements : 71 + Total combinational functions : 71 + Dedicated logic registers : 34 +Total registers : 34 +Total pins : 17 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/Exp28_Decoder/output_files/YL_7SegmentDecoder.pin b/Exp28_Decoder/output_files/YL_7SegmentDecoder.pin new file mode 100644 index 0000000..2c916f9 --- /dev/null +++ b/Exp28_Decoder/output_files/YL_7SegmentDecoder.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "YL_7SegmentDecoder" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +GND* : A11 : : : : 3 : +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +GND* : AA3 : : : : 8 : +GND* : AA4 : : : : 8 : +GND* : AA5 : : : : 8 : +GND* : AA6 : : : : 8 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +GND* : AA11 : : : : 8 : +GND* : AA12 : : : : 7 : +GND* : AA13 : : : : 7 : +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +GND* : AB3 : : : : 8 : +GND* : AB4 : : : : 8 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +GND* : AB12 : : : : 7 : +GND* : AB13 : : : : 7 : +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +GND* : B11 : : : : 3 : +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +GND* : B14 : : : : 4 : +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +GND* : B17 : : : : 4 : +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 2 : +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +GND* : C7 : : : : 3 : +GND : C8 : gnd : : : : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +GND* : C14 : : : : 4 : +GND : C15 : gnd : : : : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +GND* : C21 : : : : 5 : +GND* : C22 : : : : 5 : +GND* : D1 : : : : 2 : +GND* : D2 : : : : 2 : +GND* : D3 : : : : 2 : +GND* : D4 : : : : 2 : +GND* : D5 : : : : 2 : +GND* : D6 : : : : 2 : +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +GND* : D9 : : : : 3 : +GND : D10 : gnd : : : : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +GND* : D14 : : : : 4 : +GND* : D15 : : : : 4 : +GND* : D16 : : : : 4 : +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +GND* : D20 : : : : 5 : +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +OUTPUT_C3 : E1 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_G : E2 : output : 3.3-V LVTTL : : 2 : Y +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +GND* : E14 : : : : 4 : +GND* : E15 : : : : 4 : +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +OUTPUT_F : F1 : output : 3.3-V LVTTL : : 2 : Y +OUTPUT_E : F2 : output : 3.3-V LVTTL : : 2 : Y +GND* : F3 : : : : 2 : +GND* : F4 : : : : 2 : +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +GND* : F12 : : : : 4 : +GND* : F13 : : : : 4 : +GND* : F14 : : : : 4 : +GND* : F15 : : : : 4 : +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +OUTPUT_A1 : G3 : output : 3.3-V LVTTL : : 2 : N +GND : G4 : gnd : : : : +GND* : G5 : : : : 2 : +GND* : G6 : : : : 2 : +GND* : G7 : : : : 3 : +GND* : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +GND* : G15 : : : : 4 : +GND* : G16 : : : : 4 : +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +OUTPUT_D : H1 : output : 3.3-V LVTTL : : 2 : Y +OUTPUT_C : H2 : output : 3.3-V LVTTL : : 2 : Y +OUTPUT_F6 : H3 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_B2 : H4 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_G7 : H5 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_E5 : H6 : output : 3.3-V LVTTL : : 2 : N +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +GND* : H12 : : : : 4 : +GND* : H13 : : : : 4 : +GND* : H14 : : : : 4 : +GND* : H15 : : : : 4 : +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +OUTPUT_B : J1 : output : 3.3-V LVTTL : : 2 : Y +OUTPUT_A : J2 : output : 3.3-V LVTTL : : 2 : Y +NC : J3 : : : : : +GND* : J4 : : : : 2 : +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +GND* : J14 : : : : 4 : +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +clk : L1 : input : 3.3-V LVTTL : : 2 : Y +GND+ : L2 : : : : 2 : +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +OUTPUT_D4 : L8 : output : 3.3-V LVTTL : : 2 : N +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +ent : L21 : input : 3.3-V LVTTL : : 5 : Y +GND+ : L22 : : : : 5 : +GND+ : M1 : : : : 1 : +GND+ : M2 : : : : 1 : +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +clear : M22 : input : 3.3-V LVTTL : : 6 : Y +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +GND* : P5 : : : : 1 : +GND* : P6 : : : : 1 : +VCCIO1 : P7 : power : : 3.3V : 1 : +GND* : P8 : : : : 8 : +GND* : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +GND* : P18 : : : : 6 : +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +GND* : R1 : : : : 1 : +GND* : R2 : : : : 1 : +GND : R3 : gnd : : : : +NC : R4 : : : : : +GND* : R5 : : : : 1 : +GND* : R6 : : : : 1 : +GND* : R7 : : : : 1 : +GND* : R8 : : : : 1 : +GND* : R9 : : : : 8 : +GND* : R10 : : : : 8 : +GND* : R11 : : : : 8 : +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +GND* : T1 : : : : 1 : +GND* : T2 : : : : 1 : +GND* : T3 : : : : 1 : +VCCIO1 : T4 : power : : 3.3V : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 8 : +GND* : T8 : : : : 8 : +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +GND* : T12 : : : : 7 : +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +GND* : T15 : : : : 7 : +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +GND* : U8 : : : : 8 : +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND : V3 : gnd : : : : +GND* : V4 : : : : 1 : +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +GND* : V8 : : : : 8 : +GND* : V9 : : : : 8 : +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +VCCIO8 : W6 : power : : 3.3V : 8 : +GND* : W7 : : : : 8 : +GND* : W8 : : : : 8 : +GND* : W9 : : : : 8 : +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +GND* : Y1 : : : : 1 : +GND* : Y2 : : : : 1 : +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +GND* : Y5 : : : : 8 : +GND* : Y6 : : : : 8 : +GND* : Y7 : : : : 8 : +GND : Y8 : gnd : : : : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power : : 3.3V : 7 : +GND* : Y13 : : : : 7 : +GND* : Y14 : : : : 7 : +GND : Y15 : gnd : : : : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 6 : +GND* : Y19 : : : : 6 : +GND* : Y20 : : : : 6 : +GND* : Y21 : : : : 6 : +GND* : Y22 : : : : 6 : diff --git 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Current Strength: 24mA +// OUTPUT_B => Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C => Location: PIN_H2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D => Location: PIN_H1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_A1 => Location: PIN_G3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B2 => Location: PIN_H4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C3 => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D4 => Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E5 => Location: PIN_H6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F6 => Location: PIN_H3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G7 => Location: PIN_H5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// clear => Location: PIN_M22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// ent => Location: PIN_L21, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("YL_7SegmentDecoder_v.sdo"); +// synopsys translate_on + +wire \inst10|count[2]~27_combout ; +wire \inst10|count[5]~33_combout ; +wire \inst10|count[9]~41_combout ; +wire \inst10|count[16]~55_combout ; +wire \inst10|count[24]~72 ; +wire \inst10|count[25]~73_combout ; +wire \inst10|second~3_combout ; +wire \inst8|count[1]~2_combout ; +wire \inst8|op_1~0_combout ; +wire \inst8|op_1~1_combout ; +wire \inst_12|a~13_combout ; +wire \inst11|op_1~0_combout ; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \clear~combout ; +wire \inst10|count[0]~75_combout ; +wire \inst10|count[1]~26 ; +wire \inst10|count[2]~28 ; +wire \inst10|count[3]~30 ; +wire \inst10|count[4]~31_combout ; +wire \inst10|count[12]~47_combout ; +wire \inst10|second~4_combout ; +wire \inst10|count[7]~37_combout ; +wire \inst10|second~2_combout ; +wire \inst10|count[1]~25_combout ; +wire \inst10|count[3]~29_combout ; +wire \inst10|second~1_combout ; +wire \inst10|second~5_combout ; +wire \inst10|second~9_combout ; +wire \inst10|count[4]~32 ; +wire \inst10|count[5]~34 ; +wire \inst10|count[6]~35_combout ; +wire \inst10|count[6]~36 ; +wire \inst10|count[7]~38 ; +wire \inst10|count[8]~39_combout ; +wire \inst10|count[8]~40 ; +wire \inst10|count[9]~42 ; +wire \inst10|count[10]~43_combout ; +wire \inst10|count[10]~44 ; +wire \inst10|count[11]~45_combout ; +wire \inst10|count[11]~46 ; +wire \inst10|count[12]~48 ; +wire \inst10|count[13]~49_combout ; +wire \inst10|count[13]~50 ; +wire \inst10|count[14]~51_combout ; +wire \inst10|count[14]~52 ; +wire \inst10|count[15]~53_combout ; +wire \inst10|count[15]~54 ; +wire \inst10|count[16]~56 ; +wire \inst10|count[17]~57_combout ; +wire \inst10|count[17]~58 ; +wire \inst10|count[18]~59_combout ; +wire \inst10|count[18]~60 ; +wire \inst10|count[19]~61_combout ; +wire \inst10|second~6_combout ; +wire \inst10|count[19]~62 ; +wire \inst10|count[20]~64 ; +wire \inst10|count[21]~65_combout ; +wire \inst10|count[21]~66 ; +wire \inst10|count[22]~68 ; +wire \inst10|count[23]~69_combout ; +wire \inst10|count[23]~70 ; +wire \inst10|count[24]~71_combout ; +wire \inst10|count[20]~63_combout ; +wire \inst10|count[22]~67_combout ; +wire \inst10|second~7_combout ; +wire \inst10|second~8_combout ; +wire \inst8|count[1]~1_combout ; +wire \inst8|count[3]~6_combout ; +wire \inst8|count[1]~4_combout ; +wire \inst8|count[0]~0_combout ; +wire \inst_|a~13_combout ; +wire \inst8|count[1]~3_combout ; +wire \inst8|count[2]~5_combout ; +wire \inst_|a~12_combout ; +wire \inst_|b~3_combout ; +wire \inst_|c~1_combout ; +wire \inst_|d~0_combout ; +wire \inst_|e~0_combout ; +wire \inst_|f~0_combout ; +wire \inst_|g~0_combout ; +wire \ent~combout ; +wire \inst11|count[1]~1_combout ; +wire \inst11|count[1]~2_combout ; +wire \inst11|count[3]~8_combout ; +wire \inst11|_~0_combout ; +wire \inst11|count[0]~0_combout ; +wire \inst11|count[2]~7_combout ; +wire \inst11|count[1]~3_combout ; +wire \inst11|count[1]~4_combout ; +wire \inst11|count[1]~5_combout ; +wire \inst11|count[1]~6_combout ; +wire \inst_12|a~12_combout ; +wire \inst_12|b~3_combout ; +wire \inst_12|c~1_combout ; +wire \inst_12|d~0_combout ; +wire \inst_12|e~0_combout ; +wire \inst_12|f~0_combout ; +wire \inst_12|g~0_combout ; +wire [3:0] \inst8|count ; +wire [25:0] \inst10|count ; +wire [3:0] \inst11|count ; + + +// Location: LCFF_X3_Y21_N11 +cycloneii_lcell_ff \inst10|count[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[2]~27_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [2])); + +// Location: LCFF_X3_Y21_N17 +cycloneii_lcell_ff \inst10|count[5] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[5]~33_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [5])); + +// Location: LCFF_X3_Y21_N25 +cycloneii_lcell_ff \inst10|count[9] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[9]~41_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [9])); + +// Location: LCFF_X3_Y20_N7 +cycloneii_lcell_ff \inst10|count[16] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[16]~55_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [16])); + +// Location: LCFF_X3_Y20_N25 +cycloneii_lcell_ff \inst10|count[25] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[25]~73_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [25])); + +// Location: LCCOMB_X3_Y21_N10 +cycloneii_lcell_comb \inst10|count[2]~27 ( +// Equation(s): +// \inst10|count[2]~27_combout = (\inst10|count [2] & (!\inst10|count[1]~26 )) # (!\inst10|count [2] & ((\inst10|count[1]~26 ) # (GND))) +// \inst10|count[2]~28 = CARRY((!\inst10|count[1]~26 ) # (!\inst10|count [2])) + + .dataa(\inst10|count [2]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[1]~26 ), + .combout(\inst10|count[2]~27_combout ), + .cout(\inst10|count[2]~28 )); +// synopsys translate_off +defparam \inst10|count[2]~27 .lut_mask = 16'h5A5F; +defparam \inst10|count[2]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N16 +cycloneii_lcell_comb \inst10|count[5]~33 ( +// Equation(s): +// \inst10|count[5]~33_combout = (\inst10|count [5] & (\inst10|count[4]~32 $ (GND))) # (!\inst10|count [5] & (!\inst10|count[4]~32 & VCC)) +// \inst10|count[5]~34 = CARRY((\inst10|count [5] & !\inst10|count[4]~32 )) + + .dataa(\inst10|count [5]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[4]~32 ), + .combout(\inst10|count[5]~33_combout ), + .cout(\inst10|count[5]~34 )); +// synopsys translate_off +defparam \inst10|count[5]~33 .lut_mask = 16'hA50A; +defparam \inst10|count[5]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N24 +cycloneii_lcell_comb \inst10|count[9]~41 ( +// Equation(s): +// \inst10|count[9]~41_combout = (\inst10|count [9] & (\inst10|count[8]~40 $ (GND))) # (!\inst10|count [9] & (!\inst10|count[8]~40 & VCC)) +// \inst10|count[9]~42 = CARRY((\inst10|count [9] & !\inst10|count[8]~40 )) + + .dataa(\inst10|count [9]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[8]~40 ), + .combout(\inst10|count[9]~41_combout ), + .cout(\inst10|count[9]~42 )); +// synopsys translate_off +defparam \inst10|count[9]~41 .lut_mask = 16'hA50A; +defparam \inst10|count[9]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N6 +cycloneii_lcell_comb \inst10|count[16]~55 ( +// Equation(s): +// \inst10|count[16]~55_combout = (\inst10|count [16] & (!\inst10|count[15]~54 )) # (!\inst10|count [16] & ((\inst10|count[15]~54 ) # (GND))) +// \inst10|count[16]~56 = CARRY((!\inst10|count[15]~54 ) # (!\inst10|count [16])) + + .dataa(\inst10|count [16]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[15]~54 ), + .combout(\inst10|count[16]~55_combout ), + .cout(\inst10|count[16]~56 )); +// synopsys translate_off +defparam \inst10|count[16]~55 .lut_mask = 16'h5A5F; +defparam \inst10|count[16]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N22 +cycloneii_lcell_comb \inst10|count[24]~71 ( +// Equation(s): +// \inst10|count[24]~71_combout = (\inst10|count [24] & (!\inst10|count[23]~70 )) # (!\inst10|count [24] & ((\inst10|count[23]~70 ) # (GND))) +// \inst10|count[24]~72 = CARRY((!\inst10|count[23]~70 ) # (!\inst10|count [24])) + + .dataa(\inst10|count [24]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[23]~70 ), + .combout(\inst10|count[24]~71_combout ), + .cout(\inst10|count[24]~72 )); +// synopsys translate_off +defparam \inst10|count[24]~71 .lut_mask = 16'h5A5F; +defparam \inst10|count[24]~71 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N24 +cycloneii_lcell_comb \inst10|count[25]~73 ( +// Equation(s): +// \inst10|count[25]~73_combout = \inst10|count [25] $ (!\inst10|count[24]~72 ) + + .dataa(\inst10|count [25]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[24]~72 ), + .combout(\inst10|count[25]~73_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|count[25]~73 .lut_mask = 16'hA5A5; +defparam \inst10|count[25]~73 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N6 +cycloneii_lcell_comb \inst10|second~3 ( +// Equation(s): +// \inst10|second~3_combout = (!\inst10|count [9] & (!\inst10|count [10] & (!\inst10|count [8] & !\inst10|count [11]))) + + .dataa(\inst10|count [9]), + .datab(\inst10|count [10]), + .datac(\inst10|count [8]), + .datad(\inst10|count [11]), + .cin(gnd), + .combout(\inst10|second~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~3 .lut_mask = 16'h0001; +defparam \inst10|second~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N18 +cycloneii_lcell_comb \inst8|count[1]~2 ( +// Equation(s): +// \inst8|count[1]~2_combout = (!\clear~combout & \ent~combout ) + + .dataa(vcc), + .datab(\clear~combout ), + .datac(\ent~combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst8|count[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~2 .lut_mask = 16'h3030; +defparam \inst8|count[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N8 +cycloneii_lcell_comb \inst8|op_1~0 ( +// Equation(s): +// \inst8|op_1~0_combout = \inst8|count [2] $ (((\inst8|count [1] & \inst8|count [0]))) + + .dataa(\inst8|count [2]), + .datab(vcc), + .datac(\inst8|count [1]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst8|op_1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|op_1~0 .lut_mask = 16'h5AAA; +defparam \inst8|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N14 +cycloneii_lcell_comb \inst8|op_1~1 ( +// Equation(s): +// \inst8|op_1~1_combout = \inst8|count [3] $ (((\inst8|count [1] & (\inst8|count [2] & \inst8|count [0])))) + + .dataa(\inst8|count [1]), + .datab(\inst8|count [2]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst8|op_1~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|op_1~1 .lut_mask = 16'h78F0; +defparam \inst8|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N30 +cycloneii_lcell_comb \inst_12|a~13 ( +// Equation(s): +// \inst_12|a~13_combout = (\inst11|count [0] & \inst11|count [1]) + + .dataa(\inst11|count [0]), + .datab(vcc), + .datac(\inst11|count [1]), + .datad(vcc), + .cin(gnd), + .combout(\inst_12|a~13_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|a~13 .lut_mask = 16'hA0A0; +defparam \inst_12|a~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N4 +cycloneii_lcell_comb \inst11|op_1~0 ( +// Equation(s): +// \inst11|op_1~0_combout = \inst11|count [3] $ (((\inst11|count [1] & (\inst11|count [0] & \inst11|count [2])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst11|op_1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|op_1~0 .lut_mask = 16'h6CCC; +defparam \inst11|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_M22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clear~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clear~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clear)); +// synopsys translate_off +defparam \clear~I .input_async_reset = "none"; +defparam \clear~I .input_power_up = "low"; +defparam \clear~I .input_register_mode = "none"; +defparam \clear~I .input_sync_reset = "none"; +defparam \clear~I .oe_async_reset = "none"; +defparam \clear~I .oe_power_up = "low"; +defparam \clear~I .oe_register_mode = "none"; +defparam \clear~I .oe_sync_reset = "none"; +defparam \clear~I .operation_mode = "input"; +defparam \clear~I .output_async_reset = "none"; +defparam \clear~I .output_power_up = "low"; +defparam \clear~I .output_register_mode = "none"; +defparam \clear~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N4 +cycloneii_lcell_comb \inst10|count[0]~75 ( +// Equation(s): +// \inst10|count[0]~75_combout = !\inst10|count [0] + + .dataa(vcc), + .datab(vcc), + .datac(\inst10|count [0]), + .datad(vcc), + .cin(gnd), + .combout(\inst10|count[0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|count[0]~75 .lut_mask = 16'h0F0F; +defparam \inst10|count[0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N5 +cycloneii_lcell_ff \inst10|count[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[0]~75_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [0])); + +// Location: LCCOMB_X3_Y21_N8 +cycloneii_lcell_comb \inst10|count[1]~25 ( +// Equation(s): +// \inst10|count[1]~25_combout = (\inst10|count [1] & (\inst10|count [0] $ (VCC))) # (!\inst10|count [1] & (\inst10|count [0] & VCC)) +// \inst10|count[1]~26 = CARRY((\inst10|count [1] & \inst10|count [0])) + + .dataa(\inst10|count [1]), + .datab(\inst10|count [0]), + .datac(vcc), + .datad(vcc), + .cin(gnd), + .combout(\inst10|count[1]~25_combout ), + .cout(\inst10|count[1]~26 )); +// synopsys translate_off +defparam \inst10|count[1]~25 .lut_mask = 16'h6688; +defparam \inst10|count[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N12 +cycloneii_lcell_comb \inst10|count[3]~29 ( +// Equation(s): +// \inst10|count[3]~29_combout = (\inst10|count [3] & (\inst10|count[2]~28 $ (GND))) # (!\inst10|count [3] & (!\inst10|count[2]~28 & VCC)) +// \inst10|count[3]~30 = CARRY((\inst10|count [3] & !\inst10|count[2]~28 )) + + .dataa(\inst10|count [3]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[2]~28 ), + .combout(\inst10|count[3]~29_combout ), + .cout(\inst10|count[3]~30 )); +// synopsys translate_off +defparam \inst10|count[3]~29 .lut_mask = 16'hA50A; +defparam \inst10|count[3]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N14 +cycloneii_lcell_comb \inst10|count[4]~31 ( +// Equation(s): +// \inst10|count[4]~31_combout = (\inst10|count [4] & (!\inst10|count[3]~30 )) # (!\inst10|count [4] & ((\inst10|count[3]~30 ) # (GND))) +// \inst10|count[4]~32 = CARRY((!\inst10|count[3]~30 ) # (!\inst10|count [4])) + + .dataa(vcc), + .datab(\inst10|count [4]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[3]~30 ), + .combout(\inst10|count[4]~31_combout ), + .cout(\inst10|count[4]~32 )); +// synopsys translate_off +defparam \inst10|count[4]~31 .lut_mask = 16'h3C3F; +defparam \inst10|count[4]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N30 +cycloneii_lcell_comb \inst10|count[12]~47 ( +// Equation(s): +// \inst10|count[12]~47_combout = (\inst10|count [12] & (!\inst10|count[11]~46 )) # (!\inst10|count [12] & ((\inst10|count[11]~46 ) # (GND))) +// \inst10|count[12]~48 = CARRY((!\inst10|count[11]~46 ) # (!\inst10|count [12])) + + .dataa(\inst10|count [12]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[11]~46 ), + .combout(\inst10|count[12]~47_combout ), + .cout(\inst10|count[12]~48 )); +// synopsys translate_off +defparam \inst10|count[12]~47 .lut_mask = 16'h5A5F; +defparam \inst10|count[12]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N1 +cycloneii_lcell_ff \inst10|count[12] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\inst10|count[12]~47_combout ), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [12])); + +// Location: LCCOMB_X2_Y21_N0 +cycloneii_lcell_comb \inst10|second~4 ( +// Equation(s): +// \inst10|second~4_combout = (!\inst10|count [14] & (!\inst10|count [13] & (!\inst10|count [12] & !\inst10|count [15]))) + + .dataa(\inst10|count [14]), + .datab(\inst10|count [13]), + .datac(\inst10|count [12]), + .datad(\inst10|count [15]), + .cin(gnd), + .combout(\inst10|second~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~4 .lut_mask = 16'h0001; +defparam \inst10|second~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N20 +cycloneii_lcell_comb \inst10|count[7]~37 ( +// Equation(s): +// \inst10|count[7]~37_combout = (\inst10|count [7] & (\inst10|count[6]~36 $ (GND))) # (!\inst10|count [7] & (!\inst10|count[6]~36 & VCC)) +// \inst10|count[7]~38 = CARRY((\inst10|count [7] & !\inst10|count[6]~36 )) + + .dataa(\inst10|count [7]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[6]~36 ), + .combout(\inst10|count[7]~37_combout ), + .cout(\inst10|count[7]~38 )); +// synopsys translate_off +defparam \inst10|count[7]~37 .lut_mask = 16'hA50A; +defparam \inst10|count[7]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N21 +cycloneii_lcell_ff \inst10|count[7] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[7]~37_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [7])); + +// Location: LCCOMB_X3_Y21_N0 +cycloneii_lcell_comb \inst10|second~2 ( +// Equation(s): +// \inst10|second~2_combout = (!\inst10|count [5] & (!\inst10|count [4] & (!\inst10|count [7] & !\inst10|count [6]))) + + .dataa(\inst10|count [5]), + .datab(\inst10|count [4]), + .datac(\inst10|count [7]), + .datad(\inst10|count [6]), + .cin(gnd), + .combout(\inst10|second~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~2 .lut_mask = 16'h0001; +defparam \inst10|second~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N9 +cycloneii_lcell_ff \inst10|count[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[1]~25_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [1])); + +// Location: LCFF_X3_Y21_N13 +cycloneii_lcell_ff \inst10|count[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[3]~29_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [3])); + +// Location: LCCOMB_X3_Y21_N2 +cycloneii_lcell_comb \inst10|second~1 ( +// Equation(s): +// \inst10|second~1_combout = (\inst10|count [2] & (!\inst10|count [1] & (\inst10|count [0] & !\inst10|count [3]))) + + .dataa(\inst10|count [2]), + .datab(\inst10|count [1]), + .datac(\inst10|count [0]), + .datad(\inst10|count [3]), + .cin(gnd), + .combout(\inst10|second~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~1 .lut_mask = 16'h0020; +defparam \inst10|second~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N28 +cycloneii_lcell_comb \inst10|second~5 ( +// Equation(s): +// \inst10|second~5_combout = (\inst10|second~3_combout & (\inst10|second~4_combout & (\inst10|second~2_combout & \inst10|second~1_combout ))) + + .dataa(\inst10|second~3_combout ), + .datab(\inst10|second~4_combout ), + .datac(\inst10|second~2_combout ), + .datad(\inst10|second~1_combout ), + .cin(gnd), + .combout(\inst10|second~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~5 .lut_mask = 16'h8000; +defparam \inst10|second~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N10 +cycloneii_lcell_comb \inst10|second~9 ( +// Equation(s): +// \inst10|second~9_combout = (\inst10|second~5_combout & \inst10|second~8_combout ) + + .dataa(vcc), + .datab(\inst10|second~5_combout ), + .datac(vcc), + .datad(\inst10|second~8_combout ), + .cin(gnd), + .combout(\inst10|second~9_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~9 .lut_mask = 16'hCC00; +defparam \inst10|second~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N15 +cycloneii_lcell_ff \inst10|count[4] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[4]~31_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [4])); + +// Location: LCCOMB_X3_Y21_N18 +cycloneii_lcell_comb \inst10|count[6]~35 ( +// Equation(s): +// \inst10|count[6]~35_combout = (\inst10|count [6] & (!\inst10|count[5]~34 )) # (!\inst10|count [6] & ((\inst10|count[5]~34 ) # (GND))) +// \inst10|count[6]~36 = CARRY((!\inst10|count[5]~34 ) # (!\inst10|count [6])) + + .dataa(vcc), + .datab(\inst10|count [6]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[5]~34 ), + .combout(\inst10|count[6]~35_combout ), + .cout(\inst10|count[6]~36 )); +// synopsys translate_off +defparam \inst10|count[6]~35 .lut_mask = 16'h3C3F; +defparam \inst10|count[6]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N19 +cycloneii_lcell_ff \inst10|count[6] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[6]~35_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [6])); + +// Location: LCCOMB_X3_Y21_N22 +cycloneii_lcell_comb \inst10|count[8]~39 ( +// Equation(s): +// \inst10|count[8]~39_combout = (\inst10|count [8] & (!\inst10|count[7]~38 )) # (!\inst10|count [8] & ((\inst10|count[7]~38 ) # (GND))) +// \inst10|count[8]~40 = CARRY((!\inst10|count[7]~38 ) # (!\inst10|count [8])) + + .dataa(vcc), + .datab(\inst10|count [8]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[7]~38 ), + .combout(\inst10|count[8]~39_combout ), + .cout(\inst10|count[8]~40 )); +// synopsys translate_off +defparam \inst10|count[8]~39 .lut_mask = 16'h3C3F; +defparam \inst10|count[8]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N23 +cycloneii_lcell_ff \inst10|count[8] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[8]~39_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [8])); + +// Location: LCCOMB_X3_Y21_N26 +cycloneii_lcell_comb \inst10|count[10]~43 ( +// Equation(s): +// \inst10|count[10]~43_combout = (\inst10|count [10] & (!\inst10|count[9]~42 )) # (!\inst10|count [10] & ((\inst10|count[9]~42 ) # (GND))) +// \inst10|count[10]~44 = CARRY((!\inst10|count[9]~42 ) # (!\inst10|count [10])) + + .dataa(vcc), + .datab(\inst10|count [10]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[9]~42 ), + .combout(\inst10|count[10]~43_combout ), + .cout(\inst10|count[10]~44 )); +// synopsys translate_off +defparam \inst10|count[10]~43 .lut_mask = 16'h3C3F; +defparam \inst10|count[10]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N27 +cycloneii_lcell_ff \inst10|count[10] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[10]~43_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [10])); + +// Location: LCCOMB_X3_Y21_N28 +cycloneii_lcell_comb \inst10|count[11]~45 ( +// Equation(s): +// \inst10|count[11]~45_combout = (\inst10|count [11] & (\inst10|count[10]~44 $ (GND))) # (!\inst10|count [11] & (!\inst10|count[10]~44 & VCC)) +// \inst10|count[11]~46 = CARRY((\inst10|count [11] & !\inst10|count[10]~44 )) + + .dataa(vcc), + .datab(\inst10|count [11]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[10]~44 ), + .combout(\inst10|count[11]~45_combout ), + .cout(\inst10|count[11]~46 )); +// synopsys translate_off +defparam \inst10|count[11]~45 .lut_mask = 16'hC30C; +defparam \inst10|count[11]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N29 +cycloneii_lcell_ff \inst10|count[11] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[11]~45_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [11])); + +// Location: LCCOMB_X3_Y20_N0 +cycloneii_lcell_comb \inst10|count[13]~49 ( +// Equation(s): +// \inst10|count[13]~49_combout = (\inst10|count [13] & (\inst10|count[12]~48 $ (GND))) # (!\inst10|count [13] & (!\inst10|count[12]~48 & VCC)) +// \inst10|count[13]~50 = CARRY((\inst10|count [13] & !\inst10|count[12]~48 )) + + .dataa(vcc), + .datab(\inst10|count [13]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[12]~48 ), + .combout(\inst10|count[13]~49_combout ), + .cout(\inst10|count[13]~50 )); +// synopsys translate_off +defparam \inst10|count[13]~49 .lut_mask = 16'hC30C; +defparam \inst10|count[13]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N1 +cycloneii_lcell_ff \inst10|count[13] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[13]~49_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [13])); + +// Location: LCCOMB_X3_Y20_N2 +cycloneii_lcell_comb \inst10|count[14]~51 ( +// Equation(s): +// \inst10|count[14]~51_combout = (\inst10|count [14] & (!\inst10|count[13]~50 )) # (!\inst10|count [14] & ((\inst10|count[13]~50 ) # (GND))) +// \inst10|count[14]~52 = CARRY((!\inst10|count[13]~50 ) # (!\inst10|count [14])) + + .dataa(vcc), + .datab(\inst10|count [14]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[13]~50 ), + .combout(\inst10|count[14]~51_combout ), + .cout(\inst10|count[14]~52 )); +// synopsys translate_off +defparam \inst10|count[14]~51 .lut_mask = 16'h3C3F; +defparam \inst10|count[14]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N11 +cycloneii_lcell_ff \inst10|count[14] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\inst10|count[14]~51_combout ), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [14])); + +// Location: LCCOMB_X3_Y20_N4 +cycloneii_lcell_comb \inst10|count[15]~53 ( +// Equation(s): +// \inst10|count[15]~53_combout = (\inst10|count [15] & (\inst10|count[14]~52 $ (GND))) # (!\inst10|count [15] & (!\inst10|count[14]~52 & VCC)) +// \inst10|count[15]~54 = CARRY((\inst10|count [15] & !\inst10|count[14]~52 )) + + .dataa(vcc), + .datab(\inst10|count [15]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[14]~52 ), + .combout(\inst10|count[15]~53_combout ), + .cout(\inst10|count[15]~54 )); +// synopsys translate_off +defparam \inst10|count[15]~53 .lut_mask = 16'hC30C; +defparam \inst10|count[15]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N5 +cycloneii_lcell_ff \inst10|count[15] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[15]~53_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [15])); + +// Location: LCCOMB_X3_Y20_N8 +cycloneii_lcell_comb \inst10|count[17]~57 ( +// Equation(s): +// \inst10|count[17]~57_combout = (\inst10|count [17] & (\inst10|count[16]~56 $ (GND))) # (!\inst10|count [17] & (!\inst10|count[16]~56 & VCC)) +// \inst10|count[17]~58 = CARRY((\inst10|count [17] & !\inst10|count[16]~56 )) + + .dataa(\inst10|count [17]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[16]~56 ), + .combout(\inst10|count[17]~57_combout ), + .cout(\inst10|count[17]~58 )); +// synopsys translate_off +defparam \inst10|count[17]~57 .lut_mask = 16'hA50A; +defparam \inst10|count[17]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N9 +cycloneii_lcell_ff \inst10|count[17] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[17]~57_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [17])); + +// Location: LCCOMB_X3_Y20_N10 +cycloneii_lcell_comb \inst10|count[18]~59 ( +// Equation(s): +// \inst10|count[18]~59_combout = (\inst10|count [18] & (!\inst10|count[17]~58 )) # (!\inst10|count [18] & ((\inst10|count[17]~58 ) # (GND))) +// \inst10|count[18]~60 = CARRY((!\inst10|count[17]~58 ) # (!\inst10|count [18])) + + .dataa(\inst10|count [18]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[17]~58 ), + .combout(\inst10|count[18]~59_combout ), + .cout(\inst10|count[18]~60 )); +// synopsys translate_off +defparam \inst10|count[18]~59 .lut_mask = 16'h5A5F; +defparam \inst10|count[18]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N11 +cycloneii_lcell_ff \inst10|count[18] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[18]~59_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [18])); + +// Location: LCCOMB_X3_Y20_N12 +cycloneii_lcell_comb \inst10|count[19]~61 ( +// Equation(s): +// \inst10|count[19]~61_combout = (\inst10|count [19] & (\inst10|count[18]~60 $ (GND))) # (!\inst10|count [19] & (!\inst10|count[18]~60 & VCC)) +// \inst10|count[19]~62 = CARRY((\inst10|count [19] & !\inst10|count[18]~60 )) + + .dataa(\inst10|count [19]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[18]~60 ), + .combout(\inst10|count[19]~61_combout ), + .cout(\inst10|count[19]~62 )); +// synopsys translate_off +defparam \inst10|count[19]~61 .lut_mask = 16'hA50A; +defparam \inst10|count[19]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N13 +cycloneii_lcell_ff \inst10|count[19] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[19]~61_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [19])); + +// Location: LCCOMB_X3_Y20_N30 +cycloneii_lcell_comb \inst10|second~6 ( +// Equation(s): +// \inst10|second~6_combout = (!\inst10|count [16] & (!\inst10|count [17] & (!\inst10|count [18] & !\inst10|count [19]))) + + .dataa(\inst10|count [16]), + .datab(\inst10|count [17]), + .datac(\inst10|count [18]), + .datad(\inst10|count [19]), + .cin(gnd), + .combout(\inst10|second~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~6 .lut_mask = 16'h0001; +defparam \inst10|second~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N14 +cycloneii_lcell_comb \inst10|count[20]~63 ( +// Equation(s): +// \inst10|count[20]~63_combout = (\inst10|count [20] & (!\inst10|count[19]~62 )) # (!\inst10|count [20] & ((\inst10|count[19]~62 ) # (GND))) +// \inst10|count[20]~64 = CARRY((!\inst10|count[19]~62 ) # (!\inst10|count [20])) + + .dataa(\inst10|count [20]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[19]~62 ), + .combout(\inst10|count[20]~63_combout ), + .cout(\inst10|count[20]~64 )); +// synopsys translate_off +defparam \inst10|count[20]~63 .lut_mask = 16'h5A5F; +defparam \inst10|count[20]~63 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N16 +cycloneii_lcell_comb \inst10|count[21]~65 ( +// Equation(s): +// \inst10|count[21]~65_combout = (\inst10|count [21] & (\inst10|count[20]~64 $ (GND))) # (!\inst10|count [21] & (!\inst10|count[20]~64 & VCC)) +// \inst10|count[21]~66 = CARRY((\inst10|count [21] & !\inst10|count[20]~64 )) + + .dataa(vcc), + .datab(\inst10|count [21]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[20]~64 ), + .combout(\inst10|count[21]~65_combout ), + .cout(\inst10|count[21]~66 )); +// synopsys translate_off +defparam \inst10|count[21]~65 .lut_mask = 16'hC30C; +defparam \inst10|count[21]~65 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N17 +cycloneii_lcell_ff \inst10|count[21] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[21]~65_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [21])); + +// Location: LCCOMB_X3_Y20_N18 +cycloneii_lcell_comb \inst10|count[22]~67 ( +// Equation(s): +// \inst10|count[22]~67_combout = (\inst10|count [22] & (!\inst10|count[21]~66 )) # (!\inst10|count [22] & ((\inst10|count[21]~66 ) # (GND))) +// \inst10|count[22]~68 = CARRY((!\inst10|count[21]~66 ) # (!\inst10|count [22])) + + .dataa(\inst10|count [22]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[21]~66 ), + .combout(\inst10|count[22]~67_combout ), + .cout(\inst10|count[22]~68 )); +// synopsys translate_off +defparam \inst10|count[22]~67 .lut_mask = 16'h5A5F; +defparam \inst10|count[22]~67 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N20 +cycloneii_lcell_comb \inst10|count[23]~69 ( +// Equation(s): +// \inst10|count[23]~69_combout = (\inst10|count [23] & (\inst10|count[22]~68 $ (GND))) # (!\inst10|count [23] & (!\inst10|count[22]~68 & VCC)) +// \inst10|count[23]~70 = CARRY((\inst10|count [23] & !\inst10|count[22]~68 )) + + .dataa(vcc), + .datab(\inst10|count [23]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[22]~68 ), + .combout(\inst10|count[23]~69_combout ), + .cout(\inst10|count[23]~70 )); +// synopsys translate_off +defparam \inst10|count[23]~69 .lut_mask = 16'hC30C; +defparam \inst10|count[23]~69 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N21 +cycloneii_lcell_ff \inst10|count[23] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[23]~69_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [23])); + +// Location: LCFF_X3_Y20_N23 +cycloneii_lcell_ff \inst10|count[24] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[24]~71_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [24])); + +// Location: LCFF_X3_Y20_N15 +cycloneii_lcell_ff \inst10|count[20] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[20]~63_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [20])); + +// Location: LCFF_X3_Y20_N19 +cycloneii_lcell_ff \inst10|count[22] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[22]~67_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [22])); + +// Location: LCCOMB_X3_Y20_N28 +cycloneii_lcell_comb \inst10|second~7 ( +// Equation(s): +// \inst10|second~7_combout = (!\inst10|count [23] & (!\inst10|count [20] & (!\inst10|count [21] & !\inst10|count [22]))) + + .dataa(\inst10|count [23]), + .datab(\inst10|count [20]), + .datac(\inst10|count [21]), + .datad(\inst10|count [22]), + .cin(gnd), + .combout(\inst10|second~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~7 .lut_mask = 16'h0001; +defparam \inst10|second~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N26 +cycloneii_lcell_comb \inst10|second~8 ( +// Equation(s): +// \inst10|second~8_combout = (!\inst10|count [25] & (\inst10|second~6_combout & (!\inst10|count [24] & \inst10|second~7_combout ))) + + .dataa(\inst10|count [25]), + .datab(\inst10|second~6_combout ), + .datac(\inst10|count [24]), + .datad(\inst10|second~7_combout ), + .cin(gnd), + .combout(\inst10|second~8_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~8 .lut_mask = 16'h0400; +defparam \inst10|second~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N2 +cycloneii_lcell_comb \inst8|count[1]~1 ( +// Equation(s): +// \inst8|count[1]~1_combout = (!\clear~combout & (((!\inst10|second~5_combout ) # (!\inst10|second~8_combout )) # (!\ent~combout ))) + + .dataa(\ent~combout ), + .datab(\clear~combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst10|second~5_combout ), + .cin(gnd), + .combout(\inst8|count[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~1 .lut_mask = 16'h1333; +defparam \inst8|count[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N14 +cycloneii_lcell_comb \inst8|count[3]~6 ( +// Equation(s): +// \inst8|count[3]~6_combout = (\inst8|op_1~1_combout & ((\inst8|count[1]~3_combout ) # ((\inst8|count [3] & \inst8|count[1]~1_combout )))) # (!\inst8|op_1~1_combout & (((\inst8|count [3] & \inst8|count[1]~1_combout )))) + + .dataa(\inst8|op_1~1_combout ), + .datab(\inst8|count[1]~3_combout ), + .datac(\inst8|count [3]), + .datad(\inst8|count[1]~1_combout ), + .cin(gnd), + .combout(\inst8|count[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[3]~6 .lut_mask = 16'hF888; +defparam \inst8|count[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N15 +cycloneii_lcell_ff \inst8|count[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[3]~6_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [3])); + +// Location: LCCOMB_X2_Y21_N6 +cycloneii_lcell_comb \inst8|count[1]~4 ( +// Equation(s): +// \inst8|count[1]~4_combout = (\inst8|count [1] & ((\inst8|count[1]~1_combout ) # ((!\inst8|count [0] & \inst8|count[1]~3_combout )))) # (!\inst8|count [1] & (\inst8|count [0] & (\inst8|count[1]~3_combout ))) + + .dataa(\inst8|count [0]), + .datab(\inst8|count[1]~3_combout ), + .datac(\inst8|count [1]), + .datad(\inst8|count[1]~1_combout ), + .cin(gnd), + .combout(\inst8|count[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~4 .lut_mask = 16'hF848; +defparam \inst8|count[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N7 +cycloneii_lcell_ff \inst8|count[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[1]~4_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [1])); + +// Location: LCCOMB_X2_Y21_N24 +cycloneii_lcell_comb \inst8|count[0]~0 ( +// Equation(s): +// \inst8|count[0]~0_combout = (!\clear~combout & (\inst8|count [0] $ (((\ent~combout & \inst10|second~9_combout ))))) + + .dataa(\ent~combout ), + .datab(\clear~combout ), + .datac(\inst8|count [0]), + .datad(\inst10|second~9_combout ), + .cin(gnd), + .combout(\inst8|count[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[0]~0 .lut_mask = 16'h1230; +defparam \inst8|count[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N25 +cycloneii_lcell_ff \inst8|count[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[0]~0_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [0])); + +// Location: LCCOMB_X1_Y21_N12 +cycloneii_lcell_comb \inst_|a~13 ( +// Equation(s): +// \inst_|a~13_combout = (!\inst8|count [2] & (\inst8|count [3] & (\inst8|count [1] & \inst8|count [0]))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [3]), + .datac(\inst8|count [1]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|a~13_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|a~13 .lut_mask = 16'h4000; +defparam \inst_|a~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N8 +cycloneii_lcell_comb \inst8|count[1]~3 ( +// Equation(s): +// \inst8|count[1]~3_combout = (\inst8|count[1]~2_combout & (!\inst_|a~13_combout & (\inst10|second~8_combout & \inst10|second~5_combout ))) + + .dataa(\inst8|count[1]~2_combout ), + .datab(\inst_|a~13_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst10|second~5_combout ), + .cin(gnd), + .combout(\inst8|count[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~3 .lut_mask = 16'h2000; +defparam \inst8|count[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N4 +cycloneii_lcell_comb \inst8|count[2]~5 ( +// Equation(s): +// \inst8|count[2]~5_combout = (\inst8|op_1~0_combout & ((\inst8|count[1]~3_combout ) # ((\inst8|count [2] & \inst8|count[1]~1_combout )))) # (!\inst8|op_1~0_combout & (((\inst8|count [2] & \inst8|count[1]~1_combout )))) + + .dataa(\inst8|op_1~0_combout ), + .datab(\inst8|count[1]~3_combout ), + .datac(\inst8|count [2]), + .datad(\inst8|count[1]~1_combout ), + .cin(gnd), + .combout(\inst8|count[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[2]~5 .lut_mask = 16'hF888; +defparam \inst8|count[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N5 +cycloneii_lcell_ff \inst8|count[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[2]~5_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [2])); + +// Location: LCCOMB_X1_Y20_N28 +cycloneii_lcell_comb \inst_|a~12 ( +// Equation(s): +// \inst_|a~12_combout = (\inst8|count [2] & (!\inst8|count [1] & (\inst8|count [3] $ (!\inst8|count [0])))) # (!\inst8|count [2] & (\inst8|count [0] & (\inst8|count [1] $ (!\inst8|count [3])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|a~12 .lut_mask = 16'h6102; +defparam \inst_|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N22 +cycloneii_lcell_comb \inst_|b~3 ( +// Equation(s): +// \inst_|b~3_combout = (\inst8|count [1] & ((\inst8|count [0] & ((\inst8|count [3]))) # (!\inst8|count [0] & (\inst8|count [2])))) # (!\inst8|count [1] & (\inst8|count [2] & (\inst8|count [3] $ (\inst8|count [0])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|b~3 .lut_mask = 16'hC2A8; +defparam \inst_|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N16 +cycloneii_lcell_comb \inst_|c~1 ( +// Equation(s): +// \inst_|c~1_combout = (\inst8|count [2] & (\inst8|count [3] & ((\inst8|count [1]) # (!\inst8|count [0])))) # (!\inst8|count [2] & (\inst8|count [1] & (!\inst8|count [3] & !\inst8|count [0]))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|c~1 .lut_mask = 16'h80A4; +defparam \inst_|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N26 +cycloneii_lcell_comb \inst_|d~0 ( +// Equation(s): +// \inst_|d~0_combout = (\inst8|count [1] & ((\inst8|count [2] & ((\inst8|count [0]))) # (!\inst8|count [2] & (\inst8|count [3] & !\inst8|count [0])))) # (!\inst8|count [1] & (!\inst8|count [3] & (\inst8|count [2] $ (\inst8|count [0])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|d~0 .lut_mask = 16'h8942; +defparam \inst_|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N20 +cycloneii_lcell_comb \inst_|e~0 ( +// Equation(s): +// \inst_|e~0_combout = (\inst8|count [1] & (((!\inst8|count [3] & \inst8|count [0])))) # (!\inst8|count [1] & ((\inst8|count [2] & (!\inst8|count [3])) # (!\inst8|count [2] & ((\inst8|count [0]))))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|e~0 .lut_mask = 16'h1F02; +defparam \inst_|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N10 +cycloneii_lcell_comb \inst_|f~0 ( +// Equation(s): +// \inst_|f~0_combout = (\inst8|count [2] & (\inst8|count [0] & (\inst8|count [1] $ (\inst8|count [3])))) # (!\inst8|count [2] & (!\inst8|count [3] & ((\inst8|count [1]) # (\inst8|count [0])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|f~0 .lut_mask = 16'h2D04; +defparam \inst_|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N12 +cycloneii_lcell_comb \inst_|g~0 ( +// Equation(s): +// \inst_|g~0_combout = (\inst8|count [0] & ((\inst8|count [3]) # (\inst8|count [2] $ (\inst8|count [1])))) # (!\inst8|count [0] & ((\inst8|count [1]) # (\inst8|count [2] $ (\inst8|count [3])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|g~0 .lut_mask = 16'hF6DE; +defparam \inst_|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_L21, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \ent~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\ent~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(ent)); +// synopsys translate_off +defparam \ent~I .input_async_reset = "none"; +defparam \ent~I .input_power_up = "low"; +defparam \ent~I .input_register_mode = "none"; +defparam \ent~I .input_sync_reset = "none"; +defparam \ent~I .oe_async_reset = "none"; +defparam \ent~I .oe_power_up = "low"; +defparam \ent~I .oe_register_mode = "none"; +defparam \ent~I .oe_sync_reset = "none"; +defparam \ent~I .operation_mode = "input"; +defparam \ent~I .output_async_reset = "none"; +defparam \ent~I .output_power_up = "low"; +defparam \ent~I .output_register_mode = "none"; +defparam \ent~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N24 +cycloneii_lcell_comb \inst11|count[1]~1 ( +// Equation(s): +// \inst11|count[1]~1_combout = (!\inst_|a~13_combout ) # (!\ent~combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\ent~combout ), + .datad(\inst_|a~13_combout ), + .cin(gnd), + .combout(\inst11|count[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~1 .lut_mask = 16'h0FFF; +defparam \inst11|count[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N12 +cycloneii_lcell_comb \inst11|count[1]~2 ( +// Equation(s): +// \inst11|count[1]~2_combout = (!\clear~combout & (((\inst11|count[1]~1_combout ) # (!\inst10|second~8_combout )) # (!\inst10|second~5_combout ))) + + .dataa(\clear~combout ), + .datab(\inst10|second~5_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst11|count[1]~1_combout ), + .cin(gnd), + .combout(\inst11|count[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~2 .lut_mask = 16'h5515; +defparam \inst11|count[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N18 +cycloneii_lcell_comb \inst11|count[3]~8 ( +// Equation(s): +// \inst11|count[3]~8_combout = (\inst11|op_1~0_combout & ((\inst11|count[1]~5_combout ) # ((\inst11|count [3] & \inst11|count[1]~2_combout )))) # (!\inst11|op_1~0_combout & (((\inst11|count [3] & \inst11|count[1]~2_combout )))) + + .dataa(\inst11|op_1~0_combout ), + .datab(\inst11|count[1]~5_combout ), + .datac(\inst11|count [3]), + .datad(\inst11|count[1]~2_combout ), + .cin(gnd), + .combout(\inst11|count[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[3]~8 .lut_mask = 16'hF888; +defparam \inst11|count[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N19 +cycloneii_lcell_ff \inst11|count[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[3]~8_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [3])); + +// Location: LCCOMB_X2_Y21_N30 +cycloneii_lcell_comb \inst11|_~0 ( +// Equation(s): +// \inst11|_~0_combout = (\ent~combout & (\inst_|a~13_combout & (\inst10|second~8_combout & \inst10|second~5_combout ))) + + .dataa(\ent~combout ), + .datab(\inst_|a~13_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst10|second~5_combout ), + .cin(gnd), + .combout(\inst11|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|_~0 .lut_mask = 16'h8000; +defparam \inst11|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N16 +cycloneii_lcell_comb \inst11|count[0]~0 ( +// Equation(s): +// \inst11|count[0]~0_combout = (!\clear~combout & (\inst11|count [0] $ (\inst11|_~0_combout ))) + + .dataa(vcc), + .datab(\clear~combout ), + .datac(\inst11|count [0]), + .datad(\inst11|_~0_combout ), + .cin(gnd), + .combout(\inst11|count[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[0]~0 .lut_mask = 16'h0330; +defparam \inst11|count[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N17 +cycloneii_lcell_ff \inst11|count[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[0]~0_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [0])); + +// Location: LCCOMB_X2_Y21_N20 +cycloneii_lcell_comb \inst11|count[2]~7 ( +// Equation(s): +// \inst11|count[2]~7_combout = (\inst11|count [2] & ((\inst11|count[1]~2_combout ) # ((!\inst_12|a~13_combout & \inst11|count[1]~5_combout )))) # (!\inst11|count [2] & (\inst_12|a~13_combout & (\inst11|count[1]~5_combout ))) + + .dataa(\inst_12|a~13_combout ), + .datab(\inst11|count[1]~5_combout ), + .datac(\inst11|count [2]), + .datad(\inst11|count[1]~2_combout ), + .cin(gnd), + .combout(\inst11|count[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[2]~7 .lut_mask = 16'hF848; +defparam \inst11|count[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N21 +cycloneii_lcell_ff \inst11|count[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[2]~7_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [2])); + +// Location: LCCOMB_X1_Y21_N2 +cycloneii_lcell_comb \inst11|count[1]~3 ( +// Equation(s): +// \inst11|count[1]~3_combout = (((\inst11|count [2]) # (!\inst11|count [0])) # (!\inst11|count [3])) # (!\inst11|count [1]) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst11|count[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~3 .lut_mask = 16'hFF7F; +defparam \inst11|count[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N16 +cycloneii_lcell_comb \inst11|count[1]~4 ( +// Equation(s): +// \inst11|count[1]~4_combout = (!\clear~combout & (\ent~combout & \inst11|count[1]~3_combout )) + + .dataa(vcc), + .datab(\clear~combout ), + .datac(\ent~combout ), + .datad(\inst11|count[1]~3_combout ), + .cin(gnd), + .combout(\inst11|count[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~4 .lut_mask = 16'h3000; +defparam \inst11|count[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N22 +cycloneii_lcell_comb \inst11|count[1]~5 ( +// Equation(s): +// \inst11|count[1]~5_combout = (\inst10|second~5_combout & (\inst_|a~13_combout & (\inst10|second~8_combout & \inst11|count[1]~4_combout ))) + + .dataa(\inst10|second~5_combout ), + .datab(\inst_|a~13_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst11|count[1]~4_combout ), + .cin(gnd), + .combout(\inst11|count[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~5 .lut_mask = 16'h8000; +defparam \inst11|count[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N26 +cycloneii_lcell_comb \inst11|count[1]~6 ( +// Equation(s): +// \inst11|count[1]~6_combout = (\inst11|count [1] & ((\inst11|count[1]~2_combout ) # ((!\inst11|count [0] & \inst11|count[1]~5_combout )))) # (!\inst11|count [1] & (\inst11|count [0] & (\inst11|count[1]~5_combout ))) + + .dataa(\inst11|count [0]), + .datab(\inst11|count[1]~5_combout ), + .datac(\inst11|count [1]), + .datad(\inst11|count[1]~2_combout ), + .cin(gnd), + .combout(\inst11|count[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~6 .lut_mask = 16'hF848; +defparam \inst11|count[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N27 +cycloneii_lcell_ff \inst11|count[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[1]~6_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [1])); + +// Location: LCCOMB_X1_Y21_N20 +cycloneii_lcell_comb \inst_12|a~12 ( +// Equation(s): +// \inst_12|a~12_combout = (\inst11|count [3] & (\inst11|count [0] & (\inst11|count [1] $ (\inst11|count [2])))) # (!\inst11|count [3] & (!\inst11|count [1] & (\inst11|count [0] $ (\inst11|count [2])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|a~12 .lut_mask = 16'h4190; +defparam \inst_12|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N10 +cycloneii_lcell_comb \inst_12|b~3 ( +// Equation(s): +// \inst_12|b~3_combout = (\inst11|count [1] & ((\inst11|count [0] & (\inst11|count [3])) # (!\inst11|count [0] & ((\inst11|count [2]))))) # (!\inst11|count [1] & (\inst11|count [2] & (\inst11|count [3] $ (\inst11|count [0])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|b~3 .lut_mask = 16'h9E80; +defparam \inst_12|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y19_N0 +cycloneii_lcell_comb \inst_12|c~1 ( +// Equation(s): +// \inst_12|c~1_combout = (\inst11|count [3] & (\inst11|count [2] & ((\inst11|count [1]) # (!\inst11|count [0])))) # (!\inst11|count [3] & (!\inst11|count [0] & (!\inst11|count [2] & \inst11|count [1]))) + + .dataa(\inst11|count [3]), + .datab(\inst11|count [0]), + .datac(\inst11|count [2]), + .datad(\inst11|count [1]), + .cin(gnd), + .combout(\inst_12|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|c~1 .lut_mask = 16'hA120; +defparam \inst_12|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y19_N26 +cycloneii_lcell_comb \inst_12|d~0 ( +// Equation(s): +// \inst_12|d~0_combout = (\inst11|count [1] & ((\inst11|count [0] & ((\inst11|count [2]))) # (!\inst11|count [0] & (\inst11|count [3] & !\inst11|count [2])))) # (!\inst11|count [1] & (!\inst11|count [3] & (\inst11|count [0] $ (\inst11|count [2])))) + + .dataa(\inst11|count [3]), + .datab(\inst11|count [0]), + .datac(\inst11|count [2]), + .datad(\inst11|count [1]), + .cin(gnd), + .combout(\inst_12|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|d~0 .lut_mask = 16'hC214; +defparam \inst_12|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N0 +cycloneii_lcell_comb \inst_12|e~0 ( +// Equation(s): +// \inst_12|e~0_combout = (\inst11|count [1] & (!\inst11|count [3] & (\inst11|count [0]))) # (!\inst11|count [1] & ((\inst11|count [2] & (!\inst11|count [3])) # (!\inst11|count [2] & ((\inst11|count [0]))))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|e~0 .lut_mask = 16'h3170; +defparam \inst_12|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y19_N20 +cycloneii_lcell_comb \inst_12|f~0 ( +// Equation(s): +// \inst_12|f~0_combout = (\inst11|count [0] & (\inst11|count [3] $ (((\inst11|count [1]) # (!\inst11|count [2]))))) # (!\inst11|count [0] & (!\inst11|count [3] & (!\inst11|count [2] & \inst11|count [1]))) + + .dataa(\inst11|count [3]), + .datab(\inst11|count [0]), + .datac(\inst11|count [2]), + .datad(\inst11|count [1]), + .cin(gnd), + .combout(\inst_12|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|f~0 .lut_mask = 16'h4584; +defparam \inst_12|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N26 +cycloneii_lcell_comb \inst_12|g~0 ( +// Equation(s): +// \inst_12|g~0_combout = (\inst11|count [0] & ((\inst11|count [3]) # (\inst11|count [1] $ (\inst11|count [2])))) # (!\inst11|count [0] & ((\inst11|count [1]) # (\inst11|count [3] $ (\inst11|count [2])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|g~0 .lut_mask = 16'hDBEE; +defparam \inst_12|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A~I ( + .datain(\inst_|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A)); +// synopsys translate_off +defparam \OUTPUT_A~I .input_async_reset = "none"; +defparam \OUTPUT_A~I .input_power_up = "low"; +defparam \OUTPUT_A~I .input_register_mode = "none"; +defparam \OUTPUT_A~I .input_sync_reset = "none"; +defparam \OUTPUT_A~I .oe_async_reset = "none"; +defparam \OUTPUT_A~I .oe_power_up = "low"; +defparam \OUTPUT_A~I .oe_register_mode = "none"; +defparam \OUTPUT_A~I .oe_sync_reset = "none"; +defparam \OUTPUT_A~I .operation_mode = "output"; +defparam \OUTPUT_A~I .output_async_reset = "none"; +defparam \OUTPUT_A~I .output_power_up = "low"; +defparam \OUTPUT_A~I .output_register_mode = "none"; +defparam \OUTPUT_A~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B~I ( + .datain(\inst_|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B)); +// synopsys translate_off +defparam \OUTPUT_B~I .input_async_reset = "none"; +defparam \OUTPUT_B~I .input_power_up = "low"; +defparam \OUTPUT_B~I .input_register_mode = "none"; +defparam \OUTPUT_B~I .input_sync_reset = "none"; +defparam \OUTPUT_B~I .oe_async_reset = "none"; +defparam \OUTPUT_B~I .oe_power_up = "low"; +defparam \OUTPUT_B~I .oe_register_mode = "none"; +defparam \OUTPUT_B~I .oe_sync_reset = "none"; +defparam \OUTPUT_B~I .operation_mode = "output"; +defparam \OUTPUT_B~I .output_async_reset = "none"; +defparam \OUTPUT_B~I .output_power_up = "low"; +defparam \OUTPUT_B~I .output_register_mode = "none"; +defparam \OUTPUT_B~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C~I ( + .datain(\inst_|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C)); +// synopsys translate_off +defparam \OUTPUT_C~I .input_async_reset = "none"; +defparam \OUTPUT_C~I .input_power_up = "low"; +defparam \OUTPUT_C~I .input_register_mode = "none"; +defparam \OUTPUT_C~I .input_sync_reset = "none"; +defparam \OUTPUT_C~I .oe_async_reset = "none"; +defparam \OUTPUT_C~I .oe_power_up = "low"; +defparam \OUTPUT_C~I .oe_register_mode = "none"; +defparam \OUTPUT_C~I .oe_sync_reset = "none"; +defparam \OUTPUT_C~I .operation_mode = "output"; +defparam \OUTPUT_C~I .output_async_reset = "none"; +defparam \OUTPUT_C~I .output_power_up = "low"; +defparam \OUTPUT_C~I .output_register_mode = "none"; +defparam \OUTPUT_C~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D~I ( + .datain(\inst_|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D)); +// synopsys translate_off +defparam \OUTPUT_D~I .input_async_reset = "none"; +defparam \OUTPUT_D~I .input_power_up = "low"; +defparam \OUTPUT_D~I .input_register_mode = "none"; +defparam \OUTPUT_D~I .input_sync_reset = "none"; +defparam \OUTPUT_D~I .oe_async_reset = "none"; +defparam \OUTPUT_D~I .oe_power_up = "low"; +defparam \OUTPUT_D~I .oe_register_mode = "none"; +defparam \OUTPUT_D~I .oe_sync_reset = "none"; +defparam \OUTPUT_D~I .operation_mode = "output"; +defparam \OUTPUT_D~I .output_async_reset = "none"; +defparam \OUTPUT_D~I .output_power_up = "low"; +defparam \OUTPUT_D~I .output_register_mode = "none"; +defparam \OUTPUT_D~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E~I ( + .datain(\inst_|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E)); +// synopsys translate_off +defparam \OUTPUT_E~I .input_async_reset = "none"; +defparam \OUTPUT_E~I .input_power_up = "low"; +defparam \OUTPUT_E~I .input_register_mode = "none"; +defparam \OUTPUT_E~I .input_sync_reset = "none"; +defparam \OUTPUT_E~I .oe_async_reset = "none"; +defparam \OUTPUT_E~I .oe_power_up = "low"; +defparam \OUTPUT_E~I .oe_register_mode = "none"; +defparam \OUTPUT_E~I .oe_sync_reset = "none"; +defparam \OUTPUT_E~I .operation_mode = "output"; +defparam \OUTPUT_E~I .output_async_reset = "none"; +defparam \OUTPUT_E~I .output_power_up = "low"; +defparam \OUTPUT_E~I .output_register_mode = "none"; +defparam \OUTPUT_E~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F~I ( + .datain(\inst_|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F)); +// synopsys translate_off +defparam \OUTPUT_F~I .input_async_reset = "none"; +defparam \OUTPUT_F~I .input_power_up = "low"; +defparam \OUTPUT_F~I .input_register_mode = "none"; +defparam \OUTPUT_F~I .input_sync_reset = "none"; +defparam \OUTPUT_F~I .oe_async_reset = "none"; +defparam \OUTPUT_F~I .oe_power_up = "low"; +defparam \OUTPUT_F~I .oe_register_mode = "none"; +defparam \OUTPUT_F~I .oe_sync_reset = "none"; +defparam \OUTPUT_F~I .operation_mode = "output"; +defparam \OUTPUT_F~I .output_async_reset = "none"; +defparam \OUTPUT_F~I .output_power_up = "low"; +defparam \OUTPUT_F~I .output_register_mode = "none"; +defparam \OUTPUT_F~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G~I ( + .datain(!\inst_|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G)); +// synopsys translate_off +defparam \OUTPUT_G~I .input_async_reset = "none"; +defparam \OUTPUT_G~I .input_power_up = "low"; +defparam \OUTPUT_G~I .input_register_mode = "none"; +defparam \OUTPUT_G~I .input_sync_reset = "none"; +defparam \OUTPUT_G~I .oe_async_reset = "none"; +defparam \OUTPUT_G~I .oe_power_up = "low"; +defparam \OUTPUT_G~I .oe_register_mode = "none"; +defparam \OUTPUT_G~I .oe_sync_reset = "none"; +defparam \OUTPUT_G~I .operation_mode = "output"; +defparam \OUTPUT_G~I .output_async_reset = "none"; +defparam \OUTPUT_G~I .output_power_up = "low"; +defparam \OUTPUT_G~I .output_register_mode = "none"; +defparam \OUTPUT_G~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_G3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A1~I ( + .datain(\inst_12|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A1)); +// synopsys translate_off +defparam \OUTPUT_A1~I .input_async_reset = "none"; +defparam \OUTPUT_A1~I .input_power_up = "low"; +defparam \OUTPUT_A1~I .input_register_mode = "none"; +defparam \OUTPUT_A1~I .input_sync_reset = "none"; +defparam \OUTPUT_A1~I .oe_async_reset = "none"; +defparam \OUTPUT_A1~I .oe_power_up = "low"; +defparam \OUTPUT_A1~I .oe_register_mode = "none"; +defparam \OUTPUT_A1~I .oe_sync_reset = "none"; +defparam \OUTPUT_A1~I .operation_mode = "output"; +defparam \OUTPUT_A1~I .output_async_reset = "none"; +defparam \OUTPUT_A1~I .output_power_up = "low"; +defparam \OUTPUT_A1~I .output_register_mode = "none"; +defparam \OUTPUT_A1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B2~I ( + .datain(\inst_12|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B2)); +// synopsys translate_off +defparam \OUTPUT_B2~I .input_async_reset = "none"; +defparam \OUTPUT_B2~I .input_power_up = "low"; +defparam \OUTPUT_B2~I .input_register_mode = "none"; +defparam \OUTPUT_B2~I .input_sync_reset = "none"; +defparam \OUTPUT_B2~I .oe_async_reset = "none"; +defparam \OUTPUT_B2~I .oe_power_up = "low"; +defparam \OUTPUT_B2~I .oe_register_mode = "none"; +defparam \OUTPUT_B2~I .oe_sync_reset = "none"; +defparam \OUTPUT_B2~I .operation_mode = "output"; +defparam \OUTPUT_B2~I .output_async_reset = "none"; +defparam \OUTPUT_B2~I .output_power_up = "low"; +defparam \OUTPUT_B2~I .output_register_mode = "none"; +defparam \OUTPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C3~I ( + .datain(\inst_12|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C3)); +// synopsys translate_off +defparam \OUTPUT_C3~I .input_async_reset = "none"; +defparam \OUTPUT_C3~I .input_power_up = "low"; +defparam \OUTPUT_C3~I .input_register_mode = "none"; +defparam \OUTPUT_C3~I .input_sync_reset = "none"; +defparam \OUTPUT_C3~I .oe_async_reset = "none"; +defparam \OUTPUT_C3~I .oe_power_up = "low"; +defparam \OUTPUT_C3~I .oe_register_mode = "none"; +defparam \OUTPUT_C3~I .oe_sync_reset = "none"; +defparam \OUTPUT_C3~I .operation_mode = "output"; +defparam \OUTPUT_C3~I .output_async_reset = "none"; +defparam \OUTPUT_C3~I .output_power_up = "low"; +defparam \OUTPUT_C3~I .output_register_mode = "none"; +defparam \OUTPUT_C3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D4~I ( + .datain(\inst_12|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D4)); +// synopsys translate_off +defparam \OUTPUT_D4~I .input_async_reset = "none"; +defparam \OUTPUT_D4~I .input_power_up = "low"; +defparam \OUTPUT_D4~I .input_register_mode = "none"; +defparam \OUTPUT_D4~I .input_sync_reset = "none"; +defparam \OUTPUT_D4~I .oe_async_reset = "none"; +defparam \OUTPUT_D4~I .oe_power_up = "low"; +defparam \OUTPUT_D4~I .oe_register_mode = "none"; +defparam \OUTPUT_D4~I .oe_sync_reset = "none"; +defparam \OUTPUT_D4~I .operation_mode = "output"; +defparam \OUTPUT_D4~I .output_async_reset = "none"; +defparam \OUTPUT_D4~I .output_power_up = "low"; +defparam \OUTPUT_D4~I .output_register_mode = "none"; +defparam \OUTPUT_D4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E5~I ( + .datain(\inst_12|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E5)); +// synopsys translate_off +defparam \OUTPUT_E5~I .input_async_reset = "none"; +defparam \OUTPUT_E5~I .input_power_up = "low"; +defparam \OUTPUT_E5~I .input_register_mode = "none"; +defparam \OUTPUT_E5~I .input_sync_reset = "none"; +defparam \OUTPUT_E5~I .oe_async_reset = "none"; +defparam \OUTPUT_E5~I .oe_power_up = "low"; +defparam \OUTPUT_E5~I .oe_register_mode = "none"; +defparam \OUTPUT_E5~I .oe_sync_reset = "none"; +defparam \OUTPUT_E5~I .operation_mode = "output"; +defparam \OUTPUT_E5~I .output_async_reset = "none"; +defparam \OUTPUT_E5~I .output_power_up = "low"; +defparam \OUTPUT_E5~I .output_register_mode = "none"; +defparam \OUTPUT_E5~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F6~I ( + .datain(\inst_12|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F6)); +// synopsys translate_off +defparam \OUTPUT_F6~I .input_async_reset = "none"; +defparam \OUTPUT_F6~I .input_power_up = "low"; +defparam \OUTPUT_F6~I .input_register_mode = "none"; +defparam \OUTPUT_F6~I .input_sync_reset = "none"; +defparam \OUTPUT_F6~I .oe_async_reset = "none"; +defparam \OUTPUT_F6~I .oe_power_up = "low"; +defparam \OUTPUT_F6~I .oe_register_mode = "none"; +defparam \OUTPUT_F6~I .oe_sync_reset = "none"; +defparam \OUTPUT_F6~I .operation_mode = "output"; +defparam \OUTPUT_F6~I .output_async_reset = "none"; +defparam \OUTPUT_F6~I .output_power_up = "low"; +defparam \OUTPUT_F6~I .output_register_mode = "none"; +defparam \OUTPUT_F6~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G7~I ( + .datain(!\inst_12|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G7)); +// synopsys translate_off +defparam \OUTPUT_G7~I .input_async_reset = "none"; +defparam \OUTPUT_G7~I .input_power_up = "low"; +defparam \OUTPUT_G7~I .input_register_mode = "none"; +defparam \OUTPUT_G7~I .input_sync_reset = "none"; +defparam \OUTPUT_G7~I .oe_async_reset = "none"; +defparam \OUTPUT_G7~I .oe_power_up = "low"; +defparam \OUTPUT_G7~I .oe_register_mode = "none"; +defparam \OUTPUT_G7~I .oe_sync_reset = "none"; +defparam \OUTPUT_G7~I .operation_mode = "output"; +defparam \OUTPUT_G7~I .output_async_reset = "none"; +defparam \OUTPUT_G7~I .output_power_up = "low"; +defparam \OUTPUT_G7~I .output_register_mode = "none"; +defparam \OUTPUT_G7~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_fast.vo b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_fast.vo new file mode 100644 index 0000000..e749c11 --- /dev/null +++ b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_fast.vo @@ -0,0 +1,2504 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/03/2020 22:06:52" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_7SegmentDecoder ( + OUTPUT_A, + clk, + ent, + clear, + OUTPUT_B, + OUTPUT_C, + OUTPUT_D, + OUTPUT_E, + OUTPUT_F, + OUTPUT_G, + OUTPUT_A1, + OUTPUT_B2, + OUTPUT_C3, + OUTPUT_D4, + OUTPUT_E5, + OUTPUT_F6, + OUTPUT_G7); +output OUTPUT_A; +input clk; +input ent; +input clear; +output OUTPUT_B; +output OUTPUT_C; +output OUTPUT_D; +output OUTPUT_E; +output OUTPUT_F; +output OUTPUT_G; +output OUTPUT_A1; +output OUTPUT_B2; +output OUTPUT_C3; +output OUTPUT_D4; +output OUTPUT_E5; +output OUTPUT_F6; +output OUTPUT_G7; + +// Design Ports Information +// OUTPUT_A => Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B => Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C => Location: PIN_H2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D => Location: PIN_H1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_A1 => Location: PIN_G3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B2 => Location: PIN_H4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C3 => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D4 => Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E5 => Location: PIN_H6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F6 => Location: PIN_H3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G7 => Location: PIN_H5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// clear => Location: PIN_M22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// ent => Location: PIN_L21, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("YL_7SegmentDecoder_v_fast.sdo"); +// synopsys translate_on + +wire \inst10|count[2]~27_combout ; +wire \inst10|count[5]~33_combout ; +wire \inst10|count[9]~41_combout ; +wire \inst10|count[16]~55_combout ; +wire \inst10|count[24]~72 ; +wire \inst10|count[25]~73_combout ; +wire \inst10|second~3_combout ; +wire \inst8|count[1]~2_combout ; +wire \inst8|op_1~0_combout ; +wire \inst8|op_1~1_combout ; +wire \inst_12|a~13_combout ; +wire \inst11|op_1~0_combout ; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \clear~combout ; +wire \inst10|count[0]~75_combout ; +wire \inst10|count[1]~26 ; +wire \inst10|count[2]~28 ; +wire \inst10|count[3]~30 ; +wire \inst10|count[4]~31_combout ; +wire \inst10|count[12]~47_combout ; +wire \inst10|second~4_combout ; +wire \inst10|count[7]~37_combout ; +wire \inst10|second~2_combout ; +wire \inst10|count[1]~25_combout ; +wire \inst10|count[3]~29_combout ; +wire \inst10|second~1_combout ; +wire \inst10|second~5_combout ; +wire \inst10|second~9_combout ; +wire \inst10|count[4]~32 ; +wire \inst10|count[5]~34 ; +wire \inst10|count[6]~35_combout ; +wire \inst10|count[6]~36 ; +wire \inst10|count[7]~38 ; +wire \inst10|count[8]~39_combout ; +wire \inst10|count[8]~40 ; +wire \inst10|count[9]~42 ; +wire \inst10|count[10]~43_combout ; +wire \inst10|count[10]~44 ; +wire \inst10|count[11]~45_combout ; +wire \inst10|count[11]~46 ; +wire \inst10|count[12]~48 ; +wire \inst10|count[13]~49_combout ; +wire \inst10|count[13]~50 ; +wire \inst10|count[14]~51_combout ; +wire \inst10|count[14]~52 ; +wire \inst10|count[15]~53_combout ; +wire \inst10|count[15]~54 ; +wire \inst10|count[16]~56 ; +wire \inst10|count[17]~57_combout ; +wire \inst10|count[17]~58 ; +wire \inst10|count[18]~59_combout ; +wire \inst10|count[18]~60 ; +wire \inst10|count[19]~61_combout ; +wire \inst10|second~6_combout ; +wire \inst10|count[19]~62 ; +wire \inst10|count[20]~64 ; +wire \inst10|count[21]~65_combout ; +wire \inst10|count[21]~66 ; +wire \inst10|count[22]~68 ; +wire \inst10|count[23]~69_combout ; +wire \inst10|count[23]~70 ; +wire \inst10|count[24]~71_combout ; +wire \inst10|count[20]~63_combout ; +wire \inst10|count[22]~67_combout ; +wire \inst10|second~7_combout ; +wire \inst10|second~8_combout ; +wire \inst8|count[1]~1_combout ; +wire \inst8|count[3]~6_combout ; +wire \inst8|count[1]~4_combout ; +wire \inst8|count[0]~0_combout ; +wire \inst_|a~13_combout ; +wire \inst8|count[1]~3_combout ; +wire \inst8|count[2]~5_combout ; +wire \inst_|a~12_combout ; +wire \inst_|b~3_combout ; +wire \inst_|c~1_combout ; +wire \inst_|d~0_combout ; +wire \inst_|e~0_combout ; +wire \inst_|f~0_combout ; +wire \inst_|g~0_combout ; +wire \ent~combout ; +wire \inst11|count[1]~1_combout ; +wire \inst11|count[1]~2_combout ; +wire \inst11|count[3]~8_combout ; +wire \inst11|_~0_combout ; +wire \inst11|count[0]~0_combout ; +wire \inst11|count[2]~7_combout ; +wire \inst11|count[1]~3_combout ; +wire \inst11|count[1]~4_combout ; +wire \inst11|count[1]~5_combout ; +wire \inst11|count[1]~6_combout ; +wire \inst_12|a~12_combout ; +wire \inst_12|b~3_combout ; +wire \inst_12|c~1_combout ; +wire \inst_12|d~0_combout ; +wire \inst_12|e~0_combout ; +wire \inst_12|f~0_combout ; +wire \inst_12|g~0_combout ; +wire [3:0] \inst8|count ; +wire [25:0] \inst10|count ; +wire [3:0] \inst11|count ; + + +// Location: LCFF_X3_Y21_N11 +cycloneii_lcell_ff \inst10|count[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[2]~27_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [2])); + +// Location: LCFF_X3_Y21_N17 +cycloneii_lcell_ff \inst10|count[5] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[5]~33_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [5])); + +// Location: LCFF_X3_Y21_N25 +cycloneii_lcell_ff \inst10|count[9] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[9]~41_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [9])); + +// Location: LCFF_X3_Y20_N7 +cycloneii_lcell_ff \inst10|count[16] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[16]~55_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [16])); + +// Location: LCFF_X3_Y20_N25 +cycloneii_lcell_ff \inst10|count[25] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[25]~73_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [25])); + +// Location: LCCOMB_X3_Y21_N10 +cycloneii_lcell_comb \inst10|count[2]~27 ( +// Equation(s): +// \inst10|count[2]~27_combout = (\inst10|count [2] & (!\inst10|count[1]~26 )) # (!\inst10|count [2] & ((\inst10|count[1]~26 ) # (GND))) +// \inst10|count[2]~28 = CARRY((!\inst10|count[1]~26 ) # (!\inst10|count [2])) + + .dataa(\inst10|count [2]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[1]~26 ), + .combout(\inst10|count[2]~27_combout ), + .cout(\inst10|count[2]~28 )); +// synopsys translate_off +defparam \inst10|count[2]~27 .lut_mask = 16'h5A5F; +defparam \inst10|count[2]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N16 +cycloneii_lcell_comb \inst10|count[5]~33 ( +// Equation(s): +// \inst10|count[5]~33_combout = (\inst10|count [5] & (\inst10|count[4]~32 $ (GND))) # (!\inst10|count [5] & (!\inst10|count[4]~32 & VCC)) +// \inst10|count[5]~34 = CARRY((\inst10|count [5] & !\inst10|count[4]~32 )) + + .dataa(\inst10|count [5]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[4]~32 ), + .combout(\inst10|count[5]~33_combout ), + .cout(\inst10|count[5]~34 )); +// synopsys translate_off +defparam \inst10|count[5]~33 .lut_mask = 16'hA50A; +defparam \inst10|count[5]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N24 +cycloneii_lcell_comb \inst10|count[9]~41 ( +// Equation(s): +// \inst10|count[9]~41_combout = (\inst10|count [9] & (\inst10|count[8]~40 $ (GND))) # (!\inst10|count [9] & (!\inst10|count[8]~40 & VCC)) +// \inst10|count[9]~42 = CARRY((\inst10|count [9] & !\inst10|count[8]~40 )) + + .dataa(\inst10|count [9]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[8]~40 ), + .combout(\inst10|count[9]~41_combout ), + .cout(\inst10|count[9]~42 )); +// synopsys translate_off +defparam \inst10|count[9]~41 .lut_mask = 16'hA50A; +defparam \inst10|count[9]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N6 +cycloneii_lcell_comb \inst10|count[16]~55 ( +// Equation(s): +// \inst10|count[16]~55_combout = (\inst10|count [16] & (!\inst10|count[15]~54 )) # (!\inst10|count [16] & ((\inst10|count[15]~54 ) # (GND))) +// \inst10|count[16]~56 = CARRY((!\inst10|count[15]~54 ) # (!\inst10|count [16])) + + .dataa(\inst10|count [16]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[15]~54 ), + .combout(\inst10|count[16]~55_combout ), + .cout(\inst10|count[16]~56 )); +// synopsys translate_off +defparam \inst10|count[16]~55 .lut_mask = 16'h5A5F; +defparam \inst10|count[16]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N22 +cycloneii_lcell_comb \inst10|count[24]~71 ( +// Equation(s): +// \inst10|count[24]~71_combout = (\inst10|count [24] & (!\inst10|count[23]~70 )) # (!\inst10|count [24] & ((\inst10|count[23]~70 ) # (GND))) +// \inst10|count[24]~72 = CARRY((!\inst10|count[23]~70 ) # (!\inst10|count [24])) + + .dataa(\inst10|count [24]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[23]~70 ), + .combout(\inst10|count[24]~71_combout ), + .cout(\inst10|count[24]~72 )); +// synopsys translate_off +defparam \inst10|count[24]~71 .lut_mask = 16'h5A5F; +defparam \inst10|count[24]~71 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N24 +cycloneii_lcell_comb \inst10|count[25]~73 ( +// Equation(s): +// \inst10|count[25]~73_combout = \inst10|count [25] $ (!\inst10|count[24]~72 ) + + .dataa(\inst10|count [25]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[24]~72 ), + .combout(\inst10|count[25]~73_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|count[25]~73 .lut_mask = 16'hA5A5; +defparam \inst10|count[25]~73 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N6 +cycloneii_lcell_comb \inst10|second~3 ( +// Equation(s): +// \inst10|second~3_combout = (!\inst10|count [9] & (!\inst10|count [10] & (!\inst10|count [8] & !\inst10|count [11]))) + + .dataa(\inst10|count [9]), + .datab(\inst10|count [10]), + .datac(\inst10|count [8]), + .datad(\inst10|count [11]), + .cin(gnd), + .combout(\inst10|second~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~3 .lut_mask = 16'h0001; +defparam \inst10|second~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N18 +cycloneii_lcell_comb \inst8|count[1]~2 ( +// Equation(s): +// \inst8|count[1]~2_combout = (!\clear~combout & \ent~combout ) + + .dataa(vcc), + .datab(\clear~combout ), + .datac(\ent~combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst8|count[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~2 .lut_mask = 16'h3030; +defparam \inst8|count[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N8 +cycloneii_lcell_comb \inst8|op_1~0 ( +// Equation(s): +// \inst8|op_1~0_combout = \inst8|count [2] $ (((\inst8|count [1] & \inst8|count [0]))) + + .dataa(\inst8|count [2]), + .datab(vcc), + .datac(\inst8|count [1]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst8|op_1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|op_1~0 .lut_mask = 16'h5AAA; +defparam \inst8|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N14 +cycloneii_lcell_comb \inst8|op_1~1 ( +// Equation(s): +// \inst8|op_1~1_combout = \inst8|count [3] $ (((\inst8|count [1] & (\inst8|count [2] & \inst8|count [0])))) + + .dataa(\inst8|count [1]), + .datab(\inst8|count [2]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst8|op_1~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|op_1~1 .lut_mask = 16'h78F0; +defparam \inst8|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N30 +cycloneii_lcell_comb \inst_12|a~13 ( +// Equation(s): +// \inst_12|a~13_combout = (\inst11|count [0] & \inst11|count [1]) + + .dataa(\inst11|count [0]), + .datab(vcc), + .datac(\inst11|count [1]), + .datad(vcc), + .cin(gnd), + .combout(\inst_12|a~13_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|a~13 .lut_mask = 16'hA0A0; +defparam \inst_12|a~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N4 +cycloneii_lcell_comb \inst11|op_1~0 ( +// Equation(s): +// \inst11|op_1~0_combout = \inst11|count [3] $ (((\inst11|count [1] & (\inst11|count [0] & \inst11|count [2])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst11|op_1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|op_1~0 .lut_mask = 16'h6CCC; +defparam \inst11|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_M22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clear~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clear~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clear)); +// synopsys translate_off +defparam \clear~I .input_async_reset = "none"; +defparam \clear~I .input_power_up = "low"; +defparam \clear~I .input_register_mode = "none"; +defparam \clear~I .input_sync_reset = "none"; +defparam \clear~I .oe_async_reset = "none"; +defparam \clear~I .oe_power_up = "low"; +defparam \clear~I .oe_register_mode = "none"; +defparam \clear~I .oe_sync_reset = "none"; +defparam \clear~I .operation_mode = "input"; +defparam \clear~I .output_async_reset = "none"; +defparam \clear~I .output_power_up = "low"; +defparam \clear~I .output_register_mode = "none"; +defparam \clear~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N4 +cycloneii_lcell_comb \inst10|count[0]~75 ( +// Equation(s): +// \inst10|count[0]~75_combout = !\inst10|count [0] + + .dataa(vcc), + .datab(vcc), + .datac(\inst10|count [0]), + .datad(vcc), + .cin(gnd), + .combout(\inst10|count[0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|count[0]~75 .lut_mask = 16'h0F0F; +defparam \inst10|count[0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N5 +cycloneii_lcell_ff \inst10|count[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[0]~75_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [0])); + +// Location: LCCOMB_X3_Y21_N8 +cycloneii_lcell_comb \inst10|count[1]~25 ( +// Equation(s): +// \inst10|count[1]~25_combout = (\inst10|count [1] & (\inst10|count [0] $ (VCC))) # (!\inst10|count [1] & (\inst10|count [0] & VCC)) +// \inst10|count[1]~26 = CARRY((\inst10|count [1] & \inst10|count [0])) + + .dataa(\inst10|count [1]), + .datab(\inst10|count [0]), + .datac(vcc), + .datad(vcc), + .cin(gnd), + .combout(\inst10|count[1]~25_combout ), + .cout(\inst10|count[1]~26 )); +// synopsys translate_off +defparam \inst10|count[1]~25 .lut_mask = 16'h6688; +defparam \inst10|count[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N12 +cycloneii_lcell_comb \inst10|count[3]~29 ( +// Equation(s): +// \inst10|count[3]~29_combout = (\inst10|count [3] & (\inst10|count[2]~28 $ (GND))) # (!\inst10|count [3] & (!\inst10|count[2]~28 & VCC)) +// \inst10|count[3]~30 = CARRY((\inst10|count [3] & !\inst10|count[2]~28 )) + + .dataa(\inst10|count [3]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[2]~28 ), + .combout(\inst10|count[3]~29_combout ), + .cout(\inst10|count[3]~30 )); +// synopsys translate_off +defparam \inst10|count[3]~29 .lut_mask = 16'hA50A; +defparam \inst10|count[3]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N14 +cycloneii_lcell_comb \inst10|count[4]~31 ( +// Equation(s): +// \inst10|count[4]~31_combout = (\inst10|count [4] & (!\inst10|count[3]~30 )) # (!\inst10|count [4] & ((\inst10|count[3]~30 ) # (GND))) +// \inst10|count[4]~32 = CARRY((!\inst10|count[3]~30 ) # (!\inst10|count [4])) + + .dataa(vcc), + .datab(\inst10|count [4]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[3]~30 ), + .combout(\inst10|count[4]~31_combout ), + .cout(\inst10|count[4]~32 )); +// synopsys translate_off +defparam \inst10|count[4]~31 .lut_mask = 16'h3C3F; +defparam \inst10|count[4]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N30 +cycloneii_lcell_comb \inst10|count[12]~47 ( +// Equation(s): +// \inst10|count[12]~47_combout = (\inst10|count [12] & (!\inst10|count[11]~46 )) # (!\inst10|count [12] & ((\inst10|count[11]~46 ) # (GND))) +// \inst10|count[12]~48 = CARRY((!\inst10|count[11]~46 ) # (!\inst10|count [12])) + + .dataa(\inst10|count [12]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[11]~46 ), + .combout(\inst10|count[12]~47_combout ), + .cout(\inst10|count[12]~48 )); +// synopsys translate_off +defparam \inst10|count[12]~47 .lut_mask = 16'h5A5F; +defparam \inst10|count[12]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N1 +cycloneii_lcell_ff \inst10|count[12] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\inst10|count[12]~47_combout ), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [12])); + +// Location: LCCOMB_X2_Y21_N0 +cycloneii_lcell_comb \inst10|second~4 ( +// Equation(s): +// \inst10|second~4_combout = (!\inst10|count [14] & (!\inst10|count [13] & (!\inst10|count [12] & !\inst10|count [15]))) + + .dataa(\inst10|count [14]), + .datab(\inst10|count [13]), + .datac(\inst10|count [12]), + .datad(\inst10|count [15]), + .cin(gnd), + .combout(\inst10|second~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~4 .lut_mask = 16'h0001; +defparam \inst10|second~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y21_N20 +cycloneii_lcell_comb \inst10|count[7]~37 ( +// Equation(s): +// \inst10|count[7]~37_combout = (\inst10|count [7] & (\inst10|count[6]~36 $ (GND))) # (!\inst10|count [7] & (!\inst10|count[6]~36 & VCC)) +// \inst10|count[7]~38 = CARRY((\inst10|count [7] & !\inst10|count[6]~36 )) + + .dataa(\inst10|count [7]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[6]~36 ), + .combout(\inst10|count[7]~37_combout ), + .cout(\inst10|count[7]~38 )); +// synopsys translate_off +defparam \inst10|count[7]~37 .lut_mask = 16'hA50A; +defparam \inst10|count[7]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N21 +cycloneii_lcell_ff \inst10|count[7] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[7]~37_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [7])); + +// Location: LCCOMB_X3_Y21_N0 +cycloneii_lcell_comb \inst10|second~2 ( +// Equation(s): +// \inst10|second~2_combout = (!\inst10|count [5] & (!\inst10|count [4] & (!\inst10|count [7] & !\inst10|count [6]))) + + .dataa(\inst10|count [5]), + .datab(\inst10|count [4]), + .datac(\inst10|count [7]), + .datad(\inst10|count [6]), + .cin(gnd), + .combout(\inst10|second~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~2 .lut_mask = 16'h0001; +defparam \inst10|second~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N9 +cycloneii_lcell_ff \inst10|count[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[1]~25_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [1])); + +// Location: LCFF_X3_Y21_N13 +cycloneii_lcell_ff \inst10|count[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[3]~29_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [3])); + +// Location: LCCOMB_X3_Y21_N2 +cycloneii_lcell_comb \inst10|second~1 ( +// Equation(s): +// \inst10|second~1_combout = (\inst10|count [2] & (!\inst10|count [1] & (\inst10|count [0] & !\inst10|count [3]))) + + .dataa(\inst10|count [2]), + .datab(\inst10|count [1]), + .datac(\inst10|count [0]), + .datad(\inst10|count [3]), + .cin(gnd), + .combout(\inst10|second~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~1 .lut_mask = 16'h0020; +defparam \inst10|second~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N28 +cycloneii_lcell_comb \inst10|second~5 ( +// Equation(s): +// \inst10|second~5_combout = (\inst10|second~3_combout & (\inst10|second~4_combout & (\inst10|second~2_combout & \inst10|second~1_combout ))) + + .dataa(\inst10|second~3_combout ), + .datab(\inst10|second~4_combout ), + .datac(\inst10|second~2_combout ), + .datad(\inst10|second~1_combout ), + .cin(gnd), + .combout(\inst10|second~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~5 .lut_mask = 16'h8000; +defparam \inst10|second~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N10 +cycloneii_lcell_comb \inst10|second~9 ( +// Equation(s): +// \inst10|second~9_combout = (\inst10|second~5_combout & \inst10|second~8_combout ) + + .dataa(vcc), + .datab(\inst10|second~5_combout ), + .datac(vcc), + .datad(\inst10|second~8_combout ), + .cin(gnd), + .combout(\inst10|second~9_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~9 .lut_mask = 16'hCC00; +defparam \inst10|second~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N15 +cycloneii_lcell_ff \inst10|count[4] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[4]~31_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [4])); + +// Location: LCCOMB_X3_Y21_N18 +cycloneii_lcell_comb \inst10|count[6]~35 ( +// Equation(s): +// \inst10|count[6]~35_combout = (\inst10|count [6] & (!\inst10|count[5]~34 )) # (!\inst10|count [6] & ((\inst10|count[5]~34 ) # (GND))) +// \inst10|count[6]~36 = CARRY((!\inst10|count[5]~34 ) # (!\inst10|count [6])) + + .dataa(vcc), + .datab(\inst10|count [6]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[5]~34 ), + .combout(\inst10|count[6]~35_combout ), + .cout(\inst10|count[6]~36 )); +// synopsys translate_off +defparam \inst10|count[6]~35 .lut_mask = 16'h3C3F; +defparam \inst10|count[6]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N19 +cycloneii_lcell_ff \inst10|count[6] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[6]~35_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [6])); + +// Location: LCCOMB_X3_Y21_N22 +cycloneii_lcell_comb \inst10|count[8]~39 ( +// Equation(s): +// \inst10|count[8]~39_combout = (\inst10|count [8] & (!\inst10|count[7]~38 )) # (!\inst10|count [8] & ((\inst10|count[7]~38 ) # (GND))) +// \inst10|count[8]~40 = CARRY((!\inst10|count[7]~38 ) # (!\inst10|count [8])) + + .dataa(vcc), + .datab(\inst10|count [8]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[7]~38 ), + .combout(\inst10|count[8]~39_combout ), + .cout(\inst10|count[8]~40 )); +// synopsys translate_off +defparam \inst10|count[8]~39 .lut_mask = 16'h3C3F; +defparam \inst10|count[8]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N23 +cycloneii_lcell_ff \inst10|count[8] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[8]~39_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [8])); + +// Location: LCCOMB_X3_Y21_N26 +cycloneii_lcell_comb \inst10|count[10]~43 ( +// Equation(s): +// \inst10|count[10]~43_combout = (\inst10|count [10] & (!\inst10|count[9]~42 )) # (!\inst10|count [10] & ((\inst10|count[9]~42 ) # (GND))) +// \inst10|count[10]~44 = CARRY((!\inst10|count[9]~42 ) # (!\inst10|count [10])) + + .dataa(vcc), + .datab(\inst10|count [10]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[9]~42 ), + .combout(\inst10|count[10]~43_combout ), + .cout(\inst10|count[10]~44 )); +// synopsys translate_off +defparam \inst10|count[10]~43 .lut_mask = 16'h3C3F; +defparam \inst10|count[10]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N27 +cycloneii_lcell_ff \inst10|count[10] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[10]~43_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [10])); + +// Location: LCCOMB_X3_Y21_N28 +cycloneii_lcell_comb \inst10|count[11]~45 ( +// Equation(s): +// \inst10|count[11]~45_combout = (\inst10|count [11] & (\inst10|count[10]~44 $ (GND))) # (!\inst10|count [11] & (!\inst10|count[10]~44 & VCC)) +// \inst10|count[11]~46 = CARRY((\inst10|count [11] & !\inst10|count[10]~44 )) + + .dataa(vcc), + .datab(\inst10|count [11]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[10]~44 ), + .combout(\inst10|count[11]~45_combout ), + .cout(\inst10|count[11]~46 )); +// synopsys translate_off +defparam \inst10|count[11]~45 .lut_mask = 16'hC30C; +defparam \inst10|count[11]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y21_N29 +cycloneii_lcell_ff \inst10|count[11] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[11]~45_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [11])); + +// Location: LCCOMB_X3_Y20_N0 +cycloneii_lcell_comb \inst10|count[13]~49 ( +// Equation(s): +// \inst10|count[13]~49_combout = (\inst10|count [13] & (\inst10|count[12]~48 $ (GND))) # (!\inst10|count [13] & (!\inst10|count[12]~48 & VCC)) +// \inst10|count[13]~50 = CARRY((\inst10|count [13] & !\inst10|count[12]~48 )) + + .dataa(vcc), + .datab(\inst10|count [13]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[12]~48 ), + .combout(\inst10|count[13]~49_combout ), + .cout(\inst10|count[13]~50 )); +// synopsys translate_off +defparam \inst10|count[13]~49 .lut_mask = 16'hC30C; +defparam \inst10|count[13]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N1 +cycloneii_lcell_ff \inst10|count[13] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[13]~49_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [13])); + +// Location: LCCOMB_X3_Y20_N2 +cycloneii_lcell_comb \inst10|count[14]~51 ( +// Equation(s): +// \inst10|count[14]~51_combout = (\inst10|count [14] & (!\inst10|count[13]~50 )) # (!\inst10|count [14] & ((\inst10|count[13]~50 ) # (GND))) +// \inst10|count[14]~52 = CARRY((!\inst10|count[13]~50 ) # (!\inst10|count [14])) + + .dataa(vcc), + .datab(\inst10|count [14]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[13]~50 ), + .combout(\inst10|count[14]~51_combout ), + .cout(\inst10|count[14]~52 )); +// synopsys translate_off +defparam \inst10|count[14]~51 .lut_mask = 16'h3C3F; +defparam \inst10|count[14]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N11 +cycloneii_lcell_ff \inst10|count[14] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\inst10|count[14]~51_combout ), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [14])); + +// Location: LCCOMB_X3_Y20_N4 +cycloneii_lcell_comb \inst10|count[15]~53 ( +// Equation(s): +// \inst10|count[15]~53_combout = (\inst10|count [15] & (\inst10|count[14]~52 $ (GND))) # (!\inst10|count [15] & (!\inst10|count[14]~52 & VCC)) +// \inst10|count[15]~54 = CARRY((\inst10|count [15] & !\inst10|count[14]~52 )) + + .dataa(vcc), + .datab(\inst10|count [15]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[14]~52 ), + .combout(\inst10|count[15]~53_combout ), + .cout(\inst10|count[15]~54 )); +// synopsys translate_off +defparam \inst10|count[15]~53 .lut_mask = 16'hC30C; +defparam \inst10|count[15]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N5 +cycloneii_lcell_ff \inst10|count[15] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[15]~53_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [15])); + +// Location: LCCOMB_X3_Y20_N8 +cycloneii_lcell_comb \inst10|count[17]~57 ( +// Equation(s): +// \inst10|count[17]~57_combout = (\inst10|count [17] & (\inst10|count[16]~56 $ (GND))) # (!\inst10|count [17] & (!\inst10|count[16]~56 & VCC)) +// \inst10|count[17]~58 = CARRY((\inst10|count [17] & !\inst10|count[16]~56 )) + + .dataa(\inst10|count [17]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[16]~56 ), + .combout(\inst10|count[17]~57_combout ), + .cout(\inst10|count[17]~58 )); +// synopsys translate_off +defparam \inst10|count[17]~57 .lut_mask = 16'hA50A; +defparam \inst10|count[17]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N9 +cycloneii_lcell_ff \inst10|count[17] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[17]~57_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [17])); + +// Location: LCCOMB_X3_Y20_N10 +cycloneii_lcell_comb \inst10|count[18]~59 ( +// Equation(s): +// \inst10|count[18]~59_combout = (\inst10|count [18] & (!\inst10|count[17]~58 )) # (!\inst10|count [18] & ((\inst10|count[17]~58 ) # (GND))) +// \inst10|count[18]~60 = CARRY((!\inst10|count[17]~58 ) # (!\inst10|count [18])) + + .dataa(\inst10|count [18]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[17]~58 ), + .combout(\inst10|count[18]~59_combout ), + .cout(\inst10|count[18]~60 )); +// synopsys translate_off +defparam \inst10|count[18]~59 .lut_mask = 16'h5A5F; +defparam \inst10|count[18]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N11 +cycloneii_lcell_ff \inst10|count[18] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[18]~59_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [18])); + +// Location: LCCOMB_X3_Y20_N12 +cycloneii_lcell_comb \inst10|count[19]~61 ( +// Equation(s): +// \inst10|count[19]~61_combout = (\inst10|count [19] & (\inst10|count[18]~60 $ (GND))) # (!\inst10|count [19] & (!\inst10|count[18]~60 & VCC)) +// \inst10|count[19]~62 = CARRY((\inst10|count [19] & !\inst10|count[18]~60 )) + + .dataa(\inst10|count [19]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[18]~60 ), + .combout(\inst10|count[19]~61_combout ), + .cout(\inst10|count[19]~62 )); +// synopsys translate_off +defparam \inst10|count[19]~61 .lut_mask = 16'hA50A; +defparam \inst10|count[19]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N13 +cycloneii_lcell_ff \inst10|count[19] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[19]~61_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [19])); + +// Location: LCCOMB_X3_Y20_N30 +cycloneii_lcell_comb \inst10|second~6 ( +// Equation(s): +// \inst10|second~6_combout = (!\inst10|count [16] & (!\inst10|count [17] & (!\inst10|count [18] & !\inst10|count [19]))) + + .dataa(\inst10|count [16]), + .datab(\inst10|count [17]), + .datac(\inst10|count [18]), + .datad(\inst10|count [19]), + .cin(gnd), + .combout(\inst10|second~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~6 .lut_mask = 16'h0001; +defparam \inst10|second~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N14 +cycloneii_lcell_comb \inst10|count[20]~63 ( +// Equation(s): +// \inst10|count[20]~63_combout = (\inst10|count [20] & (!\inst10|count[19]~62 )) # (!\inst10|count [20] & ((\inst10|count[19]~62 ) # (GND))) +// \inst10|count[20]~64 = CARRY((!\inst10|count[19]~62 ) # (!\inst10|count [20])) + + .dataa(\inst10|count [20]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[19]~62 ), + .combout(\inst10|count[20]~63_combout ), + .cout(\inst10|count[20]~64 )); +// synopsys translate_off +defparam \inst10|count[20]~63 .lut_mask = 16'h5A5F; +defparam \inst10|count[20]~63 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N16 +cycloneii_lcell_comb \inst10|count[21]~65 ( +// Equation(s): +// \inst10|count[21]~65_combout = (\inst10|count [21] & (\inst10|count[20]~64 $ (GND))) # (!\inst10|count [21] & (!\inst10|count[20]~64 & VCC)) +// \inst10|count[21]~66 = CARRY((\inst10|count [21] & !\inst10|count[20]~64 )) + + .dataa(vcc), + .datab(\inst10|count [21]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[20]~64 ), + .combout(\inst10|count[21]~65_combout ), + .cout(\inst10|count[21]~66 )); +// synopsys translate_off +defparam \inst10|count[21]~65 .lut_mask = 16'hC30C; +defparam \inst10|count[21]~65 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N17 +cycloneii_lcell_ff \inst10|count[21] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[21]~65_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [21])); + +// Location: LCCOMB_X3_Y20_N18 +cycloneii_lcell_comb \inst10|count[22]~67 ( +// Equation(s): +// \inst10|count[22]~67_combout = (\inst10|count [22] & (!\inst10|count[21]~66 )) # (!\inst10|count [22] & ((\inst10|count[21]~66 ) # (GND))) +// \inst10|count[22]~68 = CARRY((!\inst10|count[21]~66 ) # (!\inst10|count [22])) + + .dataa(\inst10|count [22]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[21]~66 ), + .combout(\inst10|count[22]~67_combout ), + .cout(\inst10|count[22]~68 )); +// synopsys translate_off +defparam \inst10|count[22]~67 .lut_mask = 16'h5A5F; +defparam \inst10|count[22]~67 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N20 +cycloneii_lcell_comb \inst10|count[23]~69 ( +// Equation(s): +// \inst10|count[23]~69_combout = (\inst10|count [23] & (\inst10|count[22]~68 $ (GND))) # (!\inst10|count [23] & (!\inst10|count[22]~68 & VCC)) +// \inst10|count[23]~70 = CARRY((\inst10|count [23] & !\inst10|count[22]~68 )) + + .dataa(vcc), + .datab(\inst10|count [23]), + .datac(vcc), + .datad(vcc), + .cin(\inst10|count[22]~68 ), + .combout(\inst10|count[23]~69_combout ), + .cout(\inst10|count[23]~70 )); +// synopsys translate_off +defparam \inst10|count[23]~69 .lut_mask = 16'hC30C; +defparam \inst10|count[23]~69 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCFF_X3_Y20_N21 +cycloneii_lcell_ff \inst10|count[23] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[23]~69_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [23])); + +// Location: LCFF_X3_Y20_N23 +cycloneii_lcell_ff \inst10|count[24] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[24]~71_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [24])); + +// Location: LCFF_X3_Y20_N15 +cycloneii_lcell_ff \inst10|count[20] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[20]~63_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [20])); + +// Location: LCFF_X3_Y20_N19 +cycloneii_lcell_ff \inst10|count[22] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst10|count[22]~67_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(\inst10|second~9_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst10|count [22])); + +// Location: LCCOMB_X3_Y20_N28 +cycloneii_lcell_comb \inst10|second~7 ( +// Equation(s): +// \inst10|second~7_combout = (!\inst10|count [23] & (!\inst10|count [20] & (!\inst10|count [21] & !\inst10|count [22]))) + + .dataa(\inst10|count [23]), + .datab(\inst10|count [20]), + .datac(\inst10|count [21]), + .datad(\inst10|count [22]), + .cin(gnd), + .combout(\inst10|second~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~7 .lut_mask = 16'h0001; +defparam \inst10|second~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y20_N26 +cycloneii_lcell_comb \inst10|second~8 ( +// Equation(s): +// \inst10|second~8_combout = (!\inst10|count [25] & (\inst10|second~6_combout & (!\inst10|count [24] & \inst10|second~7_combout ))) + + .dataa(\inst10|count [25]), + .datab(\inst10|second~6_combout ), + .datac(\inst10|count [24]), + .datad(\inst10|second~7_combout ), + .cin(gnd), + .combout(\inst10|second~8_combout ), + .cout()); +// synopsys translate_off +defparam \inst10|second~8 .lut_mask = 16'h0400; +defparam \inst10|second~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N2 +cycloneii_lcell_comb \inst8|count[1]~1 ( +// Equation(s): +// \inst8|count[1]~1_combout = (!\clear~combout & (((!\inst10|second~5_combout ) # (!\inst10|second~8_combout )) # (!\ent~combout ))) + + .dataa(\ent~combout ), + .datab(\clear~combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst10|second~5_combout ), + .cin(gnd), + .combout(\inst8|count[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~1 .lut_mask = 16'h1333; +defparam \inst8|count[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N14 +cycloneii_lcell_comb \inst8|count[3]~6 ( +// Equation(s): +// \inst8|count[3]~6_combout = (\inst8|op_1~1_combout & ((\inst8|count[1]~3_combout ) # ((\inst8|count [3] & \inst8|count[1]~1_combout )))) # (!\inst8|op_1~1_combout & (((\inst8|count [3] & \inst8|count[1]~1_combout )))) + + .dataa(\inst8|op_1~1_combout ), + .datab(\inst8|count[1]~3_combout ), + .datac(\inst8|count [3]), + .datad(\inst8|count[1]~1_combout ), + .cin(gnd), + .combout(\inst8|count[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[3]~6 .lut_mask = 16'hF888; +defparam \inst8|count[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N15 +cycloneii_lcell_ff \inst8|count[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[3]~6_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [3])); + +// Location: LCCOMB_X2_Y21_N6 +cycloneii_lcell_comb \inst8|count[1]~4 ( +// Equation(s): +// \inst8|count[1]~4_combout = (\inst8|count [1] & ((\inst8|count[1]~1_combout ) # ((!\inst8|count [0] & \inst8|count[1]~3_combout )))) # (!\inst8|count [1] & (\inst8|count [0] & (\inst8|count[1]~3_combout ))) + + .dataa(\inst8|count [0]), + .datab(\inst8|count[1]~3_combout ), + .datac(\inst8|count [1]), + .datad(\inst8|count[1]~1_combout ), + .cin(gnd), + .combout(\inst8|count[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~4 .lut_mask = 16'hF848; +defparam \inst8|count[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N7 +cycloneii_lcell_ff \inst8|count[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[1]~4_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [1])); + +// Location: LCCOMB_X2_Y21_N24 +cycloneii_lcell_comb \inst8|count[0]~0 ( +// Equation(s): +// \inst8|count[0]~0_combout = (!\clear~combout & (\inst8|count [0] $ (((\ent~combout & \inst10|second~9_combout ))))) + + .dataa(\ent~combout ), + .datab(\clear~combout ), + .datac(\inst8|count [0]), + .datad(\inst10|second~9_combout ), + .cin(gnd), + .combout(\inst8|count[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[0]~0 .lut_mask = 16'h1230; +defparam \inst8|count[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N25 +cycloneii_lcell_ff \inst8|count[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[0]~0_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [0])); + +// Location: LCCOMB_X1_Y21_N12 +cycloneii_lcell_comb \inst_|a~13 ( +// Equation(s): +// \inst_|a~13_combout = (!\inst8|count [2] & (\inst8|count [3] & (\inst8|count [1] & \inst8|count [0]))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [3]), + .datac(\inst8|count [1]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|a~13_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|a~13 .lut_mask = 16'h4000; +defparam \inst_|a~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N8 +cycloneii_lcell_comb \inst8|count[1]~3 ( +// Equation(s): +// \inst8|count[1]~3_combout = (\inst8|count[1]~2_combout & (!\inst_|a~13_combout & (\inst10|second~8_combout & \inst10|second~5_combout ))) + + .dataa(\inst8|count[1]~2_combout ), + .datab(\inst_|a~13_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst10|second~5_combout ), + .cin(gnd), + .combout(\inst8|count[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[1]~3 .lut_mask = 16'h2000; +defparam \inst8|count[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N4 +cycloneii_lcell_comb \inst8|count[2]~5 ( +// Equation(s): +// \inst8|count[2]~5_combout = (\inst8|op_1~0_combout & ((\inst8|count[1]~3_combout ) # ((\inst8|count [2] & \inst8|count[1]~1_combout )))) # (!\inst8|op_1~0_combout & (((\inst8|count [2] & \inst8|count[1]~1_combout )))) + + .dataa(\inst8|op_1~0_combout ), + .datab(\inst8|count[1]~3_combout ), + .datac(\inst8|count [2]), + .datad(\inst8|count[1]~1_combout ), + .cin(gnd), + .combout(\inst8|count[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst8|count[2]~5 .lut_mask = 16'hF888; +defparam \inst8|count[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N5 +cycloneii_lcell_ff \inst8|count[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst8|count[2]~5_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst8|count [2])); + +// Location: LCCOMB_X1_Y20_N28 +cycloneii_lcell_comb \inst_|a~12 ( +// Equation(s): +// \inst_|a~12_combout = (\inst8|count [2] & (!\inst8|count [1] & (\inst8|count [3] $ (!\inst8|count [0])))) # (!\inst8|count [2] & (\inst8|count [0] & (\inst8|count [1] $ (!\inst8|count [3])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|a~12 .lut_mask = 16'h6102; +defparam \inst_|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N22 +cycloneii_lcell_comb \inst_|b~3 ( +// Equation(s): +// \inst_|b~3_combout = (\inst8|count [1] & ((\inst8|count [0] & ((\inst8|count [3]))) # (!\inst8|count [0] & (\inst8|count [2])))) # (!\inst8|count [1] & (\inst8|count [2] & (\inst8|count [3] $ (\inst8|count [0])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|b~3 .lut_mask = 16'hC2A8; +defparam \inst_|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N16 +cycloneii_lcell_comb \inst_|c~1 ( +// Equation(s): +// \inst_|c~1_combout = (\inst8|count [2] & (\inst8|count [3] & ((\inst8|count [1]) # (!\inst8|count [0])))) # (!\inst8|count [2] & (\inst8|count [1] & (!\inst8|count [3] & !\inst8|count [0]))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|c~1 .lut_mask = 16'h80A4; +defparam \inst_|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N26 +cycloneii_lcell_comb \inst_|d~0 ( +// Equation(s): +// \inst_|d~0_combout = (\inst8|count [1] & ((\inst8|count [2] & ((\inst8|count [0]))) # (!\inst8|count [2] & (\inst8|count [3] & !\inst8|count [0])))) # (!\inst8|count [1] & (!\inst8|count [3] & (\inst8|count [2] $ (\inst8|count [0])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|d~0 .lut_mask = 16'h8942; +defparam \inst_|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N20 +cycloneii_lcell_comb \inst_|e~0 ( +// Equation(s): +// \inst_|e~0_combout = (\inst8|count [1] & (((!\inst8|count [3] & \inst8|count [0])))) # (!\inst8|count [1] & ((\inst8|count [2] & (!\inst8|count [3])) # (!\inst8|count [2] & ((\inst8|count [0]))))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|e~0 .lut_mask = 16'h1F02; +defparam \inst_|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N10 +cycloneii_lcell_comb \inst_|f~0 ( +// Equation(s): +// \inst_|f~0_combout = (\inst8|count [2] & (\inst8|count [0] & (\inst8|count [1] $ (\inst8|count [3])))) # (!\inst8|count [2] & (!\inst8|count [3] & ((\inst8|count [1]) # (\inst8|count [0])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|f~0 .lut_mask = 16'h2D04; +defparam \inst_|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y20_N12 +cycloneii_lcell_comb \inst_|g~0 ( +// Equation(s): +// \inst_|g~0_combout = (\inst8|count [0] & ((\inst8|count [3]) # (\inst8|count [2] $ (\inst8|count [1])))) # (!\inst8|count [0] & ((\inst8|count [1]) # (\inst8|count [2] $ (\inst8|count [3])))) + + .dataa(\inst8|count [2]), + .datab(\inst8|count [1]), + .datac(\inst8|count [3]), + .datad(\inst8|count [0]), + .cin(gnd), + .combout(\inst_|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|g~0 .lut_mask = 16'hF6DE; +defparam \inst_|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_L21, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \ent~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\ent~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(ent)); +// synopsys translate_off +defparam \ent~I .input_async_reset = "none"; +defparam \ent~I .input_power_up = "low"; +defparam \ent~I .input_register_mode = "none"; +defparam \ent~I .input_sync_reset = "none"; +defparam \ent~I .oe_async_reset = "none"; +defparam \ent~I .oe_power_up = "low"; +defparam \ent~I .oe_register_mode = "none"; +defparam \ent~I .oe_sync_reset = "none"; +defparam \ent~I .operation_mode = "input"; +defparam \ent~I .output_async_reset = "none"; +defparam \ent~I .output_power_up = "low"; +defparam \ent~I .output_register_mode = "none"; +defparam \ent~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N24 +cycloneii_lcell_comb \inst11|count[1]~1 ( +// Equation(s): +// \inst11|count[1]~1_combout = (!\inst_|a~13_combout ) # (!\ent~combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\ent~combout ), + .datad(\inst_|a~13_combout ), + .cin(gnd), + .combout(\inst11|count[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~1 .lut_mask = 16'h0FFF; +defparam \inst11|count[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N12 +cycloneii_lcell_comb \inst11|count[1]~2 ( +// Equation(s): +// \inst11|count[1]~2_combout = (!\clear~combout & (((\inst11|count[1]~1_combout ) # (!\inst10|second~8_combout )) # (!\inst10|second~5_combout ))) + + .dataa(\clear~combout ), + .datab(\inst10|second~5_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst11|count[1]~1_combout ), + .cin(gnd), + .combout(\inst11|count[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~2 .lut_mask = 16'h5515; +defparam \inst11|count[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N18 +cycloneii_lcell_comb \inst11|count[3]~8 ( +// Equation(s): +// \inst11|count[3]~8_combout = (\inst11|op_1~0_combout & ((\inst11|count[1]~5_combout ) # ((\inst11|count [3] & \inst11|count[1]~2_combout )))) # (!\inst11|op_1~0_combout & (((\inst11|count [3] & \inst11|count[1]~2_combout )))) + + .dataa(\inst11|op_1~0_combout ), + .datab(\inst11|count[1]~5_combout ), + .datac(\inst11|count [3]), + .datad(\inst11|count[1]~2_combout ), + .cin(gnd), + .combout(\inst11|count[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[3]~8 .lut_mask = 16'hF888; +defparam \inst11|count[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N19 +cycloneii_lcell_ff \inst11|count[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[3]~8_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [3])); + +// Location: LCCOMB_X2_Y21_N30 +cycloneii_lcell_comb \inst11|_~0 ( +// Equation(s): +// \inst11|_~0_combout = (\ent~combout & (\inst_|a~13_combout & (\inst10|second~8_combout & \inst10|second~5_combout ))) + + .dataa(\ent~combout ), + .datab(\inst_|a~13_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst10|second~5_combout ), + .cin(gnd), + .combout(\inst11|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|_~0 .lut_mask = 16'h8000; +defparam \inst11|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N16 +cycloneii_lcell_comb \inst11|count[0]~0 ( +// Equation(s): +// \inst11|count[0]~0_combout = (!\clear~combout & (\inst11|count [0] $ (\inst11|_~0_combout ))) + + .dataa(vcc), + .datab(\clear~combout ), + .datac(\inst11|count [0]), + .datad(\inst11|_~0_combout ), + .cin(gnd), + .combout(\inst11|count[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[0]~0 .lut_mask = 16'h0330; +defparam \inst11|count[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N17 +cycloneii_lcell_ff \inst11|count[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[0]~0_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [0])); + +// Location: LCCOMB_X2_Y21_N20 +cycloneii_lcell_comb \inst11|count[2]~7 ( +// Equation(s): +// \inst11|count[2]~7_combout = (\inst11|count [2] & ((\inst11|count[1]~2_combout ) # ((!\inst_12|a~13_combout & \inst11|count[1]~5_combout )))) # (!\inst11|count [2] & (\inst_12|a~13_combout & (\inst11|count[1]~5_combout ))) + + .dataa(\inst_12|a~13_combout ), + .datab(\inst11|count[1]~5_combout ), + .datac(\inst11|count [2]), + .datad(\inst11|count[1]~2_combout ), + .cin(gnd), + .combout(\inst11|count[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[2]~7 .lut_mask = 16'hF848; +defparam \inst11|count[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N21 +cycloneii_lcell_ff \inst11|count[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[2]~7_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [2])); + +// Location: LCCOMB_X1_Y21_N2 +cycloneii_lcell_comb \inst11|count[1]~3 ( +// Equation(s): +// \inst11|count[1]~3_combout = (((\inst11|count [2]) # (!\inst11|count [0])) # (!\inst11|count [3])) # (!\inst11|count [1]) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst11|count[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~3 .lut_mask = 16'hFF7F; +defparam \inst11|count[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N16 +cycloneii_lcell_comb \inst11|count[1]~4 ( +// Equation(s): +// \inst11|count[1]~4_combout = (!\clear~combout & (\ent~combout & \inst11|count[1]~3_combout )) + + .dataa(vcc), + .datab(\clear~combout ), + .datac(\ent~combout ), + .datad(\inst11|count[1]~3_combout ), + .cin(gnd), + .combout(\inst11|count[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~4 .lut_mask = 16'h3000; +defparam \inst11|count[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N22 +cycloneii_lcell_comb \inst11|count[1]~5 ( +// Equation(s): +// \inst11|count[1]~5_combout = (\inst10|second~5_combout & (\inst_|a~13_combout & (\inst10|second~8_combout & \inst11|count[1]~4_combout ))) + + .dataa(\inst10|second~5_combout ), + .datab(\inst_|a~13_combout ), + .datac(\inst10|second~8_combout ), + .datad(\inst11|count[1]~4_combout ), + .cin(gnd), + .combout(\inst11|count[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~5 .lut_mask = 16'h8000; +defparam \inst11|count[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y21_N26 +cycloneii_lcell_comb \inst11|count[1]~6 ( +// Equation(s): +// \inst11|count[1]~6_combout = (\inst11|count [1] & ((\inst11|count[1]~2_combout ) # ((!\inst11|count [0] & \inst11|count[1]~5_combout )))) # (!\inst11|count [1] & (\inst11|count [0] & (\inst11|count[1]~5_combout ))) + + .dataa(\inst11|count [0]), + .datab(\inst11|count[1]~5_combout ), + .datac(\inst11|count [1]), + .datad(\inst11|count[1]~2_combout ), + .cin(gnd), + .combout(\inst11|count[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst11|count[1]~6 .lut_mask = 16'hF848; +defparam \inst11|count[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y21_N27 +cycloneii_lcell_ff \inst11|count[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst11|count[1]~6_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst11|count [1])); + +// Location: LCCOMB_X1_Y21_N20 +cycloneii_lcell_comb \inst_12|a~12 ( +// Equation(s): +// \inst_12|a~12_combout = (\inst11|count [3] & (\inst11|count [0] & (\inst11|count [1] $ (\inst11|count [2])))) # (!\inst11|count [3] & (!\inst11|count [1] & (\inst11|count [0] $ (\inst11|count [2])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|a~12 .lut_mask = 16'h4190; +defparam \inst_12|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N10 +cycloneii_lcell_comb \inst_12|b~3 ( +// Equation(s): +// \inst_12|b~3_combout = (\inst11|count [1] & ((\inst11|count [0] & (\inst11|count [3])) # (!\inst11|count [0] & ((\inst11|count [2]))))) # (!\inst11|count [1] & (\inst11|count [2] & (\inst11|count [3] $ (\inst11|count [0])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|b~3 .lut_mask = 16'h9E80; +defparam \inst_12|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y19_N0 +cycloneii_lcell_comb \inst_12|c~1 ( +// Equation(s): +// \inst_12|c~1_combout = (\inst11|count [3] & (\inst11|count [2] & ((\inst11|count [1]) # (!\inst11|count [0])))) # (!\inst11|count [3] & (!\inst11|count [0] & (!\inst11|count [2] & \inst11|count [1]))) + + .dataa(\inst11|count [3]), + .datab(\inst11|count [0]), + .datac(\inst11|count [2]), + .datad(\inst11|count [1]), + .cin(gnd), + .combout(\inst_12|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|c~1 .lut_mask = 16'hA120; +defparam \inst_12|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y19_N26 +cycloneii_lcell_comb \inst_12|d~0 ( +// Equation(s): +// \inst_12|d~0_combout = (\inst11|count [1] & ((\inst11|count [0] & ((\inst11|count [2]))) # (!\inst11|count [0] & (\inst11|count [3] & !\inst11|count [2])))) # (!\inst11|count [1] & (!\inst11|count [3] & (\inst11|count [0] $ (\inst11|count [2])))) + + .dataa(\inst11|count [3]), + .datab(\inst11|count [0]), + .datac(\inst11|count [2]), + .datad(\inst11|count [1]), + .cin(gnd), + .combout(\inst_12|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|d~0 .lut_mask = 16'hC214; +defparam \inst_12|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N0 +cycloneii_lcell_comb \inst_12|e~0 ( +// Equation(s): +// \inst_12|e~0_combout = (\inst11|count [1] & (!\inst11|count [3] & (\inst11|count [0]))) # (!\inst11|count [1] & ((\inst11|count [2] & (!\inst11|count [3])) # (!\inst11|count [2] & ((\inst11|count [0]))))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|e~0 .lut_mask = 16'h3170; +defparam \inst_12|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y19_N20 +cycloneii_lcell_comb \inst_12|f~0 ( +// Equation(s): +// \inst_12|f~0_combout = (\inst11|count [0] & (\inst11|count [3] $ (((\inst11|count [1]) # (!\inst11|count [2]))))) # (!\inst11|count [0] & (!\inst11|count [3] & (!\inst11|count [2] & \inst11|count [1]))) + + .dataa(\inst11|count [3]), + .datab(\inst11|count [0]), + .datac(\inst11|count [2]), + .datad(\inst11|count [1]), + .cin(gnd), + .combout(\inst_12|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|f~0 .lut_mask = 16'h4584; +defparam \inst_12|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y21_N26 +cycloneii_lcell_comb \inst_12|g~0 ( +// Equation(s): +// \inst_12|g~0_combout = (\inst11|count [0] & ((\inst11|count [3]) # (\inst11|count [1] $ (\inst11|count [2])))) # (!\inst11|count [0] & ((\inst11|count [1]) # (\inst11|count [3] $ (\inst11|count [2])))) + + .dataa(\inst11|count [1]), + .datab(\inst11|count [3]), + .datac(\inst11|count [0]), + .datad(\inst11|count [2]), + .cin(gnd), + .combout(\inst_12|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_12|g~0 .lut_mask = 16'hDBEE; +defparam \inst_12|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A~I ( + .datain(\inst_|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A)); +// synopsys translate_off +defparam \OUTPUT_A~I .input_async_reset = "none"; +defparam \OUTPUT_A~I .input_power_up = "low"; +defparam \OUTPUT_A~I .input_register_mode = "none"; +defparam \OUTPUT_A~I .input_sync_reset = "none"; +defparam \OUTPUT_A~I .oe_async_reset = "none"; +defparam \OUTPUT_A~I .oe_power_up = "low"; +defparam \OUTPUT_A~I .oe_register_mode = "none"; +defparam \OUTPUT_A~I .oe_sync_reset = "none"; +defparam \OUTPUT_A~I .operation_mode = "output"; +defparam \OUTPUT_A~I .output_async_reset = "none"; +defparam \OUTPUT_A~I .output_power_up = "low"; +defparam \OUTPUT_A~I .output_register_mode = "none"; +defparam \OUTPUT_A~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B~I ( + .datain(\inst_|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B)); +// synopsys translate_off +defparam \OUTPUT_B~I .input_async_reset = "none"; +defparam \OUTPUT_B~I .input_power_up = "low"; +defparam \OUTPUT_B~I .input_register_mode = "none"; +defparam \OUTPUT_B~I .input_sync_reset = "none"; +defparam \OUTPUT_B~I .oe_async_reset = "none"; +defparam \OUTPUT_B~I .oe_power_up = "low"; +defparam \OUTPUT_B~I .oe_register_mode = "none"; +defparam \OUTPUT_B~I .oe_sync_reset = "none"; +defparam \OUTPUT_B~I .operation_mode = "output"; +defparam \OUTPUT_B~I .output_async_reset = "none"; +defparam \OUTPUT_B~I .output_power_up = "low"; +defparam \OUTPUT_B~I .output_register_mode = "none"; +defparam \OUTPUT_B~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C~I ( + .datain(\inst_|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C)); +// synopsys translate_off +defparam \OUTPUT_C~I .input_async_reset = "none"; +defparam \OUTPUT_C~I .input_power_up = "low"; +defparam \OUTPUT_C~I .input_register_mode = "none"; +defparam \OUTPUT_C~I .input_sync_reset = "none"; +defparam \OUTPUT_C~I .oe_async_reset = "none"; +defparam \OUTPUT_C~I .oe_power_up = "low"; +defparam \OUTPUT_C~I .oe_register_mode = "none"; +defparam \OUTPUT_C~I .oe_sync_reset = "none"; +defparam \OUTPUT_C~I .operation_mode = "output"; +defparam \OUTPUT_C~I .output_async_reset = "none"; +defparam \OUTPUT_C~I .output_power_up = "low"; +defparam \OUTPUT_C~I .output_register_mode = "none"; +defparam \OUTPUT_C~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D~I ( + .datain(\inst_|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D)); +// synopsys translate_off +defparam \OUTPUT_D~I .input_async_reset = "none"; +defparam \OUTPUT_D~I .input_power_up = "low"; +defparam \OUTPUT_D~I .input_register_mode = "none"; +defparam \OUTPUT_D~I .input_sync_reset = "none"; +defparam \OUTPUT_D~I .oe_async_reset = "none"; +defparam \OUTPUT_D~I .oe_power_up = "low"; +defparam \OUTPUT_D~I .oe_register_mode = "none"; +defparam \OUTPUT_D~I .oe_sync_reset = "none"; +defparam \OUTPUT_D~I .operation_mode = "output"; +defparam \OUTPUT_D~I .output_async_reset = "none"; +defparam \OUTPUT_D~I .output_power_up = "low"; +defparam \OUTPUT_D~I .output_register_mode = "none"; +defparam \OUTPUT_D~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E~I ( + .datain(\inst_|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E)); +// synopsys translate_off +defparam \OUTPUT_E~I .input_async_reset = "none"; +defparam \OUTPUT_E~I .input_power_up = "low"; +defparam \OUTPUT_E~I .input_register_mode = "none"; +defparam \OUTPUT_E~I .input_sync_reset = "none"; +defparam \OUTPUT_E~I .oe_async_reset = "none"; +defparam \OUTPUT_E~I .oe_power_up = "low"; +defparam \OUTPUT_E~I .oe_register_mode = "none"; +defparam \OUTPUT_E~I .oe_sync_reset = "none"; +defparam \OUTPUT_E~I .operation_mode = "output"; +defparam \OUTPUT_E~I .output_async_reset = "none"; +defparam \OUTPUT_E~I .output_power_up = "low"; +defparam \OUTPUT_E~I .output_register_mode = "none"; +defparam \OUTPUT_E~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F~I ( + .datain(\inst_|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F)); +// synopsys translate_off +defparam \OUTPUT_F~I .input_async_reset = "none"; +defparam \OUTPUT_F~I .input_power_up = "low"; +defparam \OUTPUT_F~I .input_register_mode = "none"; +defparam \OUTPUT_F~I .input_sync_reset = "none"; +defparam \OUTPUT_F~I .oe_async_reset = "none"; +defparam \OUTPUT_F~I .oe_power_up = "low"; +defparam \OUTPUT_F~I .oe_register_mode = "none"; +defparam \OUTPUT_F~I .oe_sync_reset = "none"; +defparam \OUTPUT_F~I .operation_mode = "output"; +defparam \OUTPUT_F~I .output_async_reset = "none"; +defparam \OUTPUT_F~I .output_power_up = "low"; +defparam \OUTPUT_F~I .output_register_mode = "none"; +defparam \OUTPUT_F~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G~I ( + .datain(!\inst_|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G)); +// synopsys translate_off +defparam \OUTPUT_G~I .input_async_reset = "none"; +defparam \OUTPUT_G~I .input_power_up = "low"; +defparam \OUTPUT_G~I .input_register_mode = "none"; +defparam \OUTPUT_G~I .input_sync_reset = "none"; +defparam \OUTPUT_G~I .oe_async_reset = "none"; +defparam \OUTPUT_G~I .oe_power_up = "low"; +defparam \OUTPUT_G~I .oe_register_mode = "none"; +defparam \OUTPUT_G~I .oe_sync_reset = "none"; +defparam \OUTPUT_G~I .operation_mode = "output"; +defparam \OUTPUT_G~I .output_async_reset = "none"; +defparam \OUTPUT_G~I .output_power_up = "low"; +defparam \OUTPUT_G~I .output_register_mode = "none"; +defparam \OUTPUT_G~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_G3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A1~I ( + .datain(\inst_12|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A1)); +// synopsys translate_off +defparam \OUTPUT_A1~I .input_async_reset = "none"; +defparam \OUTPUT_A1~I .input_power_up = "low"; +defparam \OUTPUT_A1~I .input_register_mode = "none"; +defparam \OUTPUT_A1~I .input_sync_reset = "none"; +defparam \OUTPUT_A1~I .oe_async_reset = "none"; +defparam \OUTPUT_A1~I .oe_power_up = "low"; +defparam \OUTPUT_A1~I .oe_register_mode = "none"; +defparam \OUTPUT_A1~I .oe_sync_reset = "none"; +defparam \OUTPUT_A1~I .operation_mode = "output"; +defparam \OUTPUT_A1~I .output_async_reset = "none"; +defparam \OUTPUT_A1~I .output_power_up = "low"; +defparam \OUTPUT_A1~I .output_register_mode = "none"; +defparam \OUTPUT_A1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B2~I ( + .datain(\inst_12|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B2)); +// synopsys translate_off +defparam \OUTPUT_B2~I .input_async_reset = "none"; +defparam \OUTPUT_B2~I .input_power_up = "low"; +defparam \OUTPUT_B2~I .input_register_mode = "none"; +defparam \OUTPUT_B2~I .input_sync_reset = "none"; +defparam \OUTPUT_B2~I .oe_async_reset = "none"; +defparam \OUTPUT_B2~I .oe_power_up = "low"; +defparam \OUTPUT_B2~I .oe_register_mode = "none"; +defparam \OUTPUT_B2~I .oe_sync_reset = "none"; +defparam \OUTPUT_B2~I .operation_mode = "output"; +defparam \OUTPUT_B2~I .output_async_reset = "none"; +defparam \OUTPUT_B2~I .output_power_up = "low"; +defparam \OUTPUT_B2~I .output_register_mode = "none"; +defparam \OUTPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C3~I ( + .datain(\inst_12|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C3)); +// synopsys translate_off +defparam \OUTPUT_C3~I .input_async_reset = "none"; +defparam \OUTPUT_C3~I .input_power_up = "low"; +defparam \OUTPUT_C3~I .input_register_mode = "none"; +defparam \OUTPUT_C3~I .input_sync_reset = "none"; +defparam \OUTPUT_C3~I .oe_async_reset = "none"; +defparam \OUTPUT_C3~I .oe_power_up = "low"; +defparam \OUTPUT_C3~I .oe_register_mode = "none"; +defparam \OUTPUT_C3~I .oe_sync_reset = "none"; +defparam \OUTPUT_C3~I .operation_mode = "output"; +defparam \OUTPUT_C3~I .output_async_reset = "none"; +defparam \OUTPUT_C3~I .output_power_up = "low"; +defparam \OUTPUT_C3~I .output_register_mode = "none"; +defparam \OUTPUT_C3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D4~I ( + .datain(\inst_12|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D4)); +// synopsys translate_off +defparam \OUTPUT_D4~I .input_async_reset = "none"; +defparam \OUTPUT_D4~I .input_power_up = "low"; +defparam \OUTPUT_D4~I .input_register_mode = "none"; +defparam \OUTPUT_D4~I .input_sync_reset = "none"; +defparam \OUTPUT_D4~I .oe_async_reset = "none"; +defparam \OUTPUT_D4~I .oe_power_up = "low"; +defparam \OUTPUT_D4~I .oe_register_mode = "none"; +defparam \OUTPUT_D4~I .oe_sync_reset = "none"; +defparam \OUTPUT_D4~I .operation_mode = "output"; +defparam \OUTPUT_D4~I .output_async_reset = "none"; +defparam \OUTPUT_D4~I .output_power_up = "low"; +defparam \OUTPUT_D4~I .output_register_mode = "none"; +defparam \OUTPUT_D4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E5~I ( + .datain(\inst_12|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E5)); +// synopsys translate_off +defparam \OUTPUT_E5~I .input_async_reset = "none"; +defparam \OUTPUT_E5~I .input_power_up = "low"; +defparam \OUTPUT_E5~I .input_register_mode = "none"; +defparam \OUTPUT_E5~I .input_sync_reset = "none"; +defparam \OUTPUT_E5~I .oe_async_reset = "none"; +defparam \OUTPUT_E5~I .oe_power_up = "low"; +defparam \OUTPUT_E5~I .oe_register_mode = "none"; +defparam \OUTPUT_E5~I .oe_sync_reset = "none"; +defparam \OUTPUT_E5~I .operation_mode = "output"; +defparam \OUTPUT_E5~I .output_async_reset = "none"; +defparam \OUTPUT_E5~I .output_power_up = "low"; +defparam \OUTPUT_E5~I .output_register_mode = "none"; +defparam \OUTPUT_E5~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F6~I ( + .datain(\inst_12|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F6)); +// synopsys translate_off +defparam \OUTPUT_F6~I .input_async_reset = "none"; +defparam \OUTPUT_F6~I .input_power_up = "low"; +defparam \OUTPUT_F6~I .input_register_mode = "none"; +defparam \OUTPUT_F6~I .input_sync_reset = "none"; +defparam \OUTPUT_F6~I .oe_async_reset = "none"; +defparam \OUTPUT_F6~I .oe_power_up = "low"; +defparam \OUTPUT_F6~I .oe_register_mode = "none"; +defparam \OUTPUT_F6~I .oe_sync_reset = "none"; +defparam \OUTPUT_F6~I .operation_mode = "output"; +defparam \OUTPUT_F6~I .output_async_reset = "none"; +defparam \OUTPUT_F6~I .output_power_up = "low"; +defparam \OUTPUT_F6~I .output_register_mode = "none"; +defparam \OUTPUT_F6~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G7~I ( + .datain(!\inst_12|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G7)); +// synopsys translate_off +defparam \OUTPUT_G7~I .input_async_reset = "none"; +defparam \OUTPUT_G7~I .input_power_up = "low"; +defparam \OUTPUT_G7~I .input_register_mode = "none"; +defparam \OUTPUT_G7~I .input_sync_reset = "none"; +defparam \OUTPUT_G7~I .oe_async_reset = "none"; +defparam \OUTPUT_G7~I .oe_power_up = "low"; +defparam \OUTPUT_G7~I .oe_register_mode = "none"; +defparam \OUTPUT_G7~I .oe_sync_reset = "none"; +defparam \OUTPUT_G7~I .operation_mode = "output"; +defparam \OUTPUT_G7~I .output_async_reset = "none"; +defparam \OUTPUT_G7~I .output_power_up = "low"; +defparam \OUTPUT_G7~I .output_register_mode = "none"; +defparam \OUTPUT_G7~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_modelsim.xrf b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_modelsim.xrf new file mode 100644 index 0000000..66d2b67 --- /dev/null +++ b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_modelsim.xrf @@ -0,0 +1,136 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_dec_counter.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.vwf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder2.bdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder2.vwf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_sec_cnt.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder3.vwf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_Cascade.bdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_cascade.vwf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/db/YL_7SegmentDecoder.cbx.xml +design_name = YL_7SegmentDecoder +instance = comp, \inst10|count[2] , inst10|count[2], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[5] , inst10|count[5], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[9] , inst10|count[9], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[16] , inst10|count[16], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[25] , inst10|count[25], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[2]~27 , inst10|count[2]~27, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[5]~33 , inst10|count[5]~33, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[9]~41 , inst10|count[9]~41, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[16]~55 , inst10|count[16]~55, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[24]~71 , inst10|count[24]~71, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[25]~73 , inst10|count[25]~73, YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~3 , inst10|second~3, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[1]~2 , inst8|count[1]~2, YL_7SegmentDecoder, 1 +instance = comp, \inst8|op_1~0 , inst8|op_1~0, YL_7SegmentDecoder, 1 +instance = comp, \inst8|op_1~1 , inst8|op_1~1, YL_7SegmentDecoder, 1 +instance = comp, \inst_12|a~13 , inst_12|a~13, YL_7SegmentDecoder, 1 +instance = comp, \inst11|op_1~0 , inst11|op_1~0, YL_7SegmentDecoder, 1 +instance = comp, \clk~I , clk, YL_7SegmentDecoder, 1 +instance = comp, \clk~clkctrl , clk~clkctrl, YL_7SegmentDecoder, 1 +instance = comp, \clear~I , clear, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[0]~75 , inst10|count[0]~75, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[0] , inst10|count[0], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[1]~25 , inst10|count[1]~25, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[3]~29 , inst10|count[3]~29, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[4]~31 , inst10|count[4]~31, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[12]~47 , inst10|count[12]~47, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[12] , inst10|count[12], YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~4 , inst10|second~4, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[7]~37 , inst10|count[7]~37, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[7] , inst10|count[7], YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~2 , inst10|second~2, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[1] , inst10|count[1], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[3] , inst10|count[3], YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~1 , inst10|second~1, YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~5 , inst10|second~5, YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~9 , inst10|second~9, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[4] , inst10|count[4], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[6]~35 , inst10|count[6]~35, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[6] , inst10|count[6], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[8]~39 , inst10|count[8]~39, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[8] , inst10|count[8], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[10]~43 , inst10|count[10]~43, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[10] , inst10|count[10], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[11]~45 , inst10|count[11]~45, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[11] , inst10|count[11], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[13]~49 , inst10|count[13]~49, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[13] , inst10|count[13], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[14]~51 , inst10|count[14]~51, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[14] , inst10|count[14], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[15]~53 , inst10|count[15]~53, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[15] , inst10|count[15], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[17]~57 , inst10|count[17]~57, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[17] , inst10|count[17], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[18]~59 , inst10|count[18]~59, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[18] , inst10|count[18], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[19]~61 , inst10|count[19]~61, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[19] , inst10|count[19], YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~6 , inst10|second~6, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[20]~63 , inst10|count[20]~63, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[21]~65 , inst10|count[21]~65, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[21] , inst10|count[21], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[22]~67 , inst10|count[22]~67, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[23]~69 , inst10|count[23]~69, YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[23] , inst10|count[23], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[24] , inst10|count[24], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[20] , inst10|count[20], YL_7SegmentDecoder, 1 +instance = comp, \inst10|count[22] , inst10|count[22], YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~7 , inst10|second~7, YL_7SegmentDecoder, 1 +instance = comp, \inst10|second~8 , inst10|second~8, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[1]~1 , inst8|count[1]~1, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[3]~6 , inst8|count[3]~6, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[3] , inst8|count[3], YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[1]~4 , inst8|count[1]~4, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[1] , inst8|count[1], YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[0]~0 , inst8|count[0]~0, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[0] , inst8|count[0], YL_7SegmentDecoder, 1 +instance = comp, \inst_|a~13 , inst_|a~13, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[1]~3 , inst8|count[1]~3, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[2]~5 , inst8|count[2]~5, YL_7SegmentDecoder, 1 +instance = comp, \inst8|count[2] , inst8|count[2], YL_7SegmentDecoder, 1 +instance = comp, \inst_|a~12 , inst_|a~12, YL_7SegmentDecoder, 1 +instance = comp, \inst_|b~3 , inst_|b~3, YL_7SegmentDecoder, 1 +instance = comp, \inst_|c~1 , inst_|c~1, YL_7SegmentDecoder, 1 +instance = comp, \inst_|d~0 , inst_|d~0, YL_7SegmentDecoder, 1 +instance = comp, \inst_|e~0 , inst_|e~0, YL_7SegmentDecoder, 1 +instance = comp, \inst_|f~0 , inst_|f~0, YL_7SegmentDecoder, 1 +instance = comp, \inst_|g~0 , inst_|g~0, YL_7SegmentDecoder, 1 +instance = comp, \ent~I , ent, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[1]~1 , inst11|count[1]~1, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[1]~2 , inst11|count[1]~2, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[3]~8 , inst11|count[3]~8, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[3] , inst11|count[3], YL_7SegmentDecoder, 1 +instance = comp, \inst11|_~0 , inst11|_~0, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[0]~0 , inst11|count[0]~0, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[0] , inst11|count[0], YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[2]~7 , inst11|count[2]~7, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[2] , inst11|count[2], YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[1]~3 , inst11|count[1]~3, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[1]~4 , inst11|count[1]~4, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[1]~5 , inst11|count[1]~5, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[1]~6 , inst11|count[1]~6, YL_7SegmentDecoder, 1 +instance = comp, \inst11|count[1] , inst11|count[1], YL_7SegmentDecoder, 1 +instance = comp, \inst_12|a~12 , inst_12|a~12, YL_7SegmentDecoder, 1 +instance = comp, \inst_12|b~3 , inst_12|b~3, YL_7SegmentDecoder, 1 +instance = comp, \inst_12|c~1 , inst_12|c~1, YL_7SegmentDecoder, 1 +instance = comp, \inst_12|d~0 , inst_12|d~0, YL_7SegmentDecoder, 1 +instance = comp, \inst_12|e~0 , inst_12|e~0, YL_7SegmentDecoder, 1 +instance = comp, \inst_12|f~0 , inst_12|f~0, YL_7SegmentDecoder, 1 +instance = comp, \inst_12|g~0 , inst_12|g~0, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_A~I , OUTPUT_A, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_B~I , OUTPUT_B, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_C~I , OUTPUT_C, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_D~I , OUTPUT_D, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_E~I , OUTPUT_E, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_F~I , OUTPUT_F, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_G~I , OUTPUT_G, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_A1~I , OUTPUT_A1, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_B2~I , OUTPUT_B2, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_C3~I , OUTPUT_C3, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_D4~I , OUTPUT_D4, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_E5~I , OUTPUT_E5, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_F6~I , OUTPUT_F6, YL_7SegmentDecoder, 1 +instance = comp, \OUTPUT_G7~I , OUTPUT_G7, YL_7SegmentDecoder, 1 diff --git a/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v.sdo b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v.sdo new file mode 100644 index 0000000..c4b8617 --- /dev/null +++ b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v.sdo @@ -0,0 +1,1797 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "YL_7SegmentDecoder") + (DATE "05/03/2020 22:06:52") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (386:386:386)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[5\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (392:392:392)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[9\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (393:393:393)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[16\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (390:390:390)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[24\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (605:605:605)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[25\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (386:386:386)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH cin combout (458:458:458) (458:458:458)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~3) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (398:398:398)) + (PORT datab (371:371:371) (371:371:371)) + (PORT datac (590:590:590) (590:590:590)) + (PORT datad (367:367:367) (367:367:367)) + (IOPATH dataa combout (455:455:455) (455:455:455)) + (IOPATH datab combout (450:450:450) (450:450:450)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (2796:2796:2796) (2796:2796:2796)) + (PORT datac (2666:2666:2666) (2666:2666:2666)) + (IOPATH datab combout (461:461:461) (461:461:461)) + (IOPATH datac combout (322:322:322) (322:322:322)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (630:630:630)) + (PORT datac (846:846:846) (846:846:846)) + (PORT datad (693:693:693) (693:693:693)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|op_1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (619:619:619)) + (PORT datab (841:841:841) (841:841:841)) + (PORT datac (556:556:556) (556:556:556)) + (PORT datad (691:691:691) (691:691:691)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|a\~13) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (728:728:728)) + (PORT datac (699:699:699) (699:699:699)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datac combout (322:322:322) (322:322:322)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (721:721:721)) + (PORT datab (711:711:711) (711:711:711)) + (PORT datac (717:717:717) (717:717:717)) + (PORT datad (705:705:705) (705:705:705)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE clk\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE clk\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (238:238:238) (238:238:238)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE clk\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (279:279:279) (279:279:279)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (239:239:239) (239:239:239)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (55:55:55)) + (HOLD d (posedge clk) (110:110:110)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE clear\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1036:1036:1036) (1036:1036:1036)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[0\]\~75) + (DELAY + (ABSOLUTE + (IOPATH datac combout (358:358:358) (358:358:358)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (614:614:614)) + (PORT datab (374:374:374) (374:374:374)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[3\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (386:386:386)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (372:372:372)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (596:596:596) (596:596:596)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (174:174:174) (174:174:174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[12\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (597:597:597)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (609:609:609) (609:609:609)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (161:161:161) (161:161:161)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT sdata (1248:1248:1248) (1248:1248:1248)) + (PORT sclr (1335:1335:1335) (1335:1335:1335)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD sclr (posedge clk) (286:286:286)) + (HOLD sdata (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~4) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (391:391:391)) + (PORT datab (926:926:926) (926:926:926)) + (PORT datad (1189:1189:1189) (1189:1189:1189)) + (IOPATH dataa combout (455:455:455) (455:455:455)) + (IOPATH datab combout (450:450:450) (450:450:450)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[7\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (393:393:393)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~2) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (400:400:400)) + (PORT datab (375:375:375) (375:375:375)) + (PORT datac (384:384:384) (384:384:384)) + (PORT datad (364:364:364) (364:364:364)) + (IOPATH dataa combout (455:455:455) (455:455:455)) + (IOPATH datab combout (450:450:450) (450:450:450)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~1) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (387:387:387)) + (PORT datab (379:379:379) (379:379:379)) + (PORT datac (376:376:376) (376:376:376)) + (PORT datad (365:365:365) (365:365:365)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (461:461:461) (461:461:461)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~5) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (551:551:551)) + (PORT datab (306:306:306) (306:306:306)) + (PORT datac (561:561:561) (561:561:561)) + (PORT datad (531:531:531) (531:531:531)) + (IOPATH dataa combout (512:512:512) (512:512:512)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~9) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (336:336:336)) + (PORT datad (1106:1106:1106) (1106:1106:1106)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[6\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (363:363:363)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[8\]\~39) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (368:368:368)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[10\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (368:368:368)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[11\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (368:368:368)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1582:1582:1582) (1582:1582:1582)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1098:1098:1098) (1098:1098:1098)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[13\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (360:360:360)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[14\]\~51) + (DELAY + (ABSOLUTE + (PORT datab (1196:1196:1196) (1196:1196:1196)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT sdata (1302:1302:1302) (1302:1302:1302)) + (PORT sclr (1335:1335:1335) (1335:1335:1335)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD sclr (posedge clk) (286:286:286)) + (HOLD sdata (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[15\]\~53) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (368:368:368)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[17\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (605:605:605)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[18\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (395:395:395)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[19\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (391:391:391)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~6) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (393:393:393)) + (PORT datab (370:370:370) (370:370:370)) + (PORT datac (588:588:588) (588:588:588)) + (PORT datad (369:369:369) (369:369:369)) + (IOPATH dataa combout (455:455:455) (455:455:455)) + (IOPATH datab combout (450:450:450) (450:450:450)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[20\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (554:554:554)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (620:620:620) (620:620:620)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (174:174:174) (174:174:174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[21\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (587:587:587) (587:587:587)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[22\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (603:603:603)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[23\]\~69) + (DELAY + (ABSOLUTE + (PORT datab (587:587:587) (587:587:587)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1574:1574:1574) (1574:1574:1574)) + (PORT datain (96:96:96) (96:96:96)) + (PORT sclr (1426:1426:1426) (1426:1426:1426)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD sclr (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~7) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (393:393:393)) + (PORT datab (370:370:370) (370:370:370)) + (PORT datac (378:378:378) (378:378:378)) + (PORT datad (356:356:356) (356:356:356)) + (IOPATH dataa combout (455:455:455) (455:455:455)) + (IOPATH datab combout (450:450:450) (450:450:450)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~8) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (387:387:387)) + (PORT datab (294:294:294) (294:294:294)) + (PORT datac (590:590:590) (590:590:590)) + (PORT datad (289:289:289) (289:289:289)) + (IOPATH dataa combout (449:449:449) (449:449:449)) + (IOPATH datab combout (477:477:477) (477:477:477)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (3043:3043:3043) (3043:3043:3043)) + (PORT datab (3317:3317:3317) (3317:3317:3317)) + (PORT datac (935:935:935) (935:935:935)) + (PORT datad (332:332:332) (332:332:332)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (461:461:461) (461:461:461)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1541:1541:1541)) + (PORT datab (305:305:305) (305:305:305)) + (PORT datad (316:316:316) (316:316:316)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (385:385:385)) + (PORT datab (305:305:305) (305:305:305)) + (PORT datad (313:313:313) (313:313:313)) + (IOPATH dataa combout (541:541:541) (541:541:541)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3039:3039:3039) (3039:3039:3039)) + (PORT datab (3315:3315:3315) (3315:3315:3315)) + (PORT datad (808:808:808) (808:808:808)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (461:461:461) (461:461:461)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|a\~13) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (630:630:630)) + (PORT datab (554:554:554) (554:554:554)) + (PORT datac (847:847:847) (847:847:847)) + (PORT datad (693:693:693) (693:693:693)) + (IOPATH dataa combout (449:449:449) (449:449:449)) + (IOPATH datab combout (485:485:485) (485:485:485)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (812:812:812)) + (PORT datab (817:817:817) (817:817:817)) + (PORT datac (934:934:934) (934:934:934)) + (PORT datad (331:331:331) (331:331:331)) + (IOPATH dataa combout (513:513:513) (513:513:513)) + (IOPATH datab combout (427:427:427) (427:427:427)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (549:549:549)) + (PORT datab (305:305:305) (305:305:305)) + (PORT datad (313:313:313) (313:313:313)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1281:1281:1281)) + (PORT datab (1250:1250:1250) (1250:1250:1250)) + (PORT datac (1272:1272:1272) (1272:1272:1272)) + (PORT datad (1009:1009:1009) (1009:1009:1009)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (485:485:485) (485:485:485)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1278:1278:1278)) + (PORT datab (1247:1247:1247) (1247:1247:1247)) + (PORT datac (1269:1269:1269) (1269:1269:1269)) + (PORT datad (1006:1006:1006) (1006:1006:1006)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1280:1280:1280)) + (PORT datab (1245:1245:1245) (1245:1245:1245)) + (PORT datac (1268:1268:1268) (1268:1268:1268)) + (PORT datad (1005:1005:1005) (1005:1005:1005)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1280:1280:1280)) + (PORT datab (1249:1249:1249) (1249:1249:1249)) + (PORT datac (1271:1271:1271) (1271:1271:1271)) + (PORT datad (1008:1008:1008) (1008:1008:1008)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|e\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1279:1279:1279)) + (PORT datab (1246:1246:1246) (1246:1246:1246)) + (PORT datac (1268:1268:1268) (1268:1268:1268)) + (PORT datad (1005:1005:1005) (1005:1005:1005)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (483:483:483) (483:483:483)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1282:1282:1282)) + (PORT datab (1253:1253:1253) (1253:1253:1253)) + (PORT datac (1275:1275:1275) (1275:1275:1275)) + (PORT datad (1012:1012:1012) (1012:1012:1012)) + (IOPATH dataa combout (513:513:513) (513:513:513)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1281:1281:1281)) + (PORT datab (1252:1252:1252) (1252:1252:1252)) + (PORT datac (1273:1273:1273) (1273:1273:1273)) + (PORT datad (1010:1010:1010) (1010:1010:1010)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (319:319:319) (319:319:319)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE ent\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (2665:2665:2665) (2665:2665:2665)) + (PORT datad (294:294:294) (294:294:294)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (3303:3303:3303) (3303:3303:3303)) + (PORT datab (334:334:334) (334:334:334)) + (PORT datac (936:936:936) (936:936:936)) + (PORT datad (517:517:517) (517:517:517)) + (IOPATH dataa combout (455:455:455) (455:455:455)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1485:1485:1485)) + (PORT datab (317:317:317) (317:317:317)) + (PORT datad (307:307:307) (307:307:307)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3040:3040:3040) (3040:3040:3040)) + (PORT datab (819:819:819) (819:819:819)) + (PORT datac (938:938:938) (938:938:938)) + (PORT datad (328:328:328) (328:328:328)) + (IOPATH dataa combout (512:512:512) (512:512:512)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (3315:3315:3315) (3315:3315:3315)) + (PORT datad (308:308:308) (308:308:308)) + (IOPATH datab combout (461:461:461) (461:461:461)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (485:485:485)) + (PORT datab (317:317:317) (317:317:317)) + (PORT datad (307:307:307) (307:307:307)) + (IOPATH dataa combout (541:541:541) (541:541:541)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (722:722:722)) + (PORT datab (712:712:712) (712:712:712)) + (PORT datac (718:718:718) (718:718:718)) + (PORT datad (706:706:706) (706:706:706)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (319:319:319) (319:319:319)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (2796:2796:2796) (2796:2796:2796)) + (PORT datac (2667:2667:2667) (2667:2667:2667)) + (PORT datad (288:288:288) (288:288:288)) + (IOPATH datab combout (427:427:427) (427:427:427)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (550:550:550)) + (PORT datab (820:820:820) (820:820:820)) + (PORT datac (937:937:937) (937:937:937)) + (PORT datad (519:519:519) (519:519:519)) + (IOPATH dataa combout (512:512:512) (512:512:512)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (384:384:384)) + (PORT datab (317:317:317) (317:317:317)) + (PORT datad (306:306:306) (306:306:306)) + (IOPATH dataa combout (541:541:541) (541:541:541)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (710:710:710)) + (PORT datab (692:692:692) (692:692:692)) + (PORT datac (700:700:700) (700:700:700)) + (PORT datad (689:689:689) (689:689:689)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (720:720:720)) + (PORT datab (710:710:710) (710:710:710)) + (PORT datac (715:715:715) (715:715:715)) + (PORT datad (703:703:703) (703:703:703)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (971:971:971)) + (PORT datab (1001:1001:1001) (1001:1001:1001)) + (PORT datac (1192:1192:1192) (1192:1192:1192)) + (PORT datad (991:991:991) (991:991:991)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (973:973:973)) + (PORT datab (997:997:997) (997:997:997)) + (PORT datac (1196:1196:1196) (1196:1196:1196)) + (PORT datad (988:988:988) (988:988:988)) + (IOPATH dataa combout (512:512:512) (512:512:512)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|e\~0) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (722:722:722)) + (PORT datab (712:712:712) (712:712:712)) + (PORT datac (718:718:718) (718:718:718)) + (PORT datad (706:706:706) (706:706:706)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (975:975:975)) + (PORT datab (996:996:996) (996:996:996)) + (PORT datac (1196:1196:1196) (1196:1196:1196)) + (PORT datad (987:987:987) (987:987:987)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (709:709:709)) + (PORT datab (702:702:702) (702:702:702)) + (PORT datac (708:708:708) (708:708:708)) + (PORT datad (695:695:695) (695:695:695)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (863:863:863) (863:863:863)) + (IOPATH datain padio (2810:2810:2810) (2810:2810:2810)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (871:871:871) (871:871:871)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (748:748:748) (748:748:748)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (857:857:857) (857:857:857)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2830:2830:2830) (2830:2830:2830)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (741:741:741) (741:741:741)) + (IOPATH datain padio (2860:2860:2860) (2860:2860:2860)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E5\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (521:521:521) (521:521:521)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F6\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G7\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) +) diff --git a/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v_fast.sdo b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v_fast.sdo new file mode 100644 index 0000000..4c9b804 --- /dev/null +++ b/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v_fast.sdo @@ -0,0 +1,1797 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "YL_7SegmentDecoder") + (DATE "05/03/2020 22:06:52") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (163:163:163) (163:163:163)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[5\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (165:165:165) (165:165:165)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[9\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (167:167:167)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[16\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (164:164:164)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[24\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (241:241:241)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[25\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (163:163:163) (163:163:163)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH cin combout (170:170:170) (170:170:170)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~3) + (DELAY + (ABSOLUTE + (PORT dataa (172:172:172) (172:172:172)) + (PORT datab (159:159:159) (159:159:159)) + (PORT datac (233:233:233) (233:233:233)) + (PORT datad (158:158:158) (158:158:158)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1192:1192:1192) (1192:1192:1192)) + (PORT datac (1141:1141:1141) (1141:1141:1141)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (133:133:133) (133:133:133)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (252:252:252)) + (PORT datac (326:326:326) (326:326:326)) + (PORT datad (291:291:291) (291:291:291)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|op_1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (247:247:247)) + (PORT datab (323:323:323) (323:323:323)) + (PORT datac (235:235:235) (235:235:235)) + (PORT datad (289:289:289) (289:289:289)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|a\~13) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (311:311:311)) + (PORT datac (294:294:294) (294:294:294)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datac combout (133:133:133) (133:133:133)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (307:307:307)) + (PORT datab (302:302:302) (302:302:302)) + (PORT datac (310:310:310) (310:310:310)) + (PORT datad (301:301:301) (301:301:301)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE clk\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE clk\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (186:186:186) (186:186:186)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE clk\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (260:260:260) (260:260:260)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (33:33:33)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE clear\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (581:581:581) (581:581:581)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[0\]\~75) + (DELAY + (ABSOLUTE + (IOPATH datac combout (184:184:184) (184:184:184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (242:242:242)) + (PORT datab (161:161:161) (161:161:161)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[3\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (163:163:163) (163:163:163)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (159:159:159) (159:159:159)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (198:198:198) (198:198:198)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (94:94:94) (94:94:94)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[12\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (234:234:234)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (195:195:195) (195:195:195)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (87:87:87) (87:87:87)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT sdata (492:492:492) (492:492:492)) + (PORT sclr (564:564:564) (564:564:564)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD sclr (posedge clk) (152:152:152)) + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~4) + (DELAY + (ABSOLUTE + (PORT dataa (163:163:163) (163:163:163)) + (PORT datab (358:358:358) (358:358:358)) + (PORT datad (452:452:452) (452:452:452)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[7\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (167:167:167)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~2) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (174:174:174)) + (PORT datab (161:161:161) (161:161:161)) + (PORT datac (167:167:167) (167:167:167)) + (PORT datad (156:156:156) (156:156:156)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~1) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (164:164:164)) + (PORT datab (161:161:161) (161:161:161)) + (PORT datac (160:160:160) (160:160:160)) + (PORT datad (157:157:157) (157:157:157)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (135:135:135) (135:135:135)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (200:200:200)) + (PORT datab (115:115:115) (115:115:115)) + (PORT datac (210:210:210) (210:210:210)) + (PORT datad (193:193:193) (193:193:193)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~9) + (DELAY + (ABSOLUTE + (PORT datab (128:128:128) (128:128:128)) + (PORT datad (399:399:399) (399:399:399)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[6\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (154:154:154)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[8\]\~39) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (154:154:154)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[10\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (156:156:156) (156:156:156)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[11\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (157:157:157) (157:157:157)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1024:1024:1024)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (482:482:482) (482:482:482)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[13\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (149:149:149) (149:149:149)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[14\]\~51) + (DELAY + (ABSOLUTE + (PORT datab (457:457:457) (457:457:457)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT sdata (516:516:516) (516:516:516)) + (PORT sclr (564:564:564) (564:564:564)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD sclr (posedge clk) (152:152:152)) + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[15\]\~53) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (154:154:154)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[17\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (237:237:237)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[18\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (165:165:165) (165:165:165)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[19\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (165:165:165) (165:165:165)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~6) + (DELAY + (ABSOLUTE + (PORT dataa (168:168:168) (168:168:168)) + (PORT datab (156:156:156) (156:156:156)) + (PORT datac (232:232:232) (232:232:232)) + (PORT datad (159:159:159) (159:159:159)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[20\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (229:229:229)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (204:204:204) (204:204:204)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (94:94:94) (94:94:94)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[21\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (230:230:230) (230:230:230)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[22\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (237:237:237)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|count\[23\]\~69) + (DELAY + (ABSOLUTE + (PORT datab (231:231:231) (231:231:231)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst10\|count\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT datain (42:42:42) (42:42:42)) + (PORT sclr (604:604:604) (604:604:604)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD sclr (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~7) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (164:164:164)) + (PORT datab (156:156:156) (156:156:156)) + (PORT datac (159:159:159) (159:159:159)) + (PORT datad (149:149:149) (149:149:149)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst10\|second\~8) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (164:164:164)) + (PORT datab (106:106:106) (106:106:106)) + (PORT datac (235:235:235) (235:235:235)) + (PORT datad (104:104:104) (104:104:104)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1292:1292:1292)) + (PORT datab (1376:1376:1376) (1376:1376:1376)) + (PORT datac (359:359:359) (359:359:359)) + (PORT datad (126:126:126) (126:126:126)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (582:582:582)) + (PORT datab (112:112:112) (112:112:112)) + (PORT datad (119:119:119) (119:119:119)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (161:161:161)) + (PORT datab (112:112:112) (112:112:112)) + (PORT datad (117:117:117) (117:117:117)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1288:1288:1288)) + (PORT datab (1374:1374:1374) (1374:1374:1374)) + (PORT datad (292:292:292) (292:292:292)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|a\~13) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (253:253:253)) + (PORT datab (235:235:235) (235:235:235)) + (PORT datac (327:327:327) (327:327:327)) + (PORT datad (290:290:290) (290:290:290)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (291:291:291)) + (PORT datab (294:294:294) (294:294:294)) + (PORT datac (359:359:359) (359:359:359)) + (PORT datad (125:125:125) (125:125:125)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst8\|count\[2\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (197:197:197)) + (PORT datab (112:112:112) (112:112:112)) + (PORT datad (117:117:117) (117:117:117)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst8\|count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (500:500:500)) + (PORT datab (488:488:488) (488:488:488)) + (PORT datac (505:505:505) (505:505:505)) + (PORT datad (404:404:404) (404:404:404)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (498:498:498)) + (PORT datab (485:485:485) (485:485:485)) + (PORT datac (502:502:502) (502:502:502)) + (PORT datad (402:402:402) (402:402:402)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (499:499:499)) + (PORT datab (483:483:483) (483:483:483)) + (PORT datac (501:501:501) (501:501:501)) + (PORT datad (400:400:400) (400:400:400)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (500:500:500)) + (PORT datab (488:488:488) (488:488:488)) + (PORT datac (504:504:504) (504:504:504)) + (PORT datad (404:404:404) (404:404:404)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|e\~0) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (498:498:498)) + (PORT datab (485:485:485) (485:485:485)) + (PORT datac (501:501:501) (501:501:501)) + (PORT datad (401:401:401) (401:401:401)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (501:501:501)) + (PORT datab (491:491:491) (491:491:491)) + (PORT datac (506:506:506) (506:506:506)) + (PORT datad (406:406:406) (406:406:406)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (500:500:500)) + (PORT datab (490:490:490) (490:490:490)) + (PORT datac (506:506:506) (506:506:506)) + (PORT datad (406:406:406) (406:406:406)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE ent\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1140:1140:1140) (1140:1140:1140)) + (PORT datad (104:104:104) (104:104:104)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (79:79:79) (79:79:79)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1369:1369:1369)) + (PORT datab (126:126:126) (126:126:126)) + (PORT datac (360:360:360) (360:360:360)) + (PORT datad (184:184:184) (184:184:184)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (540:540:540)) + (PORT datab (118:118:118) (118:118:118)) + (PORT datad (115:115:115) (115:115:115)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1290:1290:1290)) + (PORT datab (296:296:296) (296:296:296)) + (PORT datac (361:361:361) (361:361:361)) + (PORT datad (123:123:123) (123:123:123)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1375:1375:1375) (1375:1375:1375)) + (PORT datad (114:114:114) (114:114:114)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (183:183:183)) + (PORT datab (118:118:118) (118:118:118)) + (PORT datad (115:115:115) (115:115:115)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (307:307:307)) + (PORT datab (303:303:303) (303:303:303)) + (PORT datac (311:311:311) (311:311:311)) + (PORT datad (302:302:302) (302:302:302)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (1193:1193:1193) (1193:1193:1193)) + (PORT datac (1141:1141:1141) (1141:1141:1141)) + (PORT datad (104:104:104) (104:104:104)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (195:195:195)) + (PORT datab (297:297:297) (297:297:297)) + (PORT datac (361:361:361) (361:361:361)) + (PORT datad (183:183:183) (183:183:183)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst11\|count\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (159:159:159)) + (PORT datab (119:119:119) (119:119:119)) + (PORT datad (114:114:114) (114:114:114)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst11\|count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1022:1022:1022) (1022:1022:1022)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (300:300:300)) + (PORT datab (287:287:287) (287:287:287)) + (PORT datac (294:294:294) (294:294:294)) + (PORT datad (286:286:286) (286:286:286)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (305:305:305)) + (PORT datab (301:301:301) (301:301:301)) + (PORT datac (308:308:308) (308:308:308)) + (PORT datad (299:299:299) (299:299:299)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (383:383:383)) + (PORT datab (406:406:406) (406:406:406)) + (PORT datac (463:463:463) (463:463:463)) + (PORT datad (403:403:403) (403:403:403)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (388:388:388)) + (PORT datab (403:403:403) (403:403:403)) + (PORT datac (467:467:467) (467:467:467)) + (PORT datad (400:400:400) (400:400:400)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|e\~0) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (307:307:307)) + (PORT datab (303:303:303) (303:303:303)) + (PORT datac (311:311:311) (311:311:311)) + (PORT datad (302:302:302) (302:302:302)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (389:389:389)) + (PORT datab (400:400:400) (400:400:400)) + (PORT datac (468:468:468) (468:468:468)) + (PORT datad (399:399:399) (399:399:399)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_12\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (298:298:298)) + (PORT datab (293:293:293) (293:293:293)) + (PORT datac (301:301:301) (301:301:301)) + (PORT datad (292:292:292) (292:292:292)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (348:348:348) (348:348:348)) + (IOPATH datain padio (1378:1378:1378) (1378:1378:1378)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (353:353:353) (353:353:353)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (293:293:293) (293:293:293)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (341:341:341) (341:341:341)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1418:1418:1418) (1418:1418:1418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1418:1418:1418) (1418:1418:1418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1418:1418:1418) (1418:1418:1418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1398:1398:1398) (1398:1398:1398)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (290:290:290) (290:290:290)) + (IOPATH datain padio (1428:1428:1428) (1428:1428:1428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E5\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (217:217:217) (217:217:217)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F6\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G7\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (216:216:216) (216:216:216)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) +) diff --git a/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.do b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.do new file mode 100644 index 0000000..d049d7d --- /dev/null +++ b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.do @@ -0,0 +1,10 @@ +onerror {quit -f} +vlib work +vlog -work work YL_7SegmentDecoder.vo +vlog -work work YL_7SegmentDecoder.vt +vsim -novopt -c -t 1ps -L cycloneii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.YL_7SegmentDecoder_vlg_vec_tst +vcd file -direction YL_7SegmentDecoder.msim.vcd +vcd add -internal YL_7SegmentDecoder_vlg_vec_tst/* +vcd add -internal YL_7SegmentDecoder_vlg_vec_tst/i1/* +add wave /* +run -all diff --git a/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.sim.vwf b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.sim.vwf new file mode 100644 index 0000000..cbf6416 --- /dev/null +++ b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.sim.vwf @@ -0,0 +1,809 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 30000.0; + SIMULATION_TIME = 30000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E5") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 26880.0; + LEVEL 1 FOR 640.0; + LEVEL 0 FOR 2480.0; + } +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1500; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 16640.0; + LEVEL 0 FOR 3840.0; + LEVEL 1 FOR 9520.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 4560.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 720.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 490.0; + } +} + +TRANSITION_LIST("OUTPUT_A1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 8640.0; + LEVEL 1 FOR 5280.0; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 2020.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + } + LEVEL 1 FOR 4080.0; + NODE + { + REPEAT = 4; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 240.0; + } + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1200.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 250.0; + } +} + +TRANSITION_LIST("OUTPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 7190.0; + LEVEL 1 FOR 2880.0; + LEVEL 0 FOR 5760.0; + LEVEL 1 FOR 5280.0; + LEVEL 0 FOR 8890.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1320.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 5160.0; + NODE + { + REPEAT = 3; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1320.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1920.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1320.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 730.0; + } +} + +TRANSITION_LIST("OUTPUT_C3") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 2870.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 19680.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 4570.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 45; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 4080.0; + NODE + { + REPEAT = 17; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 840.0; + NODE + { + REPEAT = 6; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 240.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 130.0; + } +} + +TRANSITION_LIST("OUTPUT_D4") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + NODE + { + REPEAT = 3; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + } + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 6720.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 2880.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 2020.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 10; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + LEVEL 0 FOR 360.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 3960.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + NODE + { + REPEAT = 4; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + } + LEVEL 0 FOR 960.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + } + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 10.0; + } +} + +TRANSITION_LIST("OUTPUT_E5") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 4320.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 1440.0; + } + LEVEL 0 FOR 8160.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 1440.0; + LEVEL 1 FOR 1460.0; + LEVEL 0 FOR 2020.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + NODE + { + REPEAT = 11; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + } + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 4200.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1200.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 130.0; + } +} + +TRANSITION_LIST("OUTPUT_F6") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1430.0; + LEVEL 1 FOR 4320.0; + LEVEL 0 FOR 4320.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 11040.0; + LEVEL 1 FOR 4320.0; + LEVEL 0 FOR 2040.0; + LEVEL 1 FOR 1090.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 230.0; + NODE + { + REPEAT = 11; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 240.0; + } + LEVEL 0 FOR 4440.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 600.0; + } + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 840.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 130.0; + } +} + +TRANSITION_LIST("OUTPUT_G7") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 2870.0; + LEVEL 0 FOR 7200.0; + LEVEL 1 FOR 1440.0; + LEVEL 0 FOR 9600.0; + LEVEL 1 FOR 2880.0; + LEVEL 0 FOR 2900.0; + LEVEL 1 FOR 3110.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E5"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.vo b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.vo new file mode 100644 index 0000000..df29a86 --- /dev/null +++ b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.vo @@ -0,0 +1,603 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/03/2020 17:53:55" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_7SegmentDecoder ( + OUTPUT_A, + in, + OUTPUT_B, + OUTPUT_C, + OUTPUT_D, + OUTPUT_E, + OUTPUT_F, + OUTPUT_G); +output OUTPUT_A; +input [3:0] in; +output OUTPUT_B; +output OUTPUT_C; +output OUTPUT_D; +output OUTPUT_E; +output OUTPUT_F; +output OUTPUT_G; + +// Design Ports Information +// OUTPUT_A => Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B => Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C => Location: PIN_H2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D => Location: PIN_H1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// in[0] => Location: PIN_L22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// in[1] => Location: PIN_L21, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// in[2] => Location: PIN_M22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// in[3] => Location: PIN_V12, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("YL_7SegmentDecoder_v.sdo"); +// synopsys translate_on + +wire \inst_|a~12_combout ; +wire \inst_|b~3_combout ; +wire \inst_|c~1_combout ; +wire \inst_|d~0_combout ; +wire \inst_|e~0_combout ; +wire \inst_|f~0_combout ; +wire \inst_|g~0_combout ; +wire [3:0] \in~combout ; + + +// Location: PIN_L21, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \in[1]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\in~combout [1]), + .regout(), + .differentialout(), + .linkout(), + .padio(in[1])); +// synopsys translate_off +defparam \in[1]~I .input_async_reset = "none"; +defparam \in[1]~I .input_power_up = "low"; +defparam \in[1]~I .input_register_mode = "none"; +defparam \in[1]~I .input_sync_reset = "none"; +defparam \in[1]~I .oe_async_reset = "none"; +defparam \in[1]~I .oe_power_up = "low"; +defparam \in[1]~I .oe_register_mode = "none"; +defparam \in[1]~I .oe_sync_reset = "none"; +defparam \in[1]~I .operation_mode = "input"; +defparam \in[1]~I .output_async_reset = "none"; +defparam \in[1]~I .output_power_up = "low"; +defparam \in[1]~I .output_register_mode = "none"; +defparam \in[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V12, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \in[3]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\in~combout [3]), + .regout(), + .differentialout(), + .linkout(), + .padio(in[3])); +// synopsys translate_off +defparam \in[3]~I .input_async_reset = "none"; +defparam \in[3]~I .input_power_up = "low"; +defparam \in[3]~I .input_register_mode = "none"; +defparam \in[3]~I .input_sync_reset = "none"; +defparam \in[3]~I .oe_async_reset = "none"; +defparam \in[3]~I .oe_power_up = "low"; +defparam \in[3]~I .oe_register_mode = "none"; +defparam \in[3]~I .oe_sync_reset = "none"; +defparam \in[3]~I .operation_mode = "input"; +defparam \in[3]~I .output_async_reset = "none"; +defparam \in[3]~I .output_power_up = "low"; +defparam \in[3]~I .output_register_mode = "none"; +defparam \in[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_L22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \in[0]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\in~combout [0]), + .regout(), + .differentialout(), + .linkout(), + .padio(in[0])); +// synopsys translate_off +defparam \in[0]~I .input_async_reset = "none"; +defparam \in[0]~I .input_power_up = "low"; +defparam \in[0]~I .input_register_mode = "none"; +defparam \in[0]~I .input_sync_reset = "none"; +defparam \in[0]~I .oe_async_reset = "none"; +defparam \in[0]~I .oe_power_up = "low"; +defparam \in[0]~I .oe_register_mode = "none"; +defparam \in[0]~I .oe_sync_reset = "none"; +defparam \in[0]~I .operation_mode = "input"; +defparam \in[0]~I .output_async_reset = "none"; +defparam \in[0]~I .output_power_up = "low"; +defparam \in[0]~I .output_register_mode = "none"; +defparam \in[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_M22, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \in[2]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\in~combout [2]), + .regout(), + .differentialout(), + .linkout(), + .padio(in[2])); +// synopsys translate_off +defparam \in[2]~I .input_async_reset = "none"; +defparam \in[2]~I .input_power_up = "low"; +defparam \in[2]~I .input_register_mode = "none"; +defparam \in[2]~I .input_sync_reset = "none"; +defparam \in[2]~I .oe_async_reset = "none"; +defparam \in[2]~I .oe_power_up = "low"; +defparam \in[2]~I .oe_register_mode = "none"; +defparam \in[2]~I .oe_sync_reset = "none"; +defparam \in[2]~I .operation_mode = "input"; +defparam \in[2]~I .output_async_reset = "none"; +defparam \in[2]~I .output_power_up = "low"; +defparam \in[2]~I .output_register_mode = "none"; +defparam \in[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y18_N16 +cycloneii_lcell_comb \inst_|a~12 ( +// Equation(s): +// \inst_|a~12_combout = (\in~combout [3] & (\in~combout [0] & (\in~combout [1] $ (\in~combout [2])))) # (!\in~combout [3] & (!\in~combout [1] & (\in~combout [0] $ (\in~combout [2])))) + + .dataa(\in~combout [1]), + .datab(\in~combout [3]), + .datac(\in~combout [0]), + .datad(\in~combout [2]), + .cin(gnd), + .combout(\inst_|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|a~12 .lut_mask = 16'h4190; +defparam \inst_|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y18_N26 +cycloneii_lcell_comb \inst_|b~3 ( +// Equation(s): +// \inst_|b~3_combout = (\in~combout [1] & ((\in~combout [0] & (\in~combout [3])) # (!\in~combout [0] & ((\in~combout [2]))))) # (!\in~combout [1] & (\in~combout [2] & (\in~combout [3] $ (\in~combout [0])))) + + .dataa(\in~combout [1]), + .datab(\in~combout [3]), + .datac(\in~combout [0]), + .datad(\in~combout [2]), + .cin(gnd), + .combout(\inst_|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|b~3 .lut_mask = 16'h9E80; +defparam \inst_|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y18_N28 +cycloneii_lcell_comb \inst_|c~1 ( +// Equation(s): +// \inst_|c~1_combout = (\in~combout [3] & (\in~combout [2] & ((\in~combout [1]) # (!\in~combout [0])))) # (!\in~combout [3] & (\in~combout [1] & (!\in~combout [0] & !\in~combout [2]))) + + .dataa(\in~combout [1]), + .datab(\in~combout [3]), + .datac(\in~combout [0]), + .datad(\in~combout [2]), + .cin(gnd), + .combout(\inst_|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|c~1 .lut_mask = 16'h8C02; +defparam \inst_|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y18_N6 +cycloneii_lcell_comb \inst_|d~0 ( +// Equation(s): +// \inst_|d~0_combout = (\in~combout [1] & ((\in~combout [0] & ((\in~combout [2]))) # (!\in~combout [0] & (\in~combout [3] & !\in~combout [2])))) # (!\in~combout [1] & (!\in~combout [3] & (\in~combout [0] $ (\in~combout [2])))) + + .dataa(\in~combout [1]), + .datab(\in~combout [3]), + .datac(\in~combout [0]), + .datad(\in~combout [2]), + .cin(gnd), + .combout(\inst_|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|d~0 .lut_mask = 16'hA118; +defparam \inst_|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y18_N8 +cycloneii_lcell_comb \inst_|e~0 ( +// Equation(s): +// \inst_|e~0_combout = (\in~combout [1] & (!\in~combout [3] & (\in~combout [0]))) # (!\in~combout [1] & ((\in~combout [2] & (!\in~combout [3])) # (!\in~combout [2] & ((\in~combout [0]))))) + + .dataa(\in~combout [1]), + .datab(\in~combout [3]), + .datac(\in~combout [0]), + .datad(\in~combout [2]), + .cin(gnd), + .combout(\inst_|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|e~0 .lut_mask = 16'h3170; +defparam \inst_|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y18_N10 +cycloneii_lcell_comb \inst_|f~0 ( +// Equation(s): +// \inst_|f~0_combout = (\in~combout [1] & (!\in~combout [3] & ((\in~combout [0]) # (!\in~combout [2])))) # (!\in~combout [1] & (\in~combout [0] & (\in~combout [3] $ (!\in~combout [2])))) + + .dataa(\in~combout [1]), + .datab(\in~combout [3]), + .datac(\in~combout [0]), + .datad(\in~combout [2]), + .cin(gnd), + .combout(\inst_|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|f~0 .lut_mask = 16'h6032; +defparam \inst_|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y18_N12 +cycloneii_lcell_comb \inst_|g~0 ( +// Equation(s): +// \inst_|g~0_combout = (\in~combout [0] & ((\in~combout [3]) # (\in~combout [1] $ (\in~combout [2])))) # (!\in~combout [0] & ((\in~combout [1]) # (\in~combout [3] $ (\in~combout [2])))) + + .dataa(\in~combout [1]), + .datab(\in~combout [3]), + .datac(\in~combout [0]), + .datad(\in~combout [2]), + .cin(gnd), + .combout(\inst_|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst_|g~0 .lut_mask = 16'hDBEE; +defparam \inst_|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A~I ( + .datain(\inst_|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A)); +// synopsys translate_off +defparam \OUTPUT_A~I .input_async_reset = "none"; +defparam \OUTPUT_A~I .input_power_up = "low"; +defparam \OUTPUT_A~I .input_register_mode = "none"; +defparam \OUTPUT_A~I .input_sync_reset = "none"; +defparam \OUTPUT_A~I .oe_async_reset = "none"; +defparam \OUTPUT_A~I .oe_power_up = "low"; +defparam \OUTPUT_A~I .oe_register_mode = "none"; +defparam \OUTPUT_A~I .oe_sync_reset = "none"; +defparam \OUTPUT_A~I .operation_mode = "output"; +defparam \OUTPUT_A~I .output_async_reset = "none"; +defparam \OUTPUT_A~I .output_power_up = "low"; +defparam \OUTPUT_A~I .output_register_mode = "none"; +defparam \OUTPUT_A~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B~I ( + .datain(\inst_|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B)); +// synopsys translate_off +defparam \OUTPUT_B~I .input_async_reset = "none"; +defparam \OUTPUT_B~I .input_power_up = "low"; +defparam \OUTPUT_B~I .input_register_mode = "none"; +defparam \OUTPUT_B~I .input_sync_reset = "none"; +defparam \OUTPUT_B~I .oe_async_reset = "none"; +defparam \OUTPUT_B~I .oe_power_up = "low"; +defparam \OUTPUT_B~I .oe_register_mode = "none"; +defparam \OUTPUT_B~I .oe_sync_reset = "none"; +defparam \OUTPUT_B~I .operation_mode = "output"; +defparam \OUTPUT_B~I .output_async_reset = "none"; +defparam \OUTPUT_B~I .output_power_up = "low"; +defparam \OUTPUT_B~I .output_register_mode = "none"; +defparam \OUTPUT_B~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C~I ( + .datain(\inst_|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C)); +// synopsys translate_off +defparam \OUTPUT_C~I .input_async_reset = "none"; +defparam \OUTPUT_C~I .input_power_up = "low"; +defparam \OUTPUT_C~I .input_register_mode = "none"; +defparam \OUTPUT_C~I .input_sync_reset = "none"; +defparam \OUTPUT_C~I .oe_async_reset = "none"; +defparam \OUTPUT_C~I .oe_power_up = "low"; +defparam \OUTPUT_C~I .oe_register_mode = "none"; +defparam \OUTPUT_C~I .oe_sync_reset = "none"; +defparam \OUTPUT_C~I .operation_mode = "output"; +defparam \OUTPUT_C~I .output_async_reset = "none"; +defparam \OUTPUT_C~I .output_power_up = "low"; +defparam \OUTPUT_C~I .output_register_mode = "none"; +defparam \OUTPUT_C~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D~I ( + .datain(\inst_|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D)); +// synopsys translate_off +defparam \OUTPUT_D~I .input_async_reset = "none"; +defparam \OUTPUT_D~I .input_power_up = "low"; +defparam \OUTPUT_D~I .input_register_mode = "none"; +defparam \OUTPUT_D~I .input_sync_reset = "none"; +defparam \OUTPUT_D~I .oe_async_reset = "none"; +defparam \OUTPUT_D~I .oe_power_up = "low"; +defparam \OUTPUT_D~I .oe_register_mode = "none"; +defparam \OUTPUT_D~I .oe_sync_reset = "none"; +defparam \OUTPUT_D~I .operation_mode = "output"; +defparam \OUTPUT_D~I .output_async_reset = "none"; +defparam \OUTPUT_D~I .output_power_up = "low"; +defparam \OUTPUT_D~I .output_register_mode = "none"; +defparam \OUTPUT_D~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E~I ( + .datain(\inst_|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E)); +// synopsys translate_off +defparam \OUTPUT_E~I .input_async_reset = "none"; +defparam \OUTPUT_E~I .input_power_up = "low"; +defparam \OUTPUT_E~I .input_register_mode = "none"; +defparam \OUTPUT_E~I .input_sync_reset = "none"; +defparam \OUTPUT_E~I .oe_async_reset = "none"; +defparam \OUTPUT_E~I .oe_power_up = "low"; +defparam \OUTPUT_E~I .oe_register_mode = "none"; +defparam \OUTPUT_E~I .oe_sync_reset = "none"; +defparam \OUTPUT_E~I .operation_mode = "output"; +defparam \OUTPUT_E~I .output_async_reset = "none"; +defparam \OUTPUT_E~I .output_power_up = "low"; +defparam \OUTPUT_E~I .output_register_mode = "none"; +defparam \OUTPUT_E~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F~I ( + .datain(\inst_|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F)); +// synopsys translate_off +defparam \OUTPUT_F~I .input_async_reset = "none"; +defparam \OUTPUT_F~I .input_power_up = "low"; +defparam \OUTPUT_F~I .input_register_mode = "none"; +defparam \OUTPUT_F~I .input_sync_reset = "none"; +defparam \OUTPUT_F~I .oe_async_reset = "none"; +defparam \OUTPUT_F~I .oe_power_up = "low"; +defparam \OUTPUT_F~I .oe_register_mode = "none"; +defparam \OUTPUT_F~I .oe_sync_reset = "none"; +defparam \OUTPUT_F~I .operation_mode = "output"; +defparam \OUTPUT_F~I .output_async_reset = "none"; +defparam \OUTPUT_F~I .output_power_up = "low"; +defparam \OUTPUT_F~I .output_register_mode = "none"; +defparam \OUTPUT_F~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G~I ( + .datain(!\inst_|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G)); +// synopsys translate_off +defparam \OUTPUT_G~I .input_async_reset = "none"; +defparam \OUTPUT_G~I .input_power_up = "low"; +defparam \OUTPUT_G~I .input_register_mode = "none"; +defparam \OUTPUT_G~I .input_sync_reset = "none"; +defparam \OUTPUT_G~I .oe_async_reset = "none"; +defparam \OUTPUT_G~I .oe_power_up = "low"; +defparam \OUTPUT_G~I .oe_register_mode = "none"; +defparam \OUTPUT_G~I .oe_sync_reset = "none"; +defparam \OUTPUT_G~I .operation_mode = "output"; +defparam \OUTPUT_G~I .output_async_reset = "none"; +defparam \OUTPUT_G~I .output_power_up = "low"; +defparam \OUTPUT_G~I .output_register_mode = "none"; +defparam \OUTPUT_G~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.vt b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.vt new file mode 100644 index 0000000..c25c29f --- /dev/null +++ b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder.vt @@ -0,0 +1,394 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "05/03/2020 17:53:54" + +// Verilog Self-Checking Test Bench (with test vectors) for design : YL_7SegmentDecoder +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module YL_7SegmentDecoder_vlg_sample_tst( + in, + sampler_tx +); +input [3:0] in; +output sampler_tx; + +reg sample; +time current_time; +always @(in) + +begin + if ($realtime > 0) + begin + if ($realtime == 0 || $realtime != current_time) + begin + if (sample === 1'bx) + sample = 0; + else + sample = ~sample; + end + current_time = $realtime; + end +end + +assign sampler_tx = sample; +endmodule + +module YL_7SegmentDecoder_vlg_check_tst ( + OUTPUT_A, + OUTPUT_B, + OUTPUT_C, + OUTPUT_D, + OUTPUT_E, + OUTPUT_F, + OUTPUT_G, + sampler_rx +); +input OUTPUT_A; +input OUTPUT_B; +input OUTPUT_C; +input OUTPUT_D; +input OUTPUT_E; +input OUTPUT_F; +input OUTPUT_G; +input sampler_rx; + +reg OUTPUT_A_expected; +reg OUTPUT_B_expected; +reg OUTPUT_C_expected; +reg OUTPUT_D_expected; +reg OUTPUT_E_expected; +reg OUTPUT_F_expected; +reg OUTPUT_G_expected; + +reg OUTPUT_A_prev; +reg OUTPUT_B_prev; +reg OUTPUT_C_prev; +reg OUTPUT_D_prev; +reg OUTPUT_E_prev; +reg OUTPUT_F_prev; +reg OUTPUT_G_prev; + +reg OUTPUT_A_expected_prev; +reg OUTPUT_B_expected_prev; +reg OUTPUT_C_expected_prev; +reg OUTPUT_D_expected_prev; +reg OUTPUT_E_expected_prev; +reg OUTPUT_F_expected_prev; +reg OUTPUT_G_expected_prev; + +reg last_OUTPUT_A_exp; +reg last_OUTPUT_B_exp; +reg last_OUTPUT_C_exp; +reg last_OUTPUT_D_exp; +reg last_OUTPUT_E_exp; +reg last_OUTPUT_F_exp; +reg last_OUTPUT_G_exp; + +reg trigger; + +integer i; +integer nummismatches; + +reg [1:7] on_first_change ; + + +initial +begin +trigger = 0; +i = 0; +nummismatches = 0; +on_first_change = 7'b1; +end + +// update real /o prevs + +always @(trigger) +begin + OUTPUT_A_prev = OUTPUT_A; + OUTPUT_B_prev = OUTPUT_B; + OUTPUT_C_prev = OUTPUT_C; + OUTPUT_D_prev = OUTPUT_D; + OUTPUT_E_prev = OUTPUT_E; + OUTPUT_F_prev = OUTPUT_F; + OUTPUT_G_prev = OUTPUT_G; +end + +// update expected /o prevs + +always @(trigger) +begin + OUTPUT_A_expected_prev = OUTPUT_A_expected; + OUTPUT_B_expected_prev = OUTPUT_B_expected; + OUTPUT_C_expected_prev = OUTPUT_C_expected; + OUTPUT_D_expected_prev = OUTPUT_D_expected; + OUTPUT_E_expected_prev = OUTPUT_E_expected; + OUTPUT_F_expected_prev = OUTPUT_F_expected; + OUTPUT_G_expected_prev = OUTPUT_G_expected; +end + + + +// expected OUTPUT_A +initial +begin + OUTPUT_A_expected = 1'bX; +end + +// expected OUTPUT_B +initial +begin + OUTPUT_B_expected = 1'bX; +end + +// expected OUTPUT_C +initial +begin + OUTPUT_C_expected = 1'bX; +end + +// expected OUTPUT_D +initial +begin + OUTPUT_D_expected = 1'bX; +end + +// expected OUTPUT_E +initial +begin + OUTPUT_E_expected = 1'bX; +end + +// expected OUTPUT_F +initial +begin + OUTPUT_F_expected = 1'bX; +end + +// expected OUTPUT_G +initial +begin + OUTPUT_G_expected = 1'bX; +end +// generate trigger +always @(OUTPUT_A_expected or OUTPUT_A or OUTPUT_B_expected or OUTPUT_B or OUTPUT_C_expected or OUTPUT_C or OUTPUT_D_expected or OUTPUT_D or OUTPUT_E_expected or OUTPUT_E or OUTPUT_F_expected or OUTPUT_F or OUTPUT_G_expected or OUTPUT_G) +begin + trigger <= ~trigger; +end + +always @(posedge sampler_rx or negedge sampler_rx) +begin +`ifdef debug_tbench + $display("Scanning pattern %d @time = %t",i,$realtime ); + i = i + 1; + $display("| expected OUTPUT_A = %b | expected OUTPUT_B = %b | expected OUTPUT_C = %b | expected OUTPUT_D = %b | expected OUTPUT_E = %b | expected OUTPUT_F = %b | expected OUTPUT_G = %b | ",OUTPUT_A_expected_prev,OUTPUT_B_expected_prev,OUTPUT_C_expected_prev,OUTPUT_D_expected_prev,OUTPUT_E_expected_prev,OUTPUT_F_expected_prev,OUTPUT_G_expected_prev); + $display("| real OUTPUT_A = %b | real OUTPUT_B = %b | real OUTPUT_C = %b | real OUTPUT_D = %b | real OUTPUT_E = %b | real OUTPUT_F = %b | real OUTPUT_G = %b | ",OUTPUT_A_prev,OUTPUT_B_prev,OUTPUT_C_prev,OUTPUT_D_prev,OUTPUT_E_prev,OUTPUT_F_prev,OUTPUT_G_prev); +`endif + if ( + ( OUTPUT_A_expected_prev !== 1'bx ) && ( OUTPUT_A_prev !== OUTPUT_A_expected_prev ) + && ((OUTPUT_A_expected_prev !== last_OUTPUT_A_exp) || + on_first_change[1]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_A :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_A_expected_prev); + $display (" Real value = %b", OUTPUT_A_prev); + nummismatches = nummismatches + 1; + on_first_change[1] = 1'b0; + last_OUTPUT_A_exp = OUTPUT_A_expected_prev; + end + if ( + ( OUTPUT_B_expected_prev !== 1'bx ) && ( OUTPUT_B_prev !== OUTPUT_B_expected_prev ) + && ((OUTPUT_B_expected_prev !== last_OUTPUT_B_exp) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_B :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_B_expected_prev); + $display (" Real value = %b", OUTPUT_B_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_OUTPUT_B_exp = OUTPUT_B_expected_prev; + end + if ( + ( OUTPUT_C_expected_prev !== 1'bx ) && ( OUTPUT_C_prev !== OUTPUT_C_expected_prev ) + && ((OUTPUT_C_expected_prev !== last_OUTPUT_C_exp) || + on_first_change[3]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_C :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_C_expected_prev); + $display (" Real value = %b", OUTPUT_C_prev); + nummismatches = nummismatches + 1; + on_first_change[3] = 1'b0; + last_OUTPUT_C_exp = OUTPUT_C_expected_prev; + end + if ( + ( OUTPUT_D_expected_prev !== 1'bx ) && ( OUTPUT_D_prev !== OUTPUT_D_expected_prev ) + && ((OUTPUT_D_expected_prev !== last_OUTPUT_D_exp) || + on_first_change[4]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_D :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_D_expected_prev); + $display (" Real value = %b", OUTPUT_D_prev); + nummismatches = nummismatches + 1; + on_first_change[4] = 1'b0; + last_OUTPUT_D_exp = OUTPUT_D_expected_prev; + end + if ( + ( OUTPUT_E_expected_prev !== 1'bx ) && ( OUTPUT_E_prev !== OUTPUT_E_expected_prev ) + && ((OUTPUT_E_expected_prev !== last_OUTPUT_E_exp) || + on_first_change[5]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_E :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_E_expected_prev); + $display (" Real value = %b", OUTPUT_E_prev); + nummismatches = nummismatches + 1; + on_first_change[5] = 1'b0; + last_OUTPUT_E_exp = OUTPUT_E_expected_prev; + end + if ( + ( OUTPUT_F_expected_prev !== 1'bx ) && ( OUTPUT_F_prev !== OUTPUT_F_expected_prev ) + && ((OUTPUT_F_expected_prev !== last_OUTPUT_F_exp) || + on_first_change[6]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_F :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_F_expected_prev); + $display (" Real value = %b", OUTPUT_F_prev); + nummismatches = nummismatches + 1; + on_first_change[6] = 1'b0; + last_OUTPUT_F_exp = OUTPUT_F_expected_prev; + end + if ( + ( OUTPUT_G_expected_prev !== 1'bx ) && ( OUTPUT_G_prev !== OUTPUT_G_expected_prev ) + && ((OUTPUT_G_expected_prev !== last_OUTPUT_G_exp) || + on_first_change[7]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_G :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_G_expected_prev); + $display (" Real value = %b", OUTPUT_G_prev); + nummismatches = nummismatches + 1; + on_first_change[7] = 1'b0; + last_OUTPUT_G_exp = OUTPUT_G_expected_prev; + end + + trigger <= ~trigger; +end +initial + +begin +$timeformat(-12,3," ps",6); +#1000000; +if (nummismatches > 0) + $display ("%d mismatched vectors : Simulation failed !",nummismatches); +else + $display ("Simulation passed !"); +$finish; +end +endmodule + +module YL_7SegmentDecoder_vlg_vec_tst(); +// constants +// general purpose registers +reg [3:0] in; +// wires +wire OUTPUT_A; +wire OUTPUT_B; +wire OUTPUT_C; +wire OUTPUT_D; +wire OUTPUT_E; +wire OUTPUT_F; +wire OUTPUT_G; + +wire sampler; + +// assign statements (if any) +YL_7SegmentDecoder i1 ( +// port map - connection between master ports and signals/registers + .in(in), + .OUTPUT_A(OUTPUT_A), + .OUTPUT_B(OUTPUT_B), + .OUTPUT_C(OUTPUT_C), + .OUTPUT_D(OUTPUT_D), + .OUTPUT_E(OUTPUT_E), + .OUTPUT_F(OUTPUT_F), + .OUTPUT_G(OUTPUT_G) +); + +// in[0] +always +begin + in[0] = 1'b0; + in[0] = #50000 1'b1; + #50000; +end + +// in[1] +always +begin + in[1] = 1'b0; + in[1] = #100000 1'b1; + #100000; +end + +// in[2] +initial +begin + repeat(2) + begin + in[2] = 1'b0; + in[2] = #200000 1'b1; + # 200000; + end + in[2] = 1'b0; +end + +// in[3] +initial +begin + in[3] = 1'b0; + in[3] = #400000 1'b1; + in[3] = #400000 1'b0; +end + +YL_7SegmentDecoder_vlg_sample_tst tb_sample ( + .in(in), + .sampler_tx(sampler) +); + +YL_7SegmentDecoder_vlg_check_tst tb_out( + .OUTPUT_A(OUTPUT_A), + .OUTPUT_B(OUTPUT_B), + .OUTPUT_C(OUTPUT_C), + .OUTPUT_D(OUTPUT_D), + .OUTPUT_E(OUTPUT_E), + .OUTPUT_F(OUTPUT_F), + .OUTPUT_G(OUTPUT_G), + .sampler_rx(sampler) +); +endmodule + diff --git a/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder_v.sdo b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder_v.sdo new file mode 100644 index 0000000..66b7ebe --- /dev/null +++ b/Exp28_Decoder/simulation/qsim/YL_7SegmentDecoder_v.sdo @@ -0,0 +1,252 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "YL_7SegmentDecoder") + (DATE "05/03/2020 17:53:55") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE in\[1\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE in\[3\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1006:1006:1006) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE in\[0\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE in\[2\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1036:1036:1036) (1036:1036:1036)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (2422:2422:2422) (2422:2422:2422)) + (PORT datab (2251:2251:2251) (2251:2251:2251)) + (PORT datac (2669:2669:2669) (2669:2669:2669)) + (PORT datad (2431:2431:2431) (2431:2431:2431)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2420:2420:2420) (2420:2420:2420)) + (PORT datab (2254:2254:2254) (2254:2254:2254)) + (PORT datac (2672:2672:2672) (2672:2672:2672)) + (PORT datad (2434:2434:2434) (2434:2434:2434)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2421:2421:2421) (2421:2421:2421)) + (PORT datab (2254:2254:2254) (2254:2254:2254)) + (PORT datac (2672:2672:2672) (2672:2672:2672)) + (PORT datad (2434:2434:2434) (2434:2434:2434)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2416:2416:2416) (2416:2416:2416)) + (PORT datab (2259:2259:2259) (2259:2259:2259)) + (PORT datac (2676:2676:2676) (2676:2676:2676)) + (PORT datad (2437:2437:2437) (2437:2437:2437)) + (IOPATH dataa combout (541:541:541) (541:541:541)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|e\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2416:2416:2416) (2416:2416:2416)) + (PORT datab (2257:2257:2257) (2257:2257:2257)) + (PORT datac (2676:2676:2676) (2676:2676:2676)) + (PORT datad (2436:2436:2436) (2436:2436:2436)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2418:2418:2418) (2418:2418:2418)) + (PORT datab (2257:2257:2257) (2257:2257:2257)) + (PORT datac (2676:2676:2676) (2676:2676:2676)) + (PORT datad (2436:2436:2436) (2436:2436:2436)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (485:485:485) (485:485:485)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst_\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2418:2418:2418) (2418:2418:2418)) + (PORT datab (2258:2258:2258) (2258:2258:2258)) + (PORT datac (2676:2676:2676) (2676:2676:2676)) + (PORT datad (2437:2437:2437) (2437:2437:2437)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2810:2810:2810) (2810:2810:2810)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (520:520:520) (520:520:520)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (860:860:860) (860:860:860)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (863:863:863) (863:863:863)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (872:872:872) (872:872:872)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (877:877:877) (877:877:877)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (869:869:869) (869:869:869)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) +) diff --git a/YL_adder/YL_adde.vwf b/YL_adder/YL_adde.vwf new file mode 100644 index 0000000..611b0ec --- /dev/null +++ b/YL_adder/YL_adde.vwf @@ -0,0 +1,1005 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("isAdd") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("overflow") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +GROUP("INPUT_B") +{ + MEMBERS = "INPUT_B1", "INPUT_B2", "INPUT_B3", "INPUT_B4"; +} + +GROUP("INPUT_A") +{ + MEMBERS = "INPUT_A4", "INPUT_A3", "INPUT_A2", "INPUT_A1"; +} + +SIGNAL("i") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("i[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("INPUT_A1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_A2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_A3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_A4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_B1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + NODE + { + REPEAT = 3; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_B2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("INPUT_B3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("INPUT_B4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 800.0; + LEVEL 1 FOR 200.0; + } + } +} + +TRANSITION_LIST("isAdd") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_A2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("overflow") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("i[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("i[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("i[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("i[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "isAdd"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 8; + TREE_LEVEL = 0; + CHILDREN = 9, 10, 11, 12; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "i"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 13; + TREE_LEVEL = 0; + CHILDREN = 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "i[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "overflow"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 27; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 28; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 29; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 30; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 31; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 32; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_adder/YL_adde.vwf.temp b/YL_adder/YL_adde.vwf.temp new file mode 100644 index 0000000..8bdd95e --- /dev/null +++ b/YL_adder/YL_adde.vwf.temp @@ -0,0 +1,862 @@ +/* Simulator = Quartus II Simulator */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("isAdd") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("num") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("overflow") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +GROUP("INPUT_A") +{ + MEMBERS = "INPUT_A1", "INPUT_A2", "INPUT_A3", "INPUT_A4"; +} + +GROUP("INPUT_B") +{ + MEMBERS = "INPUT_B1", "INPUT_B2", "INPUT_B3", "INPUT_B4"; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("INPUT_A1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_A2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_A3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_A4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_B1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("INPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("INPUT_B3") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("INPUT_B4") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("isAdd") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("num") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_A2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("overflow") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "isAdd"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 8; + TREE_LEVEL = 0; + CHILDREN = 9, 10, 11, 12; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "num"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 27; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "overflow"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 28; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_adder/YL_adder.bdf b/YL_adder/YL_adder.bdf new file mode 100644 index 0000000..93902db --- /dev/null +++ b/YL_adder/YL_adder.bdf @@ -0,0 +1,1868 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 64 48 240 64) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "clk" (rect 9 0 23 12)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 64 24 240 40) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "reset" (rect 9 0 33 12)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 16 160 192 176) + (text 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+(connector + (pt 592 336) + (pt 592 440) +) +(connector + (pt 592 440) + (pt 592 472) +) +(connector + (pt 512 336) + (pt 512 96) +) +(connector + (pt 512 96) + (pt 376 96) +) +(connector + (pt 376 96) + (pt 376 136) +) +(connector + (pt 416 312) + (pt 416 368) +) +(connector + (pt 416 312) + (pt 280 312) +) +(connector + (pt 280 312) + (pt 280 264) +) +(connector + (pt 376 264) + (pt 280 264) +) +(connector + (pt 280 264) + (pt 232 264) +) +(connector + (pt 320 392) + (pt 376 392) +) +(connector + (pt 376 392) + (pt 688 392) +) +(connector + (pt 688 448) + (pt 728 448) +) +(connector + (pt 688 392) + (pt 688 448) +) +(connector + (pt 728 368) + (pt 416 368) +) +(connector + (pt 728 368) + (pt 728 432) +) +(connector + (text "i[3..0]" (rect 938 144 966 156)(font "Arial" )) + (pt 984 160) + (pt 928 160) + (bus) +) +(connector + (pt 984 120) + (pt 984 160) + (bus) +) +(connector + (pt 984 120) + (pt 1024 120) + (bus) +) +(connector + (pt 944 0) + (pt 952 0) +) +(connector + (pt 496 168) + (pt 632 168) +) +(connector + (pt 728 464) + (pt 616 464) +) +(connector + (pt 616 216) + (pt 616 464) +) +(connector + (pt 496 216) + (pt 616 216) +) +(connector + (pt 616 216) + (pt 632 216) +) +(connector + (pt 536 152) + (pt 632 152) +) +(connector + (pt 536 32) + (pt 240 32) +) +(connector + (pt 576 336) + (pt 592 336) +) +(connector + (pt 512 336) + (pt 528 336) +) +(connector + (pt 768 120) + (pt 768 144) +) +(junction (pt 592 440)) +(junction (pt 280 264)) +(junction (pt 376 392)) +(junction (pt 616 216)) diff --git a/YL_adder/YL_adder.qpf b/YL_adder/YL_adder.qpf new file mode 100644 index 0000000..4fcc642 --- /dev/null +++ b/YL_adder/YL_adder.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 12:07:53 May 04, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "12:07:53 May 04, 2020" + +# Revisions + +PROJECT_REVISION = "YL_adder" diff --git a/YL_adder/YL_adder.qsf b/YL_adder/YL_adder.qsf new file mode 100644 index 0000000..c2f2785 --- /dev/null +++ b/YL_adder/YL_adder.qsf @@ -0,0 +1,95 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 12:07:53 May 04, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# YL_adder_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY YL_adder +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:07:53 MAY 04, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name BDF_FILE YL_adder.bdf +set_global_assignment -name AHDL_FILE YL_7segment.tdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name AHDL_FILE ../Exp28_Decoder/YL_7segment_sign.tdf +set_global_assignment -name AHDL_FILE YL_7segment_sign.tdf +set_global_assignment -name AHDL_FILE YL_sign_to_unsign.tdf +set_global_assignment -name AHDL_FILE operator.tdf +set_global_assignment -name AHDL_FILE overflow.tdf +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_adde.vwf +set_global_assignment -name SIMULATION_MODE FUNCTIONAL +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_L1 -to clk +set_location_assignment PIN_L2 -to reset +set_location_assignment PIN_M1 -to isAdd +set_location_assignment PIN_L22 -to INPUT_A4 +set_location_assignment PIN_L21 -to INPUT_A3 +set_location_assignment PIN_M22 -to INPUT_A2 +set_location_assignment PIN_V12 -to INPUT_A1 +set_location_assignment PIN_W12 -to INPUT_B4 +set_location_assignment PIN_U12 -to INPUT_B3 +set_location_assignment PIN_U11 -to INPUT_B2 +set_location_assignment PIN_M2 -to INPUT_B1 +set_location_assignment PIN_D1 -to OUTPUT_G2 +set_location_assignment PIN_E2 -to OUTPUT_G +set_location_assignment PIN_D2 -to OUTPUT_F2 +set_location_assignment PIN_F1 -to OUTPUT_F +set_location_assignment PIN_G3 -to OUTPUT_E2 +set_location_assignment PIN_F2 -to OUTPUT_E +set_location_assignment PIN_H4 -to OUTPUT_D2 +set_location_assignment PIN_H1 -to OUTPUT_D +set_location_assignment PIN_H5 -to OUTPUT_C2 +set_location_assignment PIN_H2 -to OUTPUT_C +set_location_assignment PIN_H6 -to OUTPUT_B2 +set_location_assignment PIN_J1 -to OUTPUT_B +set_location_assignment PIN_E1 -to OUTPUT_A2 +set_location_assignment PIN_J2 -to OUTPUT_A +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adde.vwf" \ No newline at end of file diff --git a/YL_adder/YL_adder.qws b/YL_adder/YL_adder.qws new file mode 100644 index 0000000000000000000000000000000000000000..35cd50d3ef7d30c72b81d1a3158ec0725d3787c4 GIT binary patch literal 6154 zcmeI0&ubGw6vw~2wOB9WNd%KDK`3dmX-jKUlGrNR_U=t@ zdh#ZoJb3HB;Ki$61pf-bYW=*)hPG?kLXEpNbeEZ(H~V(x&704>ndC~Jn%5c4si2zb zn$VIes%jQ#fx4msl#Y^~X-uQa=q_&pG-{L|kxy%eFEYBNdFrq6W=4yYGQ6v!QPLBq zS)q@Nu4|k$rkt|e8Qn*opq~=AwHmES)7Fy8^uLlw|5c?miEVLOP{H%&ivs?$xk&SD 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F^?%d59QFVJ literal 0 HcmV?d00001 diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.cmp_merge.kpt b/Exp28_Decoder/db/YL_7SegmentDecoder.cmp_merge.kpt new file mode 100644 index 0000000000000000000000000000000000000000..b01b4d8d6ea2c3f7604df90a0ad3315ef25ecad0 GIT binary patch literal 234 zcmVuG0001ZoTZV$O2jY_hVOlfA@^;YR@Te5hs8atcu)$8r;tr%*HDwj zNxHD$!<#jrhzf$&nfbo|hgpq23cUj-Eq3hjMqCbfu;}6ys!1c2%6egu4#?nqdPE9l zavkF(XYevhigWm!-sJ&ox3IietWAXbyaL{qb;)5pn`aG8+d#dncvCesZ(%?>8ijBx z)d(DhYk0sNY_y4qWPJg!8u29jWLyj)V1#(`sV?Cj37tyao(xjj_>R41p!!PuE{P;v k$VvaT>?g9Q|ET#O>fn}0&Pyhe` literal 0 HcmV?d00001 diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.db_info b/Exp28_Decoder/db/YL_7SegmentDecoder.db_info new file mode 100644 index 0000000..4d58563 --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Sun May 03 20:37:39 2020 diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.eda.qmsg b/Exp28_Decoder/db/YL_7SegmentDecoder.eda.qmsg new file mode 100644 index 0000000..7ec9509 --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588514812218 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 22:06:51 2020 " "Processing started: Sun May 03 22:06:51 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""} +{ "Info" "IWSC_DONE_HDL_DUAL_SDO_GENERATION" "YL_7SegmentDecoder.vo\", \"YL_7SegmentDecoder_fast.vo YL_7SegmentDecoder_v.sdo YL_7SegmentDecoder_v_fast.sdo C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/ simulation " "Generated files \"YL_7SegmentDecoder.vo\", \"YL_7SegmentDecoder_fast.vo\", \"YL_7SegmentDecoder_v.sdo\" and \"YL_7SegmentDecoder_v_fast.sdo\" in directory \"C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204026 "Generated files \"%1!s!\", \"%2!s!\" and \"%3!s!\" in directory \"%4!s!\" for EDA %5!s! tool" 0 0 "Quartus II" 0 -1 1588514812743 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4529 " "Peak virtual memory: 4529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514812789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:06:52 2020 " "Processing ended: Sun May 03 22:06:52 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""} diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.eds_overflow b/Exp28_Decoder/db/YL_7SegmentDecoder.eds_overflow new file mode 100644 index 0000000..bcce32e --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.eds_overflow @@ -0,0 +1 @@ +3002 \ No newline at end of file diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.fit.qmsg b/Exp28_Decoder/db/YL_7SegmentDecoder.fit.qmsg new file mode 100644 index 0000000..b86eecc --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.fit.qmsg @@ -0,0 +1,47 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1588514799754 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "YL_7SegmentDecoder EP2C20F484C7 " "Selected device EP2C20F484C7 for design \"YL_7SegmentDecoder\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1588514799764 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588514799816 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588514799816 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1588514799902 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1588514799919 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Device EP2C15AF484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588514800438 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Device EP2C35F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588514800438 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Device EP2C50F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588514800438 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1588514800438 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 183 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588514800439 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 184 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588514800439 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 185 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588514800439 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1588514800439 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 17 " "No exact pin location assignment(s) for 7 pins of 17 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_A1 " "Pin OUTPUT_A1 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_A1 } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 408 648 824 424 "OUTPUT_A1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_A1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 18 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588514800521 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_B2 " "Pin OUTPUT_B2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_B2 } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 440 648 824 456 "OUTPUT_B2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 19 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588514800521 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_C3 " "Pin OUTPUT_C3 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_C3 } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 472 648 824 488 "OUTPUT_C3" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_C3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 20 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588514800521 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_D4 " "Pin OUTPUT_D4 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_D4 } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 504 648 824 520 "OUTPUT_D4" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_D4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 21 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588514800521 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_E5 " "Pin OUTPUT_E5 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_E5 } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 536 648 824 552 "OUTPUT_E5" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_E5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 22 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588514800521 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_F6 " "Pin OUTPUT_F6 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_F6 } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 568 648 824 584 "OUTPUT_F6" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_F6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 23 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588514800521 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_G7 " "Pin OUTPUT_G7 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_G7 } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 600 648 824 616 "OUTPUT_G7" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_G7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 24 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588514800521 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1588514800521 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_7SegmentDecoder.sdc " "Synopsys Design Constraints File file not found: 'YL_7SegmentDecoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1588514800686 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1588514800688 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1588514800701 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Automatically promoted node clk (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588514800728 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 232 -88 80 248 "clk" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 0 { 0 ""} 0 9 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588514800728 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1588514800949 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588514800949 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588514800950 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588514800952 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588514800953 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1588514800955 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1588514800955 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1588514800957 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1588514800957 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1588514800962 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1588514800962 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 3.3V 0 7 0 " "Number of I/O pins in group: 7 (unused VREF, 3.3V VCCIO, 0 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1588514800965 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1588514800965 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1588514800965 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 0 41 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 10 23 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 10 total pin(s) used -- 23 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 1 38 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 38 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 2 34 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 34 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588514800968 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1588514800968 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1588514800968 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "enc " "Node \"enc\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "enc" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1588514800987 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1588514800987 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588514800987 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1588514802488 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588514802575 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1588514802585 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1588514803153 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588514803153 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1588514803219 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y14 X11_Y27 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y14 to location X11_Y27" { } { { "loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y14 to location X11_Y27"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y14 to location X11_Y27"} 0 14 12 14 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1588514804064 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1588514804064 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588514804392 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1588514804397 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1588514804397 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.30 " "Total time spent on timing analysis during the Fitter is 0.30 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1588514804405 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588514804407 ""} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "14 " "Found 14 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_A 0 " "Pin \"OUTPUT_A\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_B 0 " "Pin \"OUTPUT_B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_C 0 " "Pin \"OUTPUT_C\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_D 0 " "Pin \"OUTPUT_D\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_E 0 " "Pin \"OUTPUT_E\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_F 0 " "Pin \"OUTPUT_F\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_G 0 " "Pin \"OUTPUT_G\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_A1 0 " "Pin \"OUTPUT_A1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_B2 0 " "Pin \"OUTPUT_B2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_C3 0 " "Pin \"OUTPUT_C3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_D4 0 " "Pin \"OUTPUT_D4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_E5 0 " "Pin \"OUTPUT_E5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_F6 0 " "Pin \"OUTPUT_F6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_G7 0 " "Pin \"OUTPUT_G7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588514804412 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1588514804412 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588514804525 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588514804565 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588514804677 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588514804933 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1588514804995 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1588514804995 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.smsg " "Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1588514805083 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4840 " "Peak virtual memory: 4840 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514805391 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:06:45 2020 " "Processing ended: Sun May 03 22:06:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514805391 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514805391 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514805391 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1588514805391 ""} diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.cdb b/Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.cdb new file mode 100644 index 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z%G{5)_8ZxCPwN70|E|}`k~%BY6ts+0^ByP^1B0rhs*7LSWp1s*{OsNHKII{O#HDFB z(AgDP6ZV*;lm4w-4vys{tds%~s}+vRC$AOGyszef5m2AC?&bDQ$D#?LRTS#Pt1|M~EXb{FAe0wH9#XLM-;wEm0jjat5&!@I literal 0 HcmV?d00001 diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.qmsg b/Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.qmsg new file mode 100644 index 0000000..8128fdc --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.qmsg @@ -0,0 +1,16 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588514885944 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II 64-Bit " "Running Quartus II 64-Bit Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588514885945 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 22:08:05 2020 " "Processing started: Sun May 03 22:08:05 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588514885945 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588514885945 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map YL_7SegmentDecoder -c YL_7SegmentDecoder --generate_functional_sim_netlist " "Command: quartus_map YL_7SegmentDecoder -c YL_7SegmentDecoder --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588514885946 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588514886504 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec_counter.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dec_count " "Found entity 1: dec_count" { } { { "YL_dec_counter.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_dec_counter.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514886568 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514886568 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_7SegmentDecoder " "Found entity 1: YL_7SegmentDecoder" { } { { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514886572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514886572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7segment " "Found entity 1: 7segment" { } { { "YL_7SegmentDecoder.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514886578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514886578 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder2.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_7SegmentDecoder2 " "Found entity 1: YL_7SegmentDecoder2" { } { { "YL_7SegmentDecoder2.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder2.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514886585 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514886585 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_sec_cnt.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_sec_cnt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sec_cnt " "Found entity 1: sec_cnt" { } { { "YL_sec_cnt.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_sec_cnt.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514886593 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514886593 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_cascade.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_cascade.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_Cascade " "Found entity 1: YL_Cascade" { } { { "YL_Cascade.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_Cascade.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514886597 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514886597 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_7SegmentDecoder " "Elaborating entity \"YL_7SegmentDecoder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588514886668 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7segment 7segment:inst_ " "Elaborating entity \"7segment\" for hierarchy \"7segment:inst_\"" { } { { "YL_7SegmentDecoder.bdf" "inst_" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 184 384 512 360 "inst_" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514886676 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst8 " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst8\"" { } { { "YL_7SegmentDecoder.bdf" "inst8" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 184 168 328 296 "inst8" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514886681 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sec_cnt sec_cnt:inst10 " "Elaborating entity \"sec_cnt\" for hierarchy \"sec_cnt:inst10\"" { } { { "YL_7SegmentDecoder.bdf" "inst10" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 16 120 264 96 "inst10" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514886686 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst11 " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst11\"" { } { { "YL_7SegmentDecoder.bdf" "inst11" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 424 160 320 536 "inst11" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514886698 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514886848 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:08:06 2020 " "Processing ended: Sun May 03 22:08:06 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514886848 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514886848 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514886848 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588514886848 ""} diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.hier_info b/Exp28_Decoder/db/YL_7SegmentDecoder.hier_info new file mode 100644 index 0000000..8414958 --- /dev/null +++ b/Exp28_Decoder/db/YL_7SegmentDecoder.hier_info @@ -0,0 +1,237 @@ +|YL_7SegmentDecoder +OUTPUT_A <= inst.DB_MAX_OUTPUT_PORT_TYPE +clk => sec_cnt:inst10.clk +clk => dec_count:inst8.clk +clk => dec_count:inst11.clk +ent => dec_count:inst8.ent +clear => dec_count:inst8.clear +clear => dec_count:inst11.clear +OUTPUT_B <= inst1.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_C <= inst2.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_D <= inst3.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_E <= inst4.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_F <= inst5.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_G <= inst6.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_A1 <= inst12.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_B2 <= inst7.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_C3 <= inst13.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_D4 <= inst14.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_E5 <= inst15.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_F6 <= inst16.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_G7 <= inst17.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_7SegmentDecoder|7segment:inst_ +i[0] => _~4.IN0 +i[0] => b~1.IN3 +i[0] => _~10.IN0 +i[0] => a~6.IN3 +i[0] => _~15.IN0 +i[0] => a~8.IN3 +i[0] => _~19.IN0 +i[0] => a~12.IN3 +i[0] => _~23.IN0 +i[0] => a~16.IN3 +i[0] => _~27.IN0 +i[0] => c~2.IN3 +i[0] => _~30.IN0 +i[0] => b~6.IN3 +i[0] => _~32.IN0 +i[0] => a~24.IN3 +i[1] => _~3.IN0 +i[1] => _~7.IN0 +i[1] => a~4.IN2 +i[1] => a~6.IN2 +i[1] => _~14.IN0 +i[1] => _~17.IN0 +i[1] => a~10.IN2 +i[1] => a~12.IN2 +i[1] => _~22.IN0 +i[1] => _~25.IN0 +i[1] => a~18.IN2 +i[1] => c~2.IN2 +i[1] => _~29.IN0 +i[1] => _~31.IN0 +i[1] => a~22.IN2 +i[1] => a~24.IN2 +i[2] => _~2.IN0 +i[2] => _~6.IN0 +i[2] => _~9.IN0 +i[2] => _~12.IN0 +i[2] => b~4.IN1 +i[2] => a~8.IN1 +i[2] => a~10.IN1 +i[2] => a~12.IN1 +i[2] => _~21.IN0 +i[2] => _~24.IN0 +i[2] => _~26.IN0 +i[2] => _~28.IN0 +i[2] => a~20.IN1 +i[2] => b~6.IN1 +i[2] => a~22.IN1 +i[2] => a~24.IN1 +i[3] => _~1.IN0 +i[3] => _~5.IN0 +i[3] => _~8.IN0 +i[3] => _~11.IN0 +i[3] => _~13.IN0 +i[3] => _~16.IN0 +i[3] => _~18.IN0 +i[3] => _~20.IN0 +i[3] => a~14.IN0 +i[3] => a~16.IN0 +i[3] => a~18.IN0 +i[3] => c~2.IN0 +i[3] => a~20.IN0 +i[3] => b~6.IN0 +i[3] => a~22.IN0 +i[3] => a~24.IN0 +a <= a~2.DB_MAX_OUTPUT_PORT_TYPE +b <= b~2.DB_MAX_OUTPUT_PORT_TYPE +c <= c~0.DB_MAX_OUTPUT_PORT_TYPE +d <= d~0.DB_MAX_OUTPUT_PORT_TYPE +e <= e~0.DB_MAX_OUTPUT_PORT_TYPE +f <= f~0.DB_MAX_OUTPUT_PORT_TYPE +g <= g~0.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_7SegmentDecoder|dec_count:inst8 +enc => _~2.IN0 +enc => _~13.IN0 +ent => _~2.IN1 +ent => _~13.IN1 +ent => rco~0.IN1 +clk => count[3].CLK +clk => count[2].CLK +clk => count[1].CLK +clk => count[0].CLK +clear => _~1.IN0 +value[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE +value[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE +value[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE +value[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE +rco <= rco~0.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_7SegmentDecoder|sec_cnt:inst10 +clk => count[25].CLK +clk => count[24].CLK +clk => count[23].CLK +clk => count[22].CLK +clk => count[21].CLK +clk => count[20].CLK +clk => count[19].CLK +clk => count[18].CLK +clk => count[17].CLK +clk => count[16].CLK +clk => count[15].CLK +clk => count[14].CLK +clk => count[13].CLK +clk => count[12].CLK +clk => count[11].CLK +clk => count[10].CLK +clk => count[9].CLK +clk => count[8].CLK +clk => count[7].CLK +clk => count[6].CLK +clk => count[5].CLK +clk => count[4].CLK +clk => count[3].CLK +clk => count[2].CLK +clk => count[1].CLK +clk => count[0].CLK +second <= second~2.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_7SegmentDecoder|7segment:inst_12 +i[0] => _~4.IN0 +i[0] => b~1.IN3 +i[0] => _~10.IN0 +i[0] => a~6.IN3 +i[0] => _~15.IN0 +i[0] => a~8.IN3 +i[0] => _~19.IN0 +i[0] => a~12.IN3 +i[0] => _~23.IN0 +i[0] => a~16.IN3 +i[0] => _~27.IN0 +i[0] => c~2.IN3 +i[0] => _~30.IN0 +i[0] => b~6.IN3 +i[0] => _~32.IN0 +i[0] => a~24.IN3 +i[1] => _~3.IN0 +i[1] => _~7.IN0 +i[1] => a~4.IN2 +i[1] => a~6.IN2 +i[1] => _~14.IN0 +i[1] => _~17.IN0 +i[1] => a~10.IN2 +i[1] => a~12.IN2 +i[1] => _~22.IN0 +i[1] => _~25.IN0 +i[1] => a~18.IN2 +i[1] => c~2.IN2 +i[1] => _~29.IN0 +i[1] => _~31.IN0 +i[1] => a~22.IN2 +i[1] => a~24.IN2 +i[2] => _~2.IN0 +i[2] => _~6.IN0 +i[2] => _~9.IN0 +i[2] => _~12.IN0 +i[2] => b~4.IN1 +i[2] => a~8.IN1 +i[2] => a~10.IN1 +i[2] => a~12.IN1 +i[2] => _~21.IN0 +i[2] => _~24.IN0 +i[2] => _~26.IN0 +i[2] => _~28.IN0 +i[2] => a~20.IN1 +i[2] => b~6.IN1 +i[2] => a~22.IN1 +i[2] => a~24.IN1 +i[3] => _~1.IN0 +i[3] => _~5.IN0 +i[3] => _~8.IN0 +i[3] => _~11.IN0 +i[3] => _~13.IN0 +i[3] => _~16.IN0 +i[3] => _~18.IN0 +i[3] => _~20.IN0 +i[3] => a~14.IN0 +i[3] => a~16.IN0 +i[3] => a~18.IN0 +i[3] => c~2.IN0 +i[3] => a~20.IN0 +i[3] => b~6.IN0 +i[3] => a~22.IN0 +i[3] => a~24.IN0 +a <= a~2.DB_MAX_OUTPUT_PORT_TYPE +b <= b~2.DB_MAX_OUTPUT_PORT_TYPE +c <= c~0.DB_MAX_OUTPUT_PORT_TYPE +d <= d~0.DB_MAX_OUTPUT_PORT_TYPE +e <= e~0.DB_MAX_OUTPUT_PORT_TYPE +f <= f~0.DB_MAX_OUTPUT_PORT_TYPE +g <= g~0.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_7SegmentDecoder|dec_count:inst11 +enc => _~2.IN0 +enc => _~13.IN0 +ent => _~2.IN1 +ent => _~13.IN1 +ent => rco~0.IN1 +clk => count[3].CLK +clk => count[2].CLK +clk => count[1].CLK +clk => count[0].CLK +clear => _~1.IN0 +value[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE +value[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE +value[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE +value[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE +rco <= rco~0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/Exp28_Decoder/db/YL_7SegmentDecoder.hif b/Exp28_Decoder/db/YL_7SegmentDecoder.hif new file mode 100644 index 0000000000000000000000000000000000000000..aeae432f2efa2c8dbe76710c7ad61b3167078d25 GIT binary patch literal 619 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b/YL_adder/db/YL_adder.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Mon May 04 14:49:14 2020 diff --git a/YL_adder/db/YL_adder.eda.qmsg b/YL_adder/db/YL_adder.eda.qmsg new file mode 100644 index 0000000..5e534bf --- /dev/null +++ b/YL_adder/db/YL_adder.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588583146463 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588583146467 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:05:46 2020 " "Processing started: Mon May 04 17:05:46 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588583146467 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588583146467 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588583146467 ""} +{ "Info" "IWSC_DONE_HDL_DUAL_SDO_GENERATION" "YL_adder.vo\", \"YL_adder_fast.vo YL_adder_v.sdo YL_adder_v_fast.sdo C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/simulation/modelsim/ simulation " "Generated files \"YL_adder.vo\", \"YL_adder_fast.vo\", \"YL_adder_v.sdo\" and \"YL_adder_v_fast.sdo\" in directory \"C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204026 "Generated files \"%1!s!\", \"%2!s!\" and \"%3!s!\" in directory \"%4!s!\" for EDA %5!s! tool" 0 0 "Quartus II" 0 -1 1588583147196 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4529 " "Peak virtual memory: 4529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588583147247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:05:47 2020 " "Processing ended: Mon May 04 17:05:47 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588583147247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588583147247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588583147247 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588583147247 ""} diff --git a/YL_adder/db/YL_adder.eds_overflow b/YL_adder/db/YL_adder.eds_overflow new file mode 100644 index 0000000..4b9bce4 --- /dev/null +++ b/YL_adder/db/YL_adder.eds_overflow @@ -0,0 +1 @@ +148 \ No newline at end of file diff --git a/YL_adder/db/YL_adder.fit.qmsg b/YL_adder/db/YL_adder.fit.qmsg new file mode 100644 index 0000000..50f8e4d --- /dev/null +++ b/YL_adder/db/YL_adder.fit.qmsg @@ -0,0 +1,46 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1588583133589 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "YL_adder EP2C20F484C7 " "Selected device EP2C20F484C7 for design \"YL_adder\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1588583133604 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588583133690 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588583133690 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1588583133914 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1588583133956 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Device EP2C15AF484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588583134628 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Device EP2C35F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588583134628 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Device EP2C50F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588583134628 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1588583134628 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588583134630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588583134630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 93 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588583134630 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1588583134630 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "31 31 " "No exact pin location assignment(s) for 31 pins of 31 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_A " "Pin OUTPUT_A not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_A } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 72 1288 1464 88 "OUTPUT_A" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_A } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 15 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[3\] " "Pin i\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[3] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 11 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[2\] " "Pin i\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[2] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 12 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[1\] " "Pin i\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[1] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 13 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[0\] " "Pin i\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[0] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 14 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_B " "Pin OUTPUT_B not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_B } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 104 1288 1464 120 "OUTPUT_B" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_B } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 27 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_C " "Pin OUTPUT_C not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_C } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 136 1288 1464 152 "OUTPUT_C" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_C } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 28 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_D " "Pin OUTPUT_D not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_D } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 168 1288 1464 184 "OUTPUT_D" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_D } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 29 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_E " "Pin OUTPUT_E not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_E } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 200 1288 1464 216 "OUTPUT_E" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_E } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 30 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_F " "Pin OUTPUT_F not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_F } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 232 1288 1464 248 "OUTPUT_F" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_F } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 31 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_G " "Pin OUTPUT_G not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_G } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 264 1288 1464 280 "OUTPUT_G" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_G } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 32 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_A2 " "Pin OUTPUT_A2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_A2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 344 1288 1464 360 "OUTPUT_A2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_A2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 33 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_B2 " "Pin OUTPUT_B2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_B2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 376 1288 1464 392 "OUTPUT_B2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 34 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_C2 " "Pin OUTPUT_C2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_C2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 408 1288 1464 424 "OUTPUT_C2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_C2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 35 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_D2 " "Pin OUTPUT_D2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_D2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 440 1288 1464 456 "OUTPUT_D2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_D2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 36 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_E2 " "Pin OUTPUT_E2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_E2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 472 1288 1464 488 "OUTPUT_E2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_E2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 37 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_F2 " "Pin OUTPUT_F2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_F2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 504 1288 1464 520 "OUTPUT_F2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_F2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 38 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_G2 " "Pin OUTPUT_G2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_G2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 536 1288 1464 552 "OUTPUT_G2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_G2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 39 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "overflow " "Pin overflow not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { overflow } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 424 848 1024 440 "overflow" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { overflow } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 40 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_name1 " "Pin pin_name1 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { pin_name1 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 792 968 64 "pin_name1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pin_name1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 41 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A4 " "Pin INPUT_A4 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A4 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 208 24 192 224 "INPUT_A4" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 25 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B3 " "Pin INPUT_B3 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B3 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 368 16 184 384 "INPUT_B3" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 19 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isAdd " "Pin isAdd not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { isAdd } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 432 400 568 448 "isAdd" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { isAdd } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 21 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A3 " "Pin INPUT_A3 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A3 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 192 24 192 208 "INPUT_A3" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 24 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B2 " "Pin INPUT_B2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 352 16 184 368 "INPUT_B2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 18 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B1 " "Pin INPUT_B1 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B1 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 336 16 184 352 "INPUT_B1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 17 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A1 " "Pin INPUT_A1 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A1 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 160 16 192 176 "INPUT_A1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 22 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A2 " "Pin INPUT_A2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 176 24 192 192 "INPUT_A2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 23 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B4 " "Pin INPUT_B4 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B4 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 384 8 184 400 "INPUT_B4" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 20 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 64 240 64 "clk" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 26 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "reset " "Pin reset not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { reset } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 24 64 240 40 "reset" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 16 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588583134715 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1588583134715 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_adder.sdc " "Synopsys Design Constraints File file not found: 'YL_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1588583134854 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1588583134857 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1588583134863 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588583134897 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 64 240 64 "clk" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 26 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588583134897 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) " "Automatically promoted node reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588583134897 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { reset } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 24 64 240 40 "reset" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 16 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588583134897 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1588583134972 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588583134973 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588583134973 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588583134974 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588583134974 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1588583134974 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1588583134974 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1588583134975 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1588583134976 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1588583134977 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1588583134977 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "29 unused 3.3V 9 20 0 " "Number of I/O pins in group: 29 (unused VREF, 3.3V VCCIO, 9 input, 20 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1588583134980 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1588583134980 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1588583134980 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 39 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 31 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 39 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 35 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588583134981 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1588583134981 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1588583134981 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588583134998 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1588583136777 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588583136851 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1588583136867 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1588583137247 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588583137248 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1588583137367 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X38_Y14 X50_Y27 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y14 to location X50_Y27" { } { { "loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y14 to location X50_Y27"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y14 to location X50_Y27"} 38 14 13 14 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1588583138203 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1588583138203 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588583138278 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1588583138281 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1588583138281 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1588583138281 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.17 " "Total time spent on timing analysis during the Fitter is 0.17 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1588583138291 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588583138295 ""} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "20 " "Found 20 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_A 0 " "Pin \"OUTPUT_A\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[3\] 0 " "Pin \"i\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[2\] 0 " "Pin \"i\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[1\] 0 " "Pin \"i\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[0\] 0 " "Pin \"i\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_B 0 " "Pin \"OUTPUT_B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_C 0 " "Pin \"OUTPUT_C\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_D 0 " "Pin \"OUTPUT_D\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_E 0 " "Pin \"OUTPUT_E\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_F 0 " "Pin \"OUTPUT_F\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_G 0 " "Pin \"OUTPUT_G\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_A2 0 " "Pin \"OUTPUT_A2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_B2 0 " "Pin \"OUTPUT_B2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_C2 0 " "Pin \"OUTPUT_C2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_D2 0 " "Pin \"OUTPUT_D2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_E2 0 " "Pin \"OUTPUT_E2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_F2 0 " "Pin \"OUTPUT_F2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_G2 0 " "Pin \"OUTPUT_G2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "overflow 0 " "Pin \"overflow\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pin_name1 0 " "Pin \"pin_name1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588583138297 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1588583138297 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588583138427 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588583138439 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588583138559 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588583138818 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1588583138894 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.fit.smsg " "Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1588583139029 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4848 " "Peak virtual memory: 4848 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588583139235 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:05:39 2020 " "Processing ended: Mon May 04 17:05:39 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588583139235 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588583139235 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588583139235 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1588583139235 ""} diff --git a/YL_adder/db/YL_adder.fnsim.cdb b/YL_adder/db/YL_adder.fnsim.cdb new file mode 100644 index 0000000000000000000000000000000000000000..6c4df34ecb1ba8ccd81e222af34599c506b6a8f9 GIT binary patch literal 5936 zcmeHLc{J4f`{yEUmPoQ>sYHb#S!!m?jeAvBQG`N9hLB}M7#TB)EFsZCVWwSW8T)cA zqf3UwSYnLb45qS-G0Z;m`MLLg&+nYypTGaV=Y5{{>v^B^EU)J|&-2fFmz0!L*$(N= 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232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588585220324 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:40:20 2020 " "Processing started: Mon May 04 17:40:20 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588585220324 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588585220324 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map YL_adder -c YL_adder --generate_functional_sim_netlist " "Command: quartus_map YL_adder -c YL_adder --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588585220325 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588585221323 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_adder " "Found entity 1: YL_adder" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588585221415 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588585221415 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_7segment.tdf " "Can't analyze file -- file YL_7segment.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588585221424 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/ushio/onedrive/study/uol/elec211/exp28_decoder/yl_7segment_sign.tdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/ushio/onedrive/study/uol/elec211/exp28_decoder/yl_7segment_sign.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7segment " "Found entity 1: 7segment" { } { { "../Exp28_Decoder/YL_7segment_sign.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7segment_sign.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588585221437 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588585221437 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_7segment_sign.tdf " "Can't analyze file -- file YL_7segment_sign.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588585221478 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_sign_to_unsign.tdf " "Can't analyze file -- file YL_sign_to_unsign.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588585221497 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "operator.tdf 1 1 " "Found 1 design units, including 1 entities, in source file operator.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 operator " "Found entity 1: operator" { } { { "operator.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/operator.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588585221508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588585221508 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "overflow.tdf 1 1 " "Found 1 design units, including 1 entities, in source file overflow.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 overflow " "Found entity 1: overflow" { } { { "overflow.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/overflow.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588585221514 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588585221514 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_adder " "Elaborating entity \"YL_adder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588585221610 ""} +{ "Warning" "WSGN_SEARCH_FILE" "segment.tdf 1 1 " "Using design file segment.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 segment " "Found entity 1: segment" { } { { "segment.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/segment.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588585221694 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588585221694 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment segment:inst17 " "Elaborating entity \"segment\" for hierarchy \"segment:inst17\"" { } { { "YL_adder.bdf" "inst17" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 88 1024 1152 264 "inst17" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588585221704 ""} +{ "Warning" "WSGN_SEARCH_FILE" "encoder.tdf 1 1 " "Using design file encoder.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 encoder " "Found entity 1: encoder" { } { { "encoder.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/encoder.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588585221743 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588585221743 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "encoder encoder:inst20 " "Elaborating entity \"encoder\" for hierarchy \"encoder:inst20\"" { } { { "YL_adder.bdf" "inst20" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 800 928 224 "inst20" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588585221746 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74171 74171:inst1 " "Elaborating entity \"74171\" for hierarchy \"74171:inst1\"" { } { { "YL_adder.bdf" "inst1" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 96 632 736 256 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588585221805 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "74171:inst1 " "Elaborated megafunction instantiation \"74171:inst1\"" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 96 632 736 256 "inst1" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588585221810 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7483 7483:inst " "Elaborating entity \"7483\" for hierarchy \"7483:inst\"" { } { { "YL_adder.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 376 496 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588585221856 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "7483:inst " "Elaborated megafunction instantiation \"7483:inst\"" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 376 496 304 "inst" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588585221875 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "operator operator:inst21 " "Elaborating entity \"operator\" for hierarchy \"operator:inst21\"" { } { { "YL_adder.bdf" "inst21" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 312 184 320 456 "inst21" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588585221883 ""} +{ "Warning" "WSGN_SEARCH_FILE" "sign.tdf 1 1 " "Using design file sign.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sign " "Found entity 1: sign" { } { { "sign.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/sign.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588585221911 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588585221911 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign sign:inst19 " "Elaborating entity \"sign\" for hierarchy \"sign:inst19\"" { } { { "YL_adder.bdf" "inst19" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 360 1032 1152 536 "inst19" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588585221919 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "overflow overflow:inst23 " "Elaborating entity \"overflow\" for hierarchy \"overflow:inst23\"" { } { { "YL_adder.bdf" "inst23" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 400 728 848 512 "inst23" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588585221926 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 7 s Quartus II 64-Bit " "Quartus II 64-Bit Functional Simulation Netlist Generation was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588585222167 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:40:22 2020 " "Processing ended: Mon May 04 17:40:22 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588585222167 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588585222167 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588585222167 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588585222167 ""} diff --git a/YL_adder/db/YL_adder.hier_info b/YL_adder/db/YL_adder.hier_info new file mode 100644 index 0000000..00817e3 --- /dev/null +++ b/YL_adder/db/YL_adder.hier_info @@ -0,0 +1,265 @@ +|YL_adder +OUTPUT_A <= inst2.DB_MAX_OUTPUT_PORT_TYPE +i[0] <= encoder:inst20.o[0] +i[1] <= encoder:inst20.o[1] +i[2] <= encoder:inst20.o[2] +i[3] <= encoder:inst20.o[3] +reset => inst25.IN0 +INPUT_B1 => operator:inst21.b1 +INPUT_B2 => operator:inst21.b2 +INPUT_B3 => operator:inst21.b3 +INPUT_B4 => operator:inst21.b4 +isAdd => operator:inst21.isAdd +isAdd => inst26.IN0 +INPUT_A1 => 7483:inst.A1 +INPUT_A2 => 7483:inst.A2 +INPUT_A3 => 7483:inst.A3 +INPUT_A4 => 7483:inst.A4 +INPUT_A4 => overflow:inst23.iA +clk => 74171:inst1.CLK +OUTPUT_B <= inst3.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_C <= inst4.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_D <= inst5.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_E <= inst6.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_F <= inst7.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_G <= inst8.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_A2 <= inst10.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_B2 <= inst11.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_C2 <= inst12.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_D2 <= inst13.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_E2 <= inst14.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_F2 <= inst15.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_G2 <= inst16.DB_MAX_OUTPUT_PORT_TYPE +overflow <= overflow:inst23.v + + +|YL_adder|segment:inst17 +i[0] => _~4.IN0 +i[0] => b~1.IN3 +i[0] => _~10.IN0 +i[0] => a~6.IN3 +i[0] => _~15.IN0 +i[0] => a~8.IN3 +i[0] => _~19.IN0 +i[0] => a~12.IN3 +i[0] => _~23.IN0 +i[0] => a~16.IN3 +i[0] => _~27.IN0 +i[0] => c~2.IN3 +i[0] => _~30.IN0 +i[0] => b~6.IN3 +i[0] => _~32.IN0 +i[0] => a~24.IN3 +i[1] => _~3.IN0 +i[1] => _~7.IN0 +i[1] => a~4.IN2 +i[1] => a~6.IN2 +i[1] => _~14.IN0 +i[1] => _~17.IN0 +i[1] => a~10.IN2 +i[1] => a~12.IN2 +i[1] => _~22.IN0 +i[1] => _~25.IN0 +i[1] => a~18.IN2 +i[1] => c~2.IN2 +i[1] => _~29.IN0 +i[1] => _~31.IN0 +i[1] => a~22.IN2 +i[1] => a~24.IN2 +i[2] => _~2.IN0 +i[2] => _~6.IN0 +i[2] => _~9.IN0 +i[2] => _~12.IN0 +i[2] => b~4.IN1 +i[2] => a~8.IN1 +i[2] => a~10.IN1 +i[2] => a~12.IN1 +i[2] => _~21.IN0 +i[2] => _~24.IN0 +i[2] => _~26.IN0 +i[2] => _~28.IN0 +i[2] => a~20.IN1 +i[2] => b~6.IN1 +i[2] => a~22.IN1 +i[2] => a~24.IN1 +i[3] => _~1.IN0 +i[3] => _~5.IN0 +i[3] => _~8.IN0 +i[3] => _~11.IN0 +i[3] => _~13.IN0 +i[3] => _~16.IN0 +i[3] => _~18.IN0 +i[3] => _~20.IN0 +i[3] => a~14.IN0 +i[3] => a~16.IN0 +i[3] => a~18.IN0 +i[3] => c~2.IN0 +i[3] => a~20.IN0 +i[3] => b~6.IN0 +i[3] => a~22.IN0 +i[3] => a~24.IN0 +a <= a~2.DB_MAX_OUTPUT_PORT_TYPE +b <= b~2.DB_MAX_OUTPUT_PORT_TYPE +c <= c~0.DB_MAX_OUTPUT_PORT_TYPE +d <= d~0.DB_MAX_OUTPUT_PORT_TYPE +e <= e~0.DB_MAX_OUTPUT_PORT_TYPE +f <= f~0.DB_MAX_OUTPUT_PORT_TYPE +g <= g~0.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_adder|encoder:inst20 +a => _~0.IN0 +a => _~9.IN0 +a => _~16.IN0 +a => _~23.IN0 +a => _~29.IN0 +a => _~36.IN0 +a => _~42.IN0 +a => _~48.IN0 +a => _~54.IN0 +a => _~63.IN0 +a => _~64.IN0 +a => _~70.IN0 +a => _~71.IN0 +a => _~77.IN0 +a => _~78.IN0 +a => _~82.IN0 +b => _~3.IN0 +b => _~10.IN0 +b => _~18.IN0 +b => _~24.IN0 +b => _~31.IN0 +b => _~37.IN0 +b => _~44.IN0 +b => _~49.IN0 +b => _~55.IN0 +b => _~60.IN0 +b => _~66.IN0 +b => _~69.IN0 +b => _~72.IN0 +b => _~75.IN0 +b => _~79.IN0 +b => _~81.IN0 +c => _~5.IN0 +c => _~12.IN0 +c => _~19.IN0 +c => _~25.IN0 +c => _~33.IN0 +c => _~39.IN0 +c => _~45.IN0 +c => _~50.IN0 +c => _~56.IN0 +c => _~61.IN0 +c => _~65.IN0 +c => _~68.IN0 +c => _~73.IN1 +c => _~76.IN1 +c => _~79.IN1 +c => _~81.IN1 +d => o[0]~5.IN0 +d => o[1]~7.IN0 +d => o[1]~9.IN0 +d => o[2]~11.IN0 +d => o[2]~13.IN0 +d => o[2]~15.IN0 +d => o[2]~17.IN0 +d => o[3]~19.IN0 +d => _~53.IN0 +d => sign~0.IN0 +sign <= sign~0.DB_MAX_OUTPUT_PORT_TYPE +o[0] <= o[0]~3.DB_MAX_OUTPUT_PORT_TYPE +o[1] <= o[1]~2.DB_MAX_OUTPUT_PORT_TYPE +o[2] <= o[2]~1.DB_MAX_OUTPUT_PORT_TYPE +o[3] <= o[3]~0.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_adder|74171:inst1 +Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE +CLRN => 16.ACLR +CLRN => 15.ACLR +CLRN => 8.ACLR +CLRN => 1.ACLR +CLK => 16.CLK +CLK => 15.CLK +CLK => 8.CLK +CLK => 1.CLK +D4 => 16.DATAIN +QN4 <= 19.DB_MAX_OUTPUT_PORT_TYPE +QN3 <= 12.DB_MAX_OUTPUT_PORT_TYPE +D3 => 15.DATAIN +Q3 <= 15.DB_MAX_OUTPUT_PORT_TYPE +Q2 <= 8.DB_MAX_OUTPUT_PORT_TYPE +D2 => 8.DATAIN +QN2 <= 11.DB_MAX_OUTPUT_PORT_TYPE +QN1 <= 5.DB_MAX_OUTPUT_PORT_TYPE +D1 => 1.DATAIN +Q1 <= 1.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_adder|7483:inst +C4 <= 83.DB_MAX_OUTPUT_PORT_TYPE +B4 => 22.IN0 +B4 => 26.IN0 +A4 => 22.IN1 +A4 => 26.IN1 +B3 => 21.IN0 +B3 => 25.IN0 +A3 => 21.IN1 +A3 => 25.IN1 +B2 => 20.IN0 +B2 => 24.IN0 +A2 => 20.IN1 +A2 => 24.IN1 +B1 => 19.IN0 +B1 => 23.IN0 +A1 => 19.IN1 +A1 => 23.IN1 +C0 => 17.IN0 +S4 <= 45.DB_MAX_OUTPUT_PORT_TYPE +S3 <= 44.DB_MAX_OUTPUT_PORT_TYPE +S2 <= 43.DB_MAX_OUTPUT_PORT_TYPE +S1 <= 42.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_adder|operator:inst21 +b1 => o1~1.IN1 +b1 => _~1.IN0 +b2 => o2~1.IN1 +b2 => _~2.IN0 +b3 => o3~1.IN1 +b3 => _~3.IN0 +b4 => o4~1.IN1 +b4 => _~4.IN0 +isAdd => o1~1.IN0 +isAdd => o2~1.IN0 +isAdd => o3~1.IN0 +isAdd => o4~1.IN0 +isAdd => _~0.IN0 +o1 <= o1~4.DB_MAX_OUTPUT_PORT_TYPE +o2 <= o2~4.DB_MAX_OUTPUT_PORT_TYPE +o3 <= o3~4.DB_MAX_OUTPUT_PORT_TYPE +o4 <= o4~4.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_adder|sign:inst19 +sign => g~1.IN0 +sign => _~1.IN0 +a <= +b <= +c <= +d <= +e <= +f <= +g <= g~2.DB_MAX_OUTPUT_PORT_TYPE + + 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literal 0 HcmV?d00001 diff --git a/YL_adder/db/YL_adder.map.kpt b/YL_adder/db/YL_adder.map.kpt new file mode 100644 index 0000000000000000000000000000000000000000..a3ccc51a310b2f7d550c7d052f03ed1dea468a2a GIT binary patch literal 396 zcmV;70dxMW4*>uG0001ZoYj_1Z-PJ&hVTB0$==Jdpy&ZOnDk)NLmQJeJ&{$$c0+~j zvKmeN@#RA)R@y*65odzjt&|8_cr*MG^<2e#|5va0=^aw2q>Lnn;tY1K}&(K^Wh&aTJN6cEV2p`{Dsgli>_*tv62B8N^bucYYZf>N0r#iPX`c*3~ZBpvL q<+IO6KIa1Ev(87p;RVXa&PTq%pUd}oZ~x`Y3-iAxzxNKZBfo8tiM|p5 literal 0 HcmV?d00001 diff --git a/YL_adder/db/YL_adder.map.logdb b/YL_adder/db/YL_adder.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/YL_adder/db/YL_adder.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/YL_adder/db/YL_adder.map.qmsg b/YL_adder/db/YL_adder.map.qmsg new file mode 100644 index 0000000..c62ddd6 --- /dev/null +++ b/YL_adder/db/YL_adder.map.qmsg @@ -0,0 +1,29 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588583127832 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588583127835 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:05:27 2020 " "Processing started: Mon May 04 17:05:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588583127835 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588583127835 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_adder -c YL_adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_adder -c YL_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588583127836 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588583128592 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_adder " "Found entity 1: YL_adder" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588583128687 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588583128687 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_7segment.tdf " "Can't analyze file -- file YL_7segment.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588583128697 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/ushio/onedrive/study/uol/elec211/exp28_decoder/yl_7segment_sign.tdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/ushio/onedrive/study/uol/elec211/exp28_decoder/yl_7segment_sign.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7segment " "Found entity 1: 7segment" { } { { "../Exp28_Decoder/YL_7segment_sign.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7segment_sign.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588583128704 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588583128704 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_7segment_sign.tdf " "Can't analyze file -- file YL_7segment_sign.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588583128714 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_sign_to_unsign.tdf " "Can't analyze file -- file YL_sign_to_unsign.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588583128727 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "operator.tdf 1 1 " "Found 1 design units, including 1 entities, in source file operator.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 operator " "Found entity 1: operator" { } { { "operator.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/operator.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588583128735 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588583128735 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "overflow.tdf 1 1 " "Found 1 design units, including 1 entities, in source file overflow.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 overflow " "Found entity 1: overflow" { } { { "overflow.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/overflow.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588583128750 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588583128750 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_adder " "Elaborating entity \"YL_adder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588583128835 ""} +{ "Warning" "WGDFX_PINS_OVERLAP_WARNING" "i\[3\] " "Pin \"i\[3\]\" overlaps another pin, block, or symbol" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 936 1112 64 "i\[3\]" "" } } } } } 0 275012 "Pin \"%1!s!\" overlaps another pin, block, or symbol" 0 0 "Quartus II" 0 -1 1588583128846 ""} +{ "Warning" "WSGN_SEARCH_FILE" "segment.tdf 1 1 " "Using design file segment.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 segment " "Found entity 1: segment" { } { { "segment.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/segment.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588583128914 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588583128914 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment segment:inst17 " "Elaborating entity \"segment\" for hierarchy \"segment:inst17\"" { } { { "YL_adder.bdf" "inst17" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 88 1024 1152 264 "inst17" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588583128917 ""} +{ "Warning" "WSGN_SEARCH_FILE" "encoder.tdf 1 1 " "Using design file encoder.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 encoder " "Found entity 1: encoder" { } { { "encoder.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/encoder.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588583128940 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588583128940 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "encoder encoder:inst20 " "Elaborating entity \"encoder\" for hierarchy \"encoder:inst20\"" { } { { "YL_adder.bdf" "inst20" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 800 928 224 "inst20" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588583128942 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74171 74171:inst1 " "Elaborating entity \"74171\" for hierarchy \"74171:inst1\"" { } { { "YL_adder.bdf" "inst1" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 96 632 736 256 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588583128968 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "74171:inst1 " "Elaborated megafunction instantiation \"74171:inst1\"" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 96 632 736 256 "inst1" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588583128970 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7483 7483:inst " "Elaborating entity \"7483\" for hierarchy \"7483:inst\"" { } { { "YL_adder.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 376 496 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588583129015 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "7483:inst " "Elaborated megafunction instantiation \"7483:inst\"" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 376 496 304 "inst" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588583129018 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "operator operator:inst21 " "Elaborating entity \"operator\" for hierarchy \"operator:inst21\"" { } { { "YL_adder.bdf" "inst21" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 312 184 320 456 "inst21" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588583129034 ""} +{ "Warning" "WSGN_SEARCH_FILE" "sign.tdf 1 1 " "Using design file sign.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sign " "Found entity 1: sign" { } { { "sign.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/sign.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588583129135 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588583129135 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign sign:inst19 " "Elaborating entity \"sign\" for hierarchy \"sign:inst19\"" { } { { "YL_adder.bdf" "inst19" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 360 1032 1152 536 "inst19" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588583129145 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "overflow overflow:inst23 " "Elaborating entity \"overflow\" for hierarchy \"overflow:inst23\"" { } { { "YL_adder.bdf" "inst23" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 400 728 848 512 "inst23" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588583129183 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_A2 GND " "Pin \"OUTPUT_A2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 344 1288 1464 360 "OUTPUT_A2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588583130064 "|YL_adder|OUTPUT_A2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_B2 GND " "Pin \"OUTPUT_B2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 376 1288 1464 392 "OUTPUT_B2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588583130064 "|YL_adder|OUTPUT_B2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_C2 GND " "Pin \"OUTPUT_C2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 408 1288 1464 424 "OUTPUT_C2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588583130064 "|YL_adder|OUTPUT_C2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_D2 GND " "Pin \"OUTPUT_D2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 440 1288 1464 456 "OUTPUT_D2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588583130064 "|YL_adder|OUTPUT_D2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_E2 GND " "Pin \"OUTPUT_E2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 472 1288 1464 488 "OUTPUT_E2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588583130064 "|YL_adder|OUTPUT_E2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_F2 GND " "Pin \"OUTPUT_F2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 504 1288 1464 520 "OUTPUT_F2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588583130064 "|YL_adder|OUTPUT_F2"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1588583130064 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1588583130676 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588583130676 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "53 " "Implemented 53 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1588583130869 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1588583130869 ""} { "Info" "ICUT_CUT_TM_LCELLS" "22 " "Implemented 22 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1588583130869 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1588583130869 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4608 " "Peak virtual memory: 4608 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588583130921 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:05:30 2020 " "Processing ended: Mon May 04 17:05:30 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588583130921 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588583130921 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588583130921 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588583130921 ""} diff --git a/YL_adder/db/YL_adder.map.rdb b/YL_adder/db/YL_adder.map.rdb new file mode 100644 index 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File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 1000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("isAdd") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("overflow") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("i") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("i[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +GROUP("INPUT_B") +{ + MEMBERS = "INPUT_B1", "INPUT_B2", "INPUT_B3", "INPUT_B4"; +} + +GROUP("INPUT_A") +{ + MEMBERS = "INPUT_A4", "INPUT_A3", "INPUT_A2", "INPUT_A1"; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("INPUT_A1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_A2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_A3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_A4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_B1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + NODE + { + REPEAT = 3; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_B2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("INPUT_B3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("INPUT_B4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 800.0; + LEVEL 1 FOR 200.0; + } + } +} + +TRANSITION_LIST("isAdd") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 50.0; + } +} + +TRANSITION_LIST("OUTPUT_A2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 50.0; + } +} + +TRANSITION_LIST("OUTPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 610.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 350.0; + } +} + +TRANSITION_LIST("OUTPUT_C2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + NODE + { + REPEAT = 2; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 40.0; + } + LEVEL 1 FOR 100.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + } + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 50.0; + } +} + +TRANSITION_LIST("OUTPUT_D2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 140.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 150.0; + } +} + +TRANSITION_LIST("OUTPUT_E2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + NODE + { + REPEAT = 2; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + } + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + } +} + +TRANSITION_LIST("OUTPUT_F2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 110.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + } +} + +TRANSITION_LIST("OUTPUT_G2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 310.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 190.0; + } +} + +TRANSITION_LIST("overflow") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 600.0; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("i[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 810.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 150.0; + } +} + +TRANSITION_LIST("i[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 150.0; + } +} + +TRANSITION_LIST("i[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + } + LEVEL 0 FOR 90.0; + } +} + +TRANSITION_LIST("i[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + } + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 50.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "isAdd"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 8; + TREE_LEVEL = 0; + CHILDREN = 9, 10, 11, 12; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "i"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 13; + TREE_LEVEL = 0; + CHILDREN = 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "i[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "overflow"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 27; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 28; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 29; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 30; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 31; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 32; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_adder/db/YL_adder.simfam b/YL_adder/db/YL_adder.simfam new file mode 100644 index 0000000..37dc84f --- /dev/null +++ b/YL_adder/db/YL_adder.simfam @@ -0,0 +1,2 @@ +BOF +EOF diff --git a/YL_adder/db/YL_adder.sld_design_entry.sci b/YL_adder/db/YL_adder.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/YL_adder/db/YL_adder.sld_design_entry_dsc.sci b/YL_adder/db/YL_adder.sld_design_entry_dsc.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/YL_adder/db/YL_adder.smart_action.txt b/YL_adder/db/YL_adder.smart_action.txt new file mode 100644 index 0000000..11b531f --- /dev/null +++ b/YL_adder/db/YL_adder.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/YL_adder/db/YL_adder.sta.qmsg b/YL_adder/db/YL_adder.sta.qmsg new file mode 100644 index 0000000..26165c9 --- /dev/null +++ b/YL_adder/db/YL_adder.sta.qmsg @@ -0,0 +1,31 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588583144002 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144003 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:05:43 2020 " "Processing started: Mon May 04 17:05:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588583144003 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588583144003 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_adder -c YL_adder " "Command: quartus_sta YL_adder -c YL_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588583144006 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588583144158 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588583144410 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588583144452 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588583144452 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_adder.sdc " "Synopsys Design Constraints File file not found: 'YL_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588583144578 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588583144580 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144585 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144585 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588583144591 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588583144633 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144634 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144647 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144657 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144661 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144667 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588583144668 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -6.519 clk " " -1.631 -6.519 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144672 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588583144672 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588583144701 ""} +{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588583144704 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144749 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144752 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144756 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588583144761 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588583144768 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144774 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144774 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -5.380 clk " " -1.380 -5.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588583144774 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588583144774 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588583144806 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588583144866 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588583144867 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4557 " "Peak virtual memory: 4557 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588583144963 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:05:44 2020 " "Processing ended: Mon May 04 17:05:44 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588583144963 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588583144963 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588583144963 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588583144963 ""} diff --git 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zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR>M#RM0Rm-^sX(9up%?<8{0hb+L5^I9 z3pCuIl!$+ui$sF8=?&f-xy2A%!C$AtB(yn~O|AJWLL6Uc8omFY)NT W^!wNEh2B465lTy7N&f%^;h5AFo+6z&Y}9PR?{67CA_8tw+}7VZx29_|6|5$*}@8SVw{Kin(a O8{9kG2izyz7u+{U)DIQ_ literal 0 HcmV?d00001 diff --git a/YL_adder/db/prev_cmp_YL_adder.qmsg b/YL_adder/db/prev_cmp_YL_adder.qmsg new file mode 100644 index 0000000..064837c --- /dev/null +++ b/YL_adder/db/prev_cmp_YL_adder.qmsg @@ -0,0 +1,125 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588582908770 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588582908771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:01:48 2020 " "Processing started: Mon May 04 17:01:48 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588582908771 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588582908771 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_adder -c YL_adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_adder -c YL_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588582908771 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588582909655 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_adder " "Found entity 1: YL_adder" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588582909757 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588582909757 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_7segment.tdf " "Can't analyze file -- file YL_7segment.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588582909770 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/ushio/onedrive/study/uol/elec211/exp28_decoder/yl_7segment_sign.tdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/ushio/onedrive/study/uol/elec211/exp28_decoder/yl_7segment_sign.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7segment " "Found entity 1: 7segment" { } { { "../Exp28_Decoder/YL_7segment_sign.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7segment_sign.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588582909796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588582909796 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_7segment_sign.tdf " "Can't analyze file -- file YL_7segment_sign.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588582909814 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "YL_sign_to_unsign.tdf " "Can't analyze file -- file YL_sign_to_unsign.tdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1588582909827 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "operator.tdf 1 1 " "Found 1 design units, including 1 entities, in source file operator.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 operator " "Found entity 1: operator" { } { { "operator.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/operator.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588582909836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588582909836 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "overflow.tdf 1 1 " "Found 1 design units, including 1 entities, in source file overflow.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 overflow " "Found entity 1: overflow" { } { { "overflow.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/overflow.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588582909841 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588582909841 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_adder " "Elaborating entity \"YL_adder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588582909906 ""} +{ "Warning" "WGDFX_PINS_OVERLAP_WARNING" "i\[3\] " "Pin \"i\[3\]\" overlaps another pin, block, or symbol" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 936 1112 64 "i\[3\]" "" } } } } } 0 275012 "Pin \"%1!s!\" overlaps another pin, block, or symbol" 0 0 "Quartus II" 0 -1 1588582909914 ""} +{ "Warning" "WSGN_SEARCH_FILE" "segment.tdf 1 1 " "Using design file segment.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 segment " "Found entity 1: segment" { } { { "segment.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/segment.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588582909953 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588582909953 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segment segment:inst17 " "Elaborating entity \"segment\" for hierarchy \"segment:inst17\"" { } { { "YL_adder.bdf" "inst17" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 88 1024 1152 264 "inst17" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588582909956 ""} +{ "Warning" "WSGN_SEARCH_FILE" "encoder.tdf 1 1 " "Using design file encoder.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 encoder " "Found entity 1: encoder" { } { { "encoder.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/encoder.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588582909983 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588582909983 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "encoder encoder:inst20 " "Elaborating entity \"encoder\" for hierarchy \"encoder:inst20\"" { } { { "YL_adder.bdf" "inst20" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 800 928 224 "inst20" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588582909988 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74171 74171:inst1 " "Elaborating entity \"74171\" for hierarchy \"74171:inst1\"" { } { { "YL_adder.bdf" "inst1" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 96 632 736 256 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588582910056 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "74171:inst1 " "Elaborated megafunction instantiation \"74171:inst1\"" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 96 632 736 256 "inst1" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588582910061 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7483 7483:inst " "Elaborating entity \"7483\" for hierarchy \"7483:inst\"" { } { { "YL_adder.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 376 496 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588582910141 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "7483:inst " "Elaborated megafunction instantiation \"7483:inst\"" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 112 376 496 304 "inst" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588582910147 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "operator operator:inst21 " "Elaborating entity \"operator\" for hierarchy \"operator:inst21\"" { } { { "YL_adder.bdf" "inst21" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 312 184 320 456 "inst21" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588582910154 ""} +{ "Warning" "WSGN_SEARCH_FILE" "sign.tdf 1 1 " "Using design file sign.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sign " "Found entity 1: sign" { } { { "sign.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/sign.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588582910202 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1588582910202 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign sign:inst19 " "Elaborating entity \"sign\" for hierarchy \"sign:inst19\"" { } { { "YL_adder.bdf" "inst19" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 360 1032 1152 536 "inst19" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588582910205 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "overflow overflow:inst23 " "Elaborating entity \"overflow\" for hierarchy \"overflow:inst23\"" { } { { "YL_adder.bdf" "inst23" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 400 728 848 512 "inst23" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588582910215 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_A2 GND " "Pin \"OUTPUT_A2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 344 1288 1464 360 "OUTPUT_A2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588582910881 "|YL_adder|OUTPUT_A2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_B2 GND " "Pin \"OUTPUT_B2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 376 1288 1464 392 "OUTPUT_B2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588582910881 "|YL_adder|OUTPUT_B2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_C2 GND " "Pin \"OUTPUT_C2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 408 1288 1464 424 "OUTPUT_C2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588582910881 "|YL_adder|OUTPUT_C2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_D2 GND " "Pin \"OUTPUT_D2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 440 1288 1464 456 "OUTPUT_D2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588582910881 "|YL_adder|OUTPUT_D2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_E2 GND " "Pin \"OUTPUT_E2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 472 1288 1464 488 "OUTPUT_E2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588582910881 "|YL_adder|OUTPUT_E2"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUTPUT_F2 GND " "Pin \"OUTPUT_F2\" is stuck at GND" { } { { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 504 1288 1464 520 "OUTPUT_F2" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1588582910881 "|YL_adder|OUTPUT_F2"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1588582910881 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1588582911280 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588582911280 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "54 " "Implemented 54 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1588582911394 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1588582911394 ""} { "Info" "ICUT_CUT_TM_LCELLS" "23 " "Implemented 23 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1588582911394 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1588582911394 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4608 " "Peak virtual memory: 4608 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588582911456 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:01:51 2020 " "Processing ended: Mon May 04 17:01:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588582911456 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588582911456 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588582911456 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588582911456 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588582913153 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588582913154 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:01:52 2020 " "Processing started: Mon May 04 17:01:52 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588582913154 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1588582913154 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder " "Command: quartus_fit --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1588582913155 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1588582913304 ""} +{ "Info" "0" "" "Project = YL_adder" { } { } 0 0 "Project = YL_adder" 0 0 "Fitter" 0 0 1588582913305 ""} +{ "Info" "0" "" "Revision = YL_adder" { } { } 0 0 "Revision = YL_adder" 0 0 "Fitter" 0 0 1588582913305 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1588582913430 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "YL_adder EP2C20F484C7 " "Selected device EP2C20F484C7 for design \"YL_adder\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1588582913441 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588582913494 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588582913494 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1588582913597 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1588582913623 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Device EP2C15AF484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588582914418 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Device EP2C35F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588582914418 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Device EP2C50F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588582914418 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1588582914418 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588582914421 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 93 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588582914421 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 94 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588582914421 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1588582914421 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "31 31 " "No exact pin location assignment(s) for 31 pins of 31 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_A " "Pin OUTPUT_A not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_A } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 72 1288 1464 88 "OUTPUT_A" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_A } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 15 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[3\] " "Pin i\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[3] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 11 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[2\] " "Pin i\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[2] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 12 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[1\] " "Pin i\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[1] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 13 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "i\[0\] " "Pin i\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { i[0] } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { -8 952 1128 8 "i" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 14 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_B " "Pin OUTPUT_B not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_B } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 104 1288 1464 120 "OUTPUT_B" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_B } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 27 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_C " "Pin OUTPUT_C not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_C } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 136 1288 1464 152 "OUTPUT_C" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_C } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 28 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_D " "Pin OUTPUT_D not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_D } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 168 1288 1464 184 "OUTPUT_D" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_D } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 29 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_E " "Pin OUTPUT_E not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_E } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 200 1288 1464 216 "OUTPUT_E" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_E } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 30 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_F " "Pin OUTPUT_F not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_F } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 232 1288 1464 248 "OUTPUT_F" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_F } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 31 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_G " "Pin OUTPUT_G not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_G } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 264 1288 1464 280 "OUTPUT_G" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_G } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 32 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_A2 " "Pin OUTPUT_A2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_A2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 344 1288 1464 360 "OUTPUT_A2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_A2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 33 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_B2 " "Pin OUTPUT_B2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_B2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 376 1288 1464 392 "OUTPUT_B2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 34 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_C2 " "Pin OUTPUT_C2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_C2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 408 1288 1464 424 "OUTPUT_C2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_C2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 35 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_D2 " "Pin OUTPUT_D2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_D2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 440 1288 1464 456 "OUTPUT_D2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_D2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 36 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_E2 " "Pin OUTPUT_E2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_E2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 472 1288 1464 488 "OUTPUT_E2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_E2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 37 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_F2 " "Pin OUTPUT_F2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_F2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 504 1288 1464 520 "OUTPUT_F2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_F2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 38 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OUTPUT_G2 " "Pin OUTPUT_G2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { OUTPUT_G2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 536 1288 1464 552 "OUTPUT_G2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OUTPUT_G2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 39 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "overflow " "Pin overflow not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { overflow } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 424 848 1024 440 "overflow" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { overflow } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 40 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_name1 " "Pin pin_name1 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { pin_name1 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 792 968 64 "pin_name1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pin_name1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 41 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A4 " "Pin INPUT_A4 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A4 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 208 24 192 224 "INPUT_A4" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 25 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B3 " "Pin INPUT_B3 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B3 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 368 16 184 384 "INPUT_B3" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 19 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isAdd " "Pin isAdd not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { isAdd } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 432 400 568 448 "isAdd" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { isAdd } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 21 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A3 " "Pin INPUT_A3 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A3 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 192 24 192 208 "INPUT_A3" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 24 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B2 " "Pin INPUT_B2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 352 16 184 368 "INPUT_B2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 18 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B1 " "Pin INPUT_B1 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B1 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 336 16 184 352 "INPUT_B1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 17 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A1 " "Pin INPUT_A1 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A1 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 160 16 192 176 "INPUT_A1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 22 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_A2 " "Pin INPUT_A2 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_A2 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 176 24 192 192 "INPUT_A2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_A2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 23 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INPUT_B4 " "Pin INPUT_B4 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { INPUT_B4 } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 384 8 184 400 "INPUT_B4" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INPUT_B4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 20 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 64 240 64 "clk" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 26 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "reset " "Pin reset not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { reset } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 24 64 240 40 "reset" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 16 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588582914540 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1588582914540 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_adder.sdc " "Synopsys Design Constraints File file not found: 'YL_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1588582914693 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1588582914693 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1588582914695 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588582914725 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 48 64 240 64 "clk" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 26 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588582914725 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) " "Automatically promoted node reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588582914726 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { reset } } } { "YL_adder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf" { { 24 64 240 40 "reset" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 0 { 0 ""} 0 16 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588582914726 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1588582914799 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588582914799 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588582914800 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588582914802 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588582914805 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1588582914805 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1588582914805 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1588582914806 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1588582914806 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1588582914807 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1588582914807 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "29 unused 3.3V 9 20 0 " "Number of I/O pins in group: 29 (unused VREF, 3.3V VCCIO, 9 input, 20 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1588582914811 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1588582914811 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1588582914811 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 39 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 31 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 39 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 35 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588582914814 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1588582914814 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1588582914814 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588582914840 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1588582917172 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588582917253 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1588582917268 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1588582917497 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588582917497 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1588582917553 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X38_Y14 X50_Y27 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y14 to location X50_Y27" { } { { "loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y14 to location X50_Y27"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y14 to location X50_Y27"} 38 14 13 14 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1588582918894 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1588582918894 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588582918979 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1588582918983 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1588582918983 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1588582918983 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.16 " "Total time spent on timing analysis during the Fitter is 0.16 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1588582918994 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588582918997 ""} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "20 " "Found 20 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_A 0 " "Pin \"OUTPUT_A\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[3\] 0 " "Pin \"i\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[2\] 0 " "Pin \"i\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[1\] 0 " "Pin \"i\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "i\[0\] 0 " "Pin \"i\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_B 0 " "Pin \"OUTPUT_B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_C 0 " "Pin \"OUTPUT_C\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_D 0 " "Pin \"OUTPUT_D\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_E 0 " "Pin \"OUTPUT_E\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_F 0 " "Pin \"OUTPUT_F\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_G 0 " "Pin \"OUTPUT_G\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_A2 0 " "Pin \"OUTPUT_A2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_B2 0 " "Pin \"OUTPUT_B2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_C2 0 " "Pin \"OUTPUT_C2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_D2 0 " "Pin \"OUTPUT_D2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_E2 0 " "Pin \"OUTPUT_E2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_F2 0 " "Pin \"OUTPUT_F2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OUTPUT_G2 0 " "Pin \"OUTPUT_G2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "overflow 0 " "Pin \"overflow\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pin_name1 0 " "Pin \"pin_name1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588582919003 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1588582919003 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588582919141 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588582919160 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588582919261 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588582919534 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1588582919595 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.fit.smsg " "Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1588582919774 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4848 " "Peak virtual memory: 4848 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588582920140 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:02:00 2020 " "Processing ended: Mon May 04 17:02:00 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588582920140 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588582920140 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588582920140 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1588582920140 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1588582921640 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588582921641 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:02:01 2020 " "Processing started: Mon May 04 17:02:01 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588582921641 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1588582921641 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1588582921641 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1588582923039 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1588582923078 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4552 " "Peak virtual memory: 4552 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588582923901 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 17:02:03 2020 " "Processing ended: Mon May 04 17:02:03 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588582923901 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588582923901 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588582923901 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1588582923901 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1588582924593 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1588582925546 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588582925547 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 17:02:04 2020 " "Processing started: Mon May 04 17:02:04 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588582925547 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588582925547 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_adder -c YL_adder " "Command: quartus_sta YL_adder -c YL_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588582925548 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588582925703 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588582925967 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588582926005 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588582926005 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_adder.sdc " "Synopsys Design Constraints File file not found: 'YL_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588582926186 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588582926186 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588582926187 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588582926187 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588582926190 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588582926224 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588582926225 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588582926242 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588582926250 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588582926254 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588582926261 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588582926262 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588582926279 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588582926279 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -6.519 clk " " -1.631 -6.519 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588582926279 ""} } { } 0 332146 "Worst-case %1!s! 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was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588582929410 ""} diff --git a/YL_adder/encoder.bsf b/YL_adder/encoder.bsf new file mode 100644 index 0000000..ec1b833 --- /dev/null +++ b/YL_adder/encoder.bsf @@ -0,0 +1,71 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 144 128) + (text "encoder" (rect 5 0 36 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "a" (rect 0 0 4 12)(font "Arial" )) + (text "a" (rect 21 27 25 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "b" (rect 0 0 4 12)(font "Arial" )) + (text "b" (rect 21 43 25 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "c" (rect 0 0 4 12)(font "Arial" )) + (text "c" (rect 21 59 25 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "d" (rect 0 0 4 12)(font "Arial" )) + (text "d" (rect 21 75 25 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 128 32) + (output) + (text "sign" (rect 0 0 15 12)(font "Arial" )) + (text "sign" (rect 92 27 107 39)(font "Arial" )) + (line (pt 128 32)(pt 112 32)(line_width 1)) + ) + (port + (pt 128 48) + (output) + (text "o[3..0]" (rect 0 0 24 12)(font "Arial" )) + (text "o[3..0]" (rect 83 43 107 55)(font "Arial" )) + (line (pt 128 48)(pt 112 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 112 96)(line_width 1)) + ) +) diff --git a/YL_adder/encoder.tdf b/YL_adder/encoder.tdf new file mode 100644 index 0000000..81f80fc --- /dev/null +++ b/YL_adder/encoder.tdf @@ -0,0 +1,36 @@ +SUBDESIGN encoder +( + a, b, c, d : input; + sign, o[3..0] : output; +) +BEGIN + + IF d THEN + sign = VCC; + TABLE + !a, !b, !c => o[3..0]; + 0, 0, 0 => 1; + 1, 0, 0 => 2; + 0, 1, 0 => 3; + 1, 1, 0 => 4; + 0, 0, 1 => 5; + 1, 0, 1 => 6; + 0, 1, 1 => 7; + 1, 1, 1 => 8; + END TABLE; + ELSE + sign = GND; + TABLE + a, b, c => o[3..0]; + 0, 0, 0 => 0; + 1, 0, 0 => 1; + 0, 1, 0 => 2; + 1, 1, 0 => 3; + 0, 0, 1 => 4; + 1, 0, 1 => 5; + 0, 1, 1 => 6; + 1, 1, 1 => 7; + END TABLE; + END IF; + +END; \ No newline at end of file diff --git a/YL_adder/incremental_db/README b/YL_adder/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/YL_adder/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/YL_adder/incremental_db/compiled_partitions/YL_adder.db_info b/YL_adder/incremental_db/compiled_partitions/YL_adder.db_info new file mode 100644 index 0000000..ea56a7d --- /dev/null +++ b/YL_adder/incremental_db/compiled_partitions/YL_adder.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Mon May 04 14:59:00 2020 diff --git a/YL_adder/incremental_db/compiled_partitions/YL_adder.root_partition.cmp.ammdb b/YL_adder/incremental_db/compiled_partitions/YL_adder.root_partition.cmp.ammdb new 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 152 160) + (text "operator" (rect 5 0 38 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "b1" (rect 0 0 8 12)(font "Arial" )) + (text "b1" (rect 21 27 29 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "b2" (rect 0 0 9 12)(font "Arial" )) + (text "b2" (rect 21 43 30 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "b3" (rect 0 0 9 12)(font "Arial" )) + (text "b3" (rect 21 59 30 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "b4" (rect 0 0 10 12)(font "Arial" )) + (text "b4" (rect 21 75 31 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "isAdd" (rect 0 0 23 12)(font "Arial" )) + (text "isAdd" (rect 21 91 44 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 136 32) + (output) + (text "o1" (rect 0 0 8 12)(font "Arial" )) + (text "o1" (rect 107 27 115 39)(font "Arial" )) + (line (pt 136 32)(pt 120 32)(line_width 1)) + ) + (port + (pt 136 48) + (output) + (text "o2" (rect 0 0 9 12)(font "Arial" )) + (text "o2" (rect 106 43 115 55)(font "Arial" )) + (line (pt 136 48)(pt 120 48)(line_width 1)) + ) + (port + (pt 136 64) + (output) + (text "o3" (rect 0 0 9 12)(font "Arial" )) + (text "o3" (rect 106 59 115 71)(font "Arial" )) + (line (pt 136 64)(pt 120 64)(line_width 1)) + ) + (port + (pt 136 80) + (output) + (text "o4" (rect 0 0 10 12)(font "Arial" )) + (text "o4" (rect 105 75 115 87)(font "Arial" )) + (line (pt 136 80)(pt 120 80)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 120 128)(line_width 1)) + ) +) diff --git a/YL_adder/operator.tdf b/YL_adder/operator.tdf new file mode 100644 index 0000000..d31f7d6 --- /dev/null +++ b/YL_adder/operator.tdf @@ -0,0 +1,21 @@ +SUBDESIGN operator +( + b1, b2, b3, b4 : input; + isAdd : input; + o1, o2, o3, o4 : output; +) +BEGIN + + if isAdd THEN + o1 = b1; + o2 = b2; + o3 = b3; + o4 = b4; + ELSE + o1 = !b1; + o2 = !b2; + o3 = !b3; + o4 = !b4; + END IF; + +END; \ No newline at end of file diff --git a/YL_adder/operator.tdf.bak b/YL_adder/operator.tdf.bak new file mode 100644 index 0000000..e93e366 --- /dev/null +++ b/YL_adder/operator.tdf.bak @@ -0,0 +1,5 @@ +SUBDESIGN operator +( + a, b, c, d : input; + oa, ob, oc, +) \ No newline at end of file diff --git a/YL_adder/output_files/YL_adder.asm.rpt b/YL_adder/output_files/YL_adder.asm.rpt new file mode 100644 index 0000000..3f0c0ca --- /dev/null +++ b/YL_adder/output_files/YL_adder.asm.rpt @@ -0,0 +1,130 @@ +Assembler report for YL_adder +Mon May 04 17:05:42 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.sof + 6. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon May 04 17:05:42 2020 ; +; Revision Name ; YL_adder ; +; Top-level Entity Name ; YL_adder ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.sof ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.pof ; ++------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.sof ; ++----------------+---------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------------------------------+ +; Device ; EP2C20F484C7 ; +; JTAG usercode ; 0x001B4ADE ; +; Checksum ; 0x001B4ADE ; ++----------------+---------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.pof ; ++--------------------+-----------------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+-----------------------------------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1DD8E9F4 ; +; Compression Ratio ; 3 ; ++--------------------+-----------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 17:05:40 2020 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4552 megabytes + Info: Processing ended: Mon May 04 17:05:42 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_adder/output_files/YL_adder.done b/YL_adder/output_files/YL_adder.done new file mode 100644 index 0000000..4f027f8 --- /dev/null +++ b/YL_adder/output_files/YL_adder.done @@ -0,0 +1 @@ +Mon May 04 17:05:47 2020 diff --git a/YL_adder/output_files/YL_adder.eda.rpt b/YL_adder/output_files/YL_adder.eda.rpt new file mode 100644 index 0000000..80c0a47 --- /dev/null +++ b/YL_adder/output_files/YL_adder.eda.rpt @@ -0,0 +1,96 @@ +EDA Netlist Writer report for YL_adder +Mon May 04 17:05:47 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Mon May 04 17:05:47 2020 ; +; Revision Name ; YL_adder ; +; Top-level Entity Name ; YL_adder ; +; Family ; Cyclone II ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++--------------------------------------------------------------------------------------------+ +; Generated Files ; ++--------------------------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/simulation/modelsim/YL_adder.vo ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/simulation/modelsim/YL_adder_fast.vo ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/simulation/modelsim/YL_adder_v.sdo ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/simulation/modelsim/YL_adder_v_fast.sdo ; ++--------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit EDA Netlist Writer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 17:05:46 2020 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder +Info (204026): Generated files "YL_adder.vo", "YL_adder_fast.vo", "YL_adder_v.sdo" and "YL_adder_v_fast.sdo" in directory "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4529 megabytes + Info: Processing ended: Mon May 04 17:05:47 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/YL_adder/output_files/YL_adder.fit.rpt b/YL_adder/output_files/YL_adder.fit.rpt new file mode 100644 index 0000000..02462fc --- /dev/null +++ b/YL_adder/output_files/YL_adder.fit.rpt @@ -0,0 +1,1325 @@ +Fitter report for YL_adder +Mon May 04 17:05:39 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. Output Pin Default Load For Reported TCO + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Control Signals + 20. Global & Other Fast Signals + 21. Non-Global High Fan-Out Signals + 22. Other Routing Usage Summary + 23. LAB Logic Elements + 24. LAB-wide Signals + 25. LAB Signals Sourced + 26. LAB Signals Sourced Out + 27. LAB Distinct Inputs + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Mon May 04 17:05:38 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_adder ; +; Top-level Entity Name ; YL_adder ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 22 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 22 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 4 / 18,752 ( < 1 % ) ; +; Total registers ; 4 ; +; Total pins ; 31 / 315 ( 10 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C20F484C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 63 ( 0.00 % ) ; +; -- Achieved ; 0 / 63 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 60 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 22 / 18,752 ( < 1 % ) ; +; -- Combinational with no register ; 18 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 4 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 12 ; +; -- 3 input functions ; 7 ; +; -- <=2 input functions ; 3 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 22 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 4 / 19,649 ( < 1 % ) ; +; -- Dedicated logic registers ; 4 / 18,752 ( < 1 % ) ; +; -- I/O registers ; 0 / 897 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 1,172 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 31 / 315 ( 10 % ) ; +; -- Clock pins ; 2 / 8 ( 25 % ) ; +; ; ; +; Global signals ; 2 ; +; M4Ks ; 0 / 52 ( 0 % ) ; +; Total block memory bits ; 0 / 239,616 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 12 ; +; Highest non-global fan-out ; 12 ; +; Total fan-out ; 103 ; +; Average fan-out ; 1.66 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 22 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; -- Combinational with no register ; 18 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 4 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 12 ; 0 ; +; -- 3 input functions ; 7 ; 0 ; +; -- <=2 input functions ; 3 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 22 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 4 ; 0 ; +; -- Dedicated logic registers ; 4 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 1172 ( < 1 % ) ; 0 / 1172 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 31 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; 0 / 52 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 2 / 20 ( 10 % ) ; 0 / 20 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 103 ; 0 ; +; -- Registered Connections ; 40 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 11 ; 0 ; +; -- Output Ports ; 20 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; INPUT_A1 ; H14 ; 4 ; 42 ; 27 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_A2 ; L1 ; 2 ; 0 ; 13 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_A3 ; D16 ; 4 ; 42 ; 27 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_A4 ; D20 ; 5 ; 50 ; 25 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_B1 ; G16 ; 4 ; 44 ; 27 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_B2 ; E15 ; 4 ; 42 ; 27 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_B3 ; D14 ; 4 ; 35 ; 27 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; INPUT_B4 ; L2 ; 2 ; 0 ; 13 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; clk ; M1 ; 1 ; 0 ; 13 ; 2 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; isAdd ; B18 ; 4 ; 46 ; 27 ; 2 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; reset ; M2 ; 1 ; 0 ; 13 ; 3 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; OUTPUT_A ; A17 ; 4 ; 37 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_A2 ; P18 ; 6 ; 50 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_B ; H13 ; 4 ; 37 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_B2 ; A19 ; 4 ; 46 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_C ; B17 ; 4 ; 37 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_C2 ; Y13 ; 7 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_D ; F13 ; 4 ; 35 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_D2 ; AA17 ; 7 ; 37 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_E ; D15 ; 4 ; 39 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_E2 ; V9 ; 8 ; 9 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_F ; E14 ; 4 ; 35 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_F2 ; R10 ; 8 ; 13 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_G ; F14 ; 4 ; 35 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_G2 ; F15 ; 4 ; 39 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; i[0] ; H15 ; 4 ; 44 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; i[1] ; C16 ; 4 ; 44 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; i[2] ; G15 ; 4 ; 39 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; i[3] ; C14 ; 4 ; 39 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; overflow ; A18 ; 4 ; 46 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; pin_name1 ; J14 ; 4 ; 42 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 2 / 41 ( 5 % ) ; 3.3V ; -- ; +; 2 ; 4 / 33 ( 12 % ) ; 3.3V ; -- ; +; 3 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; +; 4 ; 21 / 40 ( 53 % ) ; 3.3V ; -- ; +; 5 ; 1 / 39 ( 3 % ) ; 3.3V ; -- ; +; 6 ; 2 / 36 ( 6 % ) ; 3.3V ; -- ; +; 7 ; 2 / 40 ( 5 % ) ; 3.3V ; -- ; +; 8 ; 2 / 43 ( 5 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 306 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A8 ; 304 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A9 ; 298 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A10 ; 293 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A11 ; 287 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 265 ; 4 ; OUTPUT_A ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; A18 ; 251 ; 4 ; overflow ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; A19 ; 249 ; 4 ; OUTPUT_B2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 82 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA4 ; 85 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA5 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA6 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA7 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA11 ; 122 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 130 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 144 ; 7 ; OUTPUT_D2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 83 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB4 ; 84 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB5 ; 88 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB6 ; 96 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB7 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB12 ; 127 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB13 ; 129 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 305 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B8 ; 303 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B9 ; 297 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B10 ; 292 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B11 ; 286 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B14 ; 278 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 264 ; 4 ; OUTPUT_C ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B18 ; 250 ; 4 ; isAdd ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C7 ; 315 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; 310 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C10 ; 296 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C14 ; 260 ; 4 ; i[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C16 ; 254 ; 4 ; i[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D2 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D5 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D6 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 302 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 289 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 267 ; 4 ; INPUT_B3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; D15 ; 259 ; 4 ; OUTPUT_E ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; D16 ; 255 ; 4 ; INPUT_A3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D20 ; 241 ; 5 ; INPUT_A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; 266 ; 4 ; OUTPUT_F ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; E15 ; 256 ; 4 ; INPUT_B2 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F4 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 276 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F13 ; 269 ; 4 ; OUTPUT_D ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; F14 ; 268 ; 4 ; OUTPUT_G ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; F15 ; 262 ; 4 ; OUTPUT_G2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 261 ; 4 ; i[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; G16 ; 252 ; 4 ; INPUT_B1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H2 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; H4 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H6 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 274 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; 263 ; 4 ; OUTPUT_B ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; H14 ; 257 ; 4 ; INPUT_A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; H15 ; 253 ; 4 ; i[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J1 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J2 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; 258 ; 4 ; pin_name1 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; 38 ; 2 ; INPUT_A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L2 ; 39 ; 2 ; INPUT_B4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M1 ; 41 ; 1 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M2 ; 42 ; 1 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P6 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 187 ; 6 ; OUTPUT_A2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R1 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R2 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R5 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R6 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R7 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R8 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R10 ; 108 ; 8 ; OUTPUT_F2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; R11 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; R21 ; 190 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R22 ; 191 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T1 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T2 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T3 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T5 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T6 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T7 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T8 ; 90 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T12 ; 131 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T15 ; 147 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 188 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T22 ; 189 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U1 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U2 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U3 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U4 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U8 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U21 ; 182 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U22 ; 183 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V9 ; 101 ; 8 ; OUTPUT_E2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 180 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 181 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W2 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W7 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W8 ; 100 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W9 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W21 ; 174 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; 175 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y3 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y4 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y5 ; 86 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y6 ; 87 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y7 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y13 ; 133 ; 7 ; OUTPUT_C2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y21 ; 178 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 179 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------+--------------+ +; |YL_adder ; 22 (0) ; 4 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 ; 0 ; 18 (0) ; 0 (0) ; 4 (0) ; |YL_adder ; work ; +; |74171:inst1| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |YL_adder|74171:inst1 ; work ; +; |7483:inst| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 4 (4) ; |YL_adder|7483:inst ; work ; +; |encoder:inst20| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |YL_adder|encoder:inst20 ; work ; +; |operator:inst21| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |YL_adder|operator:inst21 ; work ; +; |overflow:inst23| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |YL_adder|overflow:inst23 ; work ; +; |segment:inst17| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |YL_adder|segment:inst17 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-----------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++-----------+----------+---------------+---------------+-----------------------+-----+ +; OUTPUT_A ; Output ; -- ; -- ; -- ; -- ; +; i[3] ; Output ; -- ; -- ; -- ; -- ; +; i[2] ; Output ; -- ; -- ; -- ; -- ; +; i[1] ; Output ; -- ; -- ; -- ; -- ; +; i[0] ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_B ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_C ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_D ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_E ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_F ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_G ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_A2 ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_B2 ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_C2 ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_D2 ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_E2 ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_F2 ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_G2 ; Output ; -- ; -- ; -- ; -- ; +; overflow ; Output ; -- ; -- ; -- ; -- ; +; pin_name1 ; Output ; -- ; -- ; -- ; -- ; +; INPUT_A4 ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; INPUT_B3 ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; isAdd ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_A3 ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_B2 ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_B1 ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_A1 ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; INPUT_A2 ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; INPUT_B4 ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; clk ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; reset ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; ++-----------+----------+---------------+---------------+-----------------------+-----+ + + ++-----------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------+-------------------+---------+ +; INPUT_A4 ; ; ; +; - overflow:inst23|v~1 ; 0 ; 6 ; +; - 7483:inst|45 ; 0 ; 6 ; +; INPUT_B3 ; ; ; +; - 7483:inst|21~0 ; 0 ; 6 ; +; - 7483:inst|25 ; 0 ; 6 ; +; - 7483:inst|44~0 ; 0 ; 6 ; +; isAdd ; ; ; +; - 7483:inst|21~0 ; 1 ; 6 ; +; - operator:inst21|o2~2 ; 1 ; 6 ; +; - 7483:inst|18~0 ; 1 ; 6 ; +; - 7483:inst|25 ; 1 ; 6 ; +; - operator:inst21|o4~2 ; 1 ; 6 ; +; - 7483:inst|44~0 ; 1 ; 6 ; +; - 7483:inst|43 ; 1 ; 6 ; +; INPUT_A3 ; ; ; +; - 7483:inst|21~0 ; 0 ; 6 ; +; - 7483:inst|25 ; 0 ; 6 ; +; - 7483:inst|44~0 ; 0 ; 6 ; +; INPUT_B2 ; ; ; +; - operator:inst21|o2~2 ; 0 ; 6 ; +; - 7483:inst|43 ; 0 ; 6 ; +; INPUT_B1 ; ; ; +; - 7483:inst|18~0 ; 1 ; 6 ; +; - 7483:inst|42 ; 1 ; 6 ; +; INPUT_A1 ; ; ; +; - 7483:inst|18~0 ; 0 ; 6 ; +; - 7483:inst|42 ; 0 ; 6 ; +; INPUT_A2 ; ; ; +; INPUT_B4 ; ; ; +; clk ; ; ; +; reset ; ; ; ++-----------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 4 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; reset ; PIN_M2 ; 4 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 4 ; Global Clock ; GCLK3 ; -- ; +; reset ; PIN_M2 ; 4 ; Global Clock ; GCLK1 ; -- ; ++-------+----------+---------+----------------------+------------------+---------------------------+ + + ++----------------------------------+ +; Non-Global High Fan-Out Signals ; ++------------------------+---------+ +; Name ; Fan-Out ; ++------------------------+---------+ +; 74171:inst1|1 ; 12 ; +; 74171:inst1|8 ; 10 ; +; 74171:inst1|16 ; 9 ; +; 74171:inst1|15 ; 9 ; +; isAdd ; 7 ; +; INPUT_A2 ; 3 ; +; INPUT_A3 ; 3 ; +; INPUT_B3 ; 3 ; +; 7483:inst|18~0 ; 3 ; +; INPUT_A1 ; 2 ; +; INPUT_B1 ; 2 ; +; INPUT_B2 ; 2 ; +; INPUT_A4 ; 2 ; +; operator:inst21|o4~2 ; 2 ; +; 7483:inst|1~0 ; 2 ; +; operator:inst21|o2~2 ; 2 ; +; 7483:inst|21~0 ; 2 ; +; INPUT_B4 ; 1 ; +; 7483:inst|43 ; 1 ; +; 7483:inst|42 ; 1 ; +; 7483:inst|45 ; 1 ; +; 7483:inst|44 ; 1 ; +; 7483:inst|44~0 ; 1 ; +; overflow:inst23|v~1 ; 1 ; +; 7483:inst|25 ; 1 ; +; segment:inst17|g~0 ; 1 ; +; segment:inst17|f~0 ; 1 ; +; segment:inst17|e~0 ; 1 ; +; segment:inst17|d~0 ; 1 ; +; segment:inst17|c~1 ; 1 ; +; segment:inst17|b~3 ; 1 ; +; encoder:inst20|o[1]~17 ; 1 ; +; encoder:inst20|o[2]~16 ; 1 ; +; encoder:inst20|o[3]~15 ; 1 ; +; segment:inst17|a~12 ; 1 ; ++------------------------+---------+ + + ++-----------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-----------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-----------------------+ +; Block interconnects ; 29 / 54,004 ( < 1 % ) ; +; C16 interconnects ; 2 / 2,100 ( < 1 % ) ; +; C4 interconnects ; 21 / 36,000 ( < 1 % ) ; +; Direct links ; 1 / 54,004 ( < 1 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Local interconnects ; 7 / 18,752 ( < 1 % ) ; +; R24 interconnects ; 4 / 1,900 ( < 1 % ) ; +; R4 interconnects ; 20 / 46,920 ( < 1 % ) ; ++-----------------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 11.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 2) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 1 ; +; 1 Clock ; 1 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 13.00) ; Number of LABs (Total = 2) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 7.50) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 7.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP2C20F484C7 for design "YL_adder" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP2C15AF484C7 is compatible + Info (176445): Device EP2C35F484C7 is compatible + Info (176445): Device EP2C50F484C7 is compatible +Info (169124): Fitter converted 3 user pins into dedicated programming pins + Info (169125): Pin ~ASDO~ is reserved at location C4 + Info (169125): Pin ~nCSO~ is reserved at location C3 + Info (169125): Pin ~LVDS91p/nCEO~ is reserved at location W20 +Critical Warning (169085): No exact pin location assignment(s) for 31 pins of 31 total pins + Info (169086): Pin OUTPUT_A not assigned to an exact location on the device + Info (169086): Pin i[3] not assigned to an exact location on the device + Info (169086): Pin i[2] not assigned to an exact location on the device + Info (169086): Pin i[1] not assigned to an exact location on the device + Info (169086): Pin i[0] not assigned to an exact location on the device + Info (169086): Pin OUTPUT_B not assigned to an exact location on the device + Info (169086): Pin OUTPUT_C not assigned to an exact location on the device + Info (169086): Pin OUTPUT_D not assigned to an exact location on the device + Info (169086): Pin OUTPUT_E not assigned to an exact location on the device + Info (169086): Pin OUTPUT_F not assigned to an exact location on the device + Info (169086): Pin OUTPUT_G not assigned to an exact location on the device + Info (169086): Pin OUTPUT_A2 not assigned to an exact location on the device + Info (169086): Pin OUTPUT_B2 not assigned to an exact location on the device + Info (169086): Pin OUTPUT_C2 not assigned to an exact location on the device + Info (169086): Pin OUTPUT_D2 not assigned to an exact location on the device + Info (169086): Pin OUTPUT_E2 not assigned to an exact location on the device + Info (169086): Pin OUTPUT_F2 not assigned to an exact location on the device + Info (169086): Pin OUTPUT_G2 not assigned to an exact location on the device + Info (169086): Pin overflow not assigned to an exact location on the device + Info (169086): Pin pin_name1 not assigned to an exact location on the device + Info (169086): Pin INPUT_A4 not assigned to an exact location on the device + Info (169086): Pin INPUT_B3 not assigned to an exact location on the device + Info (169086): Pin isAdd not assigned to an exact location on the device + Info (169086): Pin INPUT_A3 not assigned to an exact location on the device + Info (169086): Pin INPUT_B2 not assigned to an exact location on the device + Info (169086): Pin INPUT_B1 not assigned to an exact location on the device + Info (169086): Pin INPUT_A1 not assigned to an exact location on the device + Info (169086): Pin INPUT_A2 not assigned to an exact location on the device + Info (169086): Pin INPUT_B4 not assigned to an exact location on the device + Info (169086): Pin clk not assigned to an exact location on the device + Info (169086): Pin reset not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 29 (unused VREF, 3.3V VCCIO, 9 input, 20 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y14 to location X50_Y27 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.17 seconds. +Info (306004): Started post-fitting delay annotation +Warning (306006): Found 20 output pins without output pin load capacitance assignment + Info (306007): Pin "OUTPUT_A" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "i[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "i[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "i[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "i[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_B" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_C" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_D" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_E" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_F" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_G" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_A2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_B2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_C2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_D2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_E2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_F2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_G2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "overflow" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "pin_name1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info (306005): Delay annotation completed successfully +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 4848 megabytes + Info: Processing ended: Mon May 04 17:05:39 2020 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:06 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/output_files/YL_adder.fit.smsg. + + diff --git a/YL_adder/output_files/YL_adder.fit.smsg b/YL_adder/output_files/YL_adder.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/YL_adder/output_files/YL_adder.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/YL_adder/output_files/YL_adder.fit.summary b/YL_adder/output_files/YL_adder.fit.summary new file mode 100644 index 0000000..c221849 --- /dev/null +++ b/YL_adder/output_files/YL_adder.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon May 04 17:05:38 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_adder +Top-level Entity Name : YL_adder +Family : Cyclone II +Device : EP2C20F484C7 +Timing Models : Final +Total logic elements : 22 / 18,752 ( < 1 % ) + Total combinational functions : 22 / 18,752 ( < 1 % ) + Dedicated logic registers : 4 / 18,752 ( < 1 % ) +Total registers : 4 +Total pins : 31 / 315 ( 10 % ) +Total virtual pins : 0 +Total memory bits : 0 / 239,616 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/YL_adder/output_files/YL_adder.flow.rpt b/YL_adder/output_files/YL_adder.flow.rpt new file mode 100644 index 0000000..37c259d --- /dev/null +++ b/YL_adder/output_files/YL_adder.flow.rpt @@ -0,0 +1,128 @@ +Flow report for YL_adder +Mon May 04 17:05:47 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Mon May 04 17:05:47 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_adder ; +; Top-level Entity Name ; YL_adder ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 22 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 22 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 4 / 18,752 ( < 1 % ) ; +; Total registers ; 4 ; +; Total pins ; 31 / 315 ( 10 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 05/04/2020 17:05:28 ; +; Main task ; Compilation ; +; Revision Name ; YL_adder ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 345052807169.158858312821972 ; -- ; -- ; -- ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------------+---------------+-------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:03 ; 1.0 ; 4597 MB ; 00:00:02 ; +; Fitter ; 00:00:06 ; 1.0 ; 4848 MB ; 00:00:06 ; +; Assembler ; 00:00:02 ; 1.0 ; 4552 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4557 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4518 MB ; 00:00:01 ; +; Total ; 00:00:13 ; -- ; -- ; 00:00:12 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off YL_adder -c YL_adder +quartus_fit --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder +quartus_asm --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder +quartus_sta YL_adder -c YL_adder +quartus_eda --read_settings_files=off --write_settings_files=off YL_adder -c YL_adder + + + diff --git a/YL_adder/output_files/YL_adder.jdi b/YL_adder/output_files/YL_adder.jdi new file mode 100644 index 0000000..5361a4c --- /dev/null +++ b/YL_adder/output_files/YL_adder.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/YL_adder/output_files/YL_adder.map.rpt b/YL_adder/output_files/YL_adder.map.rpt new file mode 100644 index 0000000..f5ebd10 --- /dev/null +++ b/YL_adder/output_files/YL_adder.map.rpt @@ -0,0 +1,299 @@ +Analysis & Synthesis report for YL_adder +Mon May 04 17:05:30 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon May 04 17:05:30 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_adder ; +; Top-level Entity Name ; YL_adder ; +; Family ; Cyclone II ; +; Total logic elements ; 22 ; +; Total combinational functions ; 22 ; +; Dedicated logic registers ; 4 ; +; Total registers ; 4 ; +; Total pins ; 31 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; YL_adder ; YL_adder ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+---------+ +; YL_adder.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf ; ; +; operator.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/operator.tdf ; ; +; overflow.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/overflow.tdf ; ; +; segment.tdf ; yes ; Auto-Found AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/segment.tdf ; ; +; encoder.tdf ; yes ; Auto-Found AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/encoder.tdf ; ; +; 74171.bdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/others/maxplus2/74171.bdf ; ; +; 7483.bdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/others/maxplus2/7483.bdf ; ; +; sign.tdf ; yes ; Auto-Found AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/sign.tdf ; ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+---------+ + + ++-------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------+ +; Estimated Total logic elements ; 22 ; +; ; ; +; Total combinational functions ; 22 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 12 ; +; -- 3 input functions ; 7 ; +; -- <=2 input functions ; 3 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 22 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 4 ; +; -- Dedicated logic registers ; 4 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 31 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; 74171:inst1|1 ; +; Maximum fan-out ; 12 ; +; Total fan-out ; 101 ; +; Average fan-out ; 1.77 ; ++---------------------------------------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ +; |YL_adder ; 22 (0) ; 4 (0) ; 0 ; 0 ; 0 ; 0 ; 31 ; 0 ; |YL_adder ; work ; +; |74171:inst1| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_adder|74171:inst1 ; work ; +; |7483:inst| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_adder|7483:inst ; work ; +; |encoder:inst20| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_adder|encoder:inst20 ; work ; +; |operator:inst21| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_adder|operator:inst21 ; work ; +; |overflow:inst23| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_adder|overflow:inst23 ; work ; +; |segment:inst17| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_adder|segment:inst17 ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 4 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 4 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 17:05:27 2020 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_adder -c YL_adder +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file yl_adder.bdf + Info (12023): Found entity 1: YL_adder +Warning (12019): Can't analyze file -- file YL_7segment.tdf is missing +Info (12021): Found 1 design units, including 1 entities, in source file /users/ushio/onedrive/study/uol/elec211/exp28_decoder/yl_7segment_sign.tdf + Info (12023): Found entity 1: 7segment +Warning (12019): Can't analyze file -- file YL_7segment_sign.tdf is missing +Warning (12019): Can't analyze file -- file YL_sign_to_unsign.tdf is missing +Info (12021): Found 1 design units, including 1 entities, in source file operator.tdf + Info (12023): Found entity 1: operator +Info (12021): Found 1 design units, including 1 entities, in source file overflow.tdf + Info (12023): Found entity 1: overflow +Info (12127): Elaborating entity "YL_adder" for the top level hierarchy +Warning (275012): Pin "i[3]" overlaps another pin, block, or symbol +Warning (12125): Using design file segment.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info (12023): Found entity 1: segment +Info (12128): Elaborating entity "segment" for hierarchy "segment:inst17" +Warning (12125): Using design file encoder.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info (12023): Found entity 1: encoder +Info (12128): Elaborating entity "encoder" for hierarchy "encoder:inst20" +Info (12128): Elaborating entity "74171" for hierarchy "74171:inst1" +Info (12130): Elaborated megafunction instantiation "74171:inst1" +Info (12128): Elaborating entity "7483" for hierarchy "7483:inst" +Info (12130): Elaborated megafunction instantiation "7483:inst" +Info (12128): Elaborating entity "operator" for hierarchy "operator:inst21" +Warning (12125): Using design file sign.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info (12023): Found entity 1: sign +Info (12128): Elaborating entity "sign" for hierarchy "sign:inst19" +Info (12128): Elaborating entity "overflow" for hierarchy "overflow:inst23" +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "OUTPUT_A2" is stuck at GND + Warning (13410): Pin "OUTPUT_B2" is stuck at GND + Warning (13410): Pin "OUTPUT_C2" is stuck at GND + Warning (13410): Pin "OUTPUT_D2" is stuck at GND + Warning (13410): Pin "OUTPUT_E2" is stuck at GND + Warning (13410): Pin "OUTPUT_F2" is stuck at GND +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 53 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 11 input pins + Info (21059): Implemented 20 output pins + Info (21061): Implemented 22 logic cells +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 15 warnings + Info: Peak virtual memory: 4608 megabytes + Info: Processing ended: Mon May 04 17:05:30 2020 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_adder/output_files/YL_adder.map.summary b/YL_adder/output_files/YL_adder.map.summary new file mode 100644 index 0000000..86f5697 --- /dev/null +++ b/YL_adder/output_files/YL_adder.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon May 04 17:05:30 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_adder +Top-level Entity Name : YL_adder +Family : Cyclone II +Total logic elements : 22 + Total combinational functions : 22 + Dedicated logic registers : 4 +Total registers : 4 +Total pins : 31 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/YL_adder/output_files/YL_adder.pin b/YL_adder/output_files/YL_adder.pin new file mode 100644 index 0000000..aea9d3c --- /dev/null +++ b/YL_adder/output_files/YL_adder.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "YL_adder" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +GND* : A11 : : : : 3 : +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +OUTPUT_A : A17 : output : 3.3-V LVTTL : : 4 : N +overflow : A18 : output : 3.3-V LVTTL : : 4 : N +OUTPUT_B2 : A19 : output : 3.3-V LVTTL : : 4 : N +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +GND* : AA3 : : : : 8 : +GND* : AA4 : : : : 8 : +GND* : AA5 : : : : 8 : +GND* : AA6 : : : : 8 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +GND* : AA11 : : : : 8 : +GND* : AA12 : : : : 7 : +GND* : AA13 : : : : 7 : +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +OUTPUT_D2 : AA17 : output : 3.3-V LVTTL : : 7 : N +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +GND* : AB3 : : : : 8 : +GND* : AB4 : : : : 8 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +GND* : AB12 : : : : 7 : +GND* : AB13 : : : : 7 : +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +GND* : B11 : : : : 3 : +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +GND* : B14 : : : : 4 : +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +OUTPUT_C : B17 : output : 3.3-V LVTTL : : 4 : N +isAdd : B18 : input : 3.3-V LVTTL : : 4 : N +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 2 : +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +GND* : C7 : : : : 3 : +GND : C8 : gnd : : : : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +i[3] : C14 : output : 3.3-V LVTTL : : 4 : N +GND : C15 : gnd : : : : +i[1] : C16 : output : 3.3-V LVTTL : : 4 : N +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +GND* : C21 : : : : 5 : +GND* : C22 : : : : 5 : +GND* : D1 : : : : 2 : +GND* : D2 : : : : 2 : +GND* : D3 : : : : 2 : +GND* : D4 : : : : 2 : +GND* : D5 : : : : 2 : +GND* : D6 : : : : 2 : +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +GND* : D9 : : : : 3 : +GND : D10 : gnd : : : : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +INPUT_B3 : D14 : input : 3.3-V LVTTL : : 4 : N +OUTPUT_E : D15 : output : 3.3-V LVTTL : : 4 : N +INPUT_A3 : D16 : input : 3.3-V LVTTL : : 4 : N +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +INPUT_A4 : D20 : input : 3.3-V LVTTL : : 5 : N +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +OUTPUT_F : E14 : output : 3.3-V LVTTL : : 4 : N +INPUT_B2 : E15 : input : 3.3-V LVTTL : : 4 : N +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +GND* : F1 : : : : 2 : +GND* : F2 : : : : 2 : +GND* : F3 : : : : 2 : +GND* : F4 : : : : 2 : +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +GND* : F12 : : : : 4 : +OUTPUT_D : F13 : output : 3.3-V LVTTL : : 4 : N +OUTPUT_G : F14 : output : 3.3-V LVTTL : : 4 : N +OUTPUT_G2 : F15 : output : 3.3-V LVTTL : : 4 : N +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +GND* : G3 : : : : 2 : +GND : G4 : gnd : : : : +GND* : G5 : : : : 2 : +GND* : G6 : : : : 2 : +GND* : G7 : : : : 3 : +GND* : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +i[2] : G15 : output : 3.3-V LVTTL : : 4 : N +INPUT_B1 : G16 : input : 3.3-V LVTTL : : 4 : N +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +GND* : H4 : : : : 2 : +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +GND* : H12 : : : : 4 : +OUTPUT_B : H13 : output : 3.3-V LVTTL : : 4 : N +INPUT_A1 : H14 : input : 3.3-V LVTTL : : 4 : N +i[0] : H15 : output : 3.3-V LVTTL : : 4 : N +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +GND* : J1 : : : : 2 : +GND* : J2 : : : : 2 : +NC : J3 : : : : : +GND* : J4 : : : : 2 : +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +pin_name1 : J14 : output : 3.3-V LVTTL : : 4 : N +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +INPUT_A2 : L1 : input : 3.3-V LVTTL : : 2 : N +INPUT_B4 : L2 : input : 3.3-V LVTTL : : 2 : N +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +GND* : L8 : : : : 2 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +GND+ : L21 : : : : 5 : +GND+ : L22 : : : : 5 : +clk : M1 : input : 3.3-V LVTTL : : 1 : N +reset : M2 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +GND+ : M22 : : : : 6 : +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +GND* : P5 : : : : 1 : +GND* : P6 : : : : 1 : +VCCIO1 : P7 : power : : 3.3V : 1 : +GND* : P8 : : : : 8 : +GND* : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +OUTPUT_A2 : P18 : output : 3.3-V LVTTL : : 6 : N +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +GND* : R1 : : : : 1 : +GND* : R2 : : : : 1 : +GND : R3 : gnd : : : : +NC : R4 : : : : : +GND* : R5 : : : : 1 : +GND* : R6 : : : : 1 : +GND* : R7 : : : : 1 : +GND* : R8 : : : : 1 : +GND* : R9 : : : : 8 : +OUTPUT_F2 : R10 : output : 3.3-V LVTTL : : 8 : N +GND* : R11 : : : : 8 : +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +GND* : T1 : : : : 1 : +GND* : T2 : : : : 1 : +GND* : T3 : : : : 1 : +VCCIO1 : T4 : power : : 3.3V : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 8 : +GND* : T8 : : : : 8 : +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +GND* : T12 : : : : 7 : +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +GND* : T15 : : : : 7 : +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +GND* : U8 : : : : 8 : +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND : V3 : gnd : : : : +GND* : V4 : : : : 1 : +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +GND* : V8 : : : : 8 : +OUTPUT_E2 : V9 : output : 3.3-V LVTTL : : 8 : N +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +VCCIO8 : W6 : power : : 3.3V : 8 : +GND* : W7 : : : : 8 : +GND* : W8 : : : : 8 : +GND* : W9 : : : : 8 : +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +GND* : Y1 : : : : 1 : +GND* : Y2 : : : : 1 : +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +GND* : Y5 : : : : 8 : +GND* : Y6 : : : : 8 : +GND* : Y7 : : : : 8 : +GND : Y8 : gnd : : : : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power 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z(|?YR_8XUf@BhS|9=PH^xIX-M8lEUmHr&bf(W*>&v_185x?S*foad8G=-bI1+Uqlb qX(z(~Rfc~gszc1DNjTjuOYGDyVg!F0KyLd&fpwVM_Vd?k@BRP0iPPl( literal 0 HcmV?d00001 diff --git a/YL_adder/output_files/YL_adder.sta.rpt b/YL_adder/output_files/YL_adder.sta.rpt new file mode 100644 index 0000000..9c97a88 --- /dev/null +++ b/YL_adder/output_files/YL_adder.sta.rpt @@ -0,0 +1,667 @@ +TimeQuest Timing Analyzer report for YL_adder +Mon May 04 17:05:44 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow Model Fmax Summary + 6. Slow Model Setup Summary + 7. Slow Model Hold Summary + 8. Slow Model Recovery Summary + 9. Slow Model Removal Summary + 10. Slow Model Minimum Pulse Width Summary + 11. Slow Model Minimum Pulse Width: 'clk' + 12. Setup Times + 13. Hold Times + 14. Clock to Output Times + 15. Minimum Clock to Output Times + 16. Propagation Delay + 17. Minimum Propagation Delay + 18. Fast Model Setup Summary + 19. Fast Model Hold Summary + 20. Fast Model Recovery Summary + 21. Fast Model Removal Summary + 22. Fast Model Minimum Pulse Width Summary + 23. Fast Model Minimum Pulse Width: 'clk' + 24. Setup Times + 25. Hold Times + 26. Clock to Output Times + 27. Minimum Clock to Output Times + 28. Propagation Delay + 29. Minimum Propagation Delay + 30. Multicorner Timing Analysis Summary + 31. Setup Times + 32. Hold Times + 33. Clock to Output Times + 34. Minimum Clock to Output Times + 35. Progagation Delay + 36. Minimum Progagation Delay + 37. Clock Transfers + 38. Report TCCS + 39. Report RSKM + 40. Unconstrained Paths + 41. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; YL_adder ; +; Device Family ; Cyclone II ; +; Device Name ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ + + +--------------------------- +; Slow Model Fmax Summary ; +--------------------------- +No paths to report. + + +---------------------------- +; Slow Model Setup Summary ; +---------------------------- +No paths to report. + + +--------------------------- +; Slow Model Hold Summary ; +--------------------------- +No paths to report. + + +------------------------------- +; Slow Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Slow Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Slow Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clk ; -1.631 ; -6.519 ; ++-------+--------+-----------------------+ + + ++-------------------------------------------------------------------------------------------------------+ +; Slow Model Minimum Pulse Width: 'clk' ; ++--------+--------------+----------------+------------------+-------+------------+----------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+----------------------+ +; -1.631 ; 1.000 ; 2.631 ; Port Rate ; clk ; Rise ; clk ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; 74171:inst1|1 ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|1 ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; 74171:inst1|15 ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|15 ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; 74171:inst1|16 ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|16 ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; 74171:inst1|8 ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|8 ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|15|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|15|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|16|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|16|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|1|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|1|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|8|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|8|clk ; ++--------+--------------+----------------+------------------+-------+------------+----------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; INPUT_A1 ; clk ; 5.170 ; 5.170 ; Rise ; clk ; +; INPUT_A2 ; clk ; 1.373 ; 1.373 ; Rise ; clk ; +; INPUT_A3 ; clk ; 4.766 ; 4.766 ; Rise ; clk ; +; INPUT_A4 ; clk ; 4.003 ; 4.003 ; Rise ; clk ; +; INPUT_B1 ; clk ; 5.417 ; 5.417 ; Rise ; clk ; +; INPUT_B2 ; clk ; 5.112 ; 5.112 ; Rise ; clk ; +; INPUT_B3 ; clk ; 5.146 ; 5.146 ; Rise ; clk ; +; INPUT_B4 ; clk ; 1.836 ; 1.836 ; Rise ; clk ; +; isAdd ; clk ; 5.419 ; 5.419 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; INPUT_A1 ; clk ; -3.325 ; -3.325 ; Rise ; clk ; +; INPUT_A2 ; clk ; -0.618 ; -0.618 ; Rise ; clk ; +; INPUT_A3 ; clk ; -4.109 ; -4.109 ; Rise ; clk ; +; INPUT_A4 ; clk ; -3.755 ; -3.755 ; Rise ; clk ; +; INPUT_B1 ; clk ; -3.227 ; -3.227 ; Rise ; clk ; +; INPUT_B2 ; clk ; -3.581 ; -3.581 ; Rise ; clk ; +; INPUT_B3 ; clk ; -4.552 ; -4.552 ; Rise ; clk ; +; INPUT_B4 ; clk ; -1.588 ; -1.588 ; Rise ; clk ; +; isAdd ; clk ; -3.569 ; -3.569 ; Rise ; clk ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; OUTPUT_A ; clk ; 8.898 ; 8.898 ; Rise ; clk ; +; OUTPUT_B ; clk ; 8.691 ; 8.691 ; Rise ; clk ; +; OUTPUT_C ; clk ; 8.634 ; 8.634 ; Rise ; clk ; +; OUTPUT_D ; clk ; 8.553 ; 8.553 ; Rise ; clk ; +; OUTPUT_E ; clk ; 8.341 ; 8.341 ; Rise ; clk ; +; OUTPUT_F ; clk ; 8.895 ; 8.895 ; Rise ; clk ; +; OUTPUT_G ; clk ; 8.903 ; 8.903 ; Rise ; clk ; +; OUTPUT_G2 ; clk ; 7.197 ; 7.197 ; Rise ; clk ; +; i[*] ; clk ; 9.209 ; 9.209 ; Rise ; clk ; +; i[0] ; clk ; 7.171 ; 7.171 ; Rise ; clk ; +; i[1] ; clk ; 9.209 ; 9.209 ; Rise ; clk ; +; i[2] ; clk ; 8.631 ; 8.631 ; Rise ; clk ; +; i[3] ; clk ; 8.629 ; 8.629 ; Rise ; clk ; +; pin_name1 ; clk ; 6.896 ; 6.896 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; OUTPUT_A ; clk ; 8.265 ; 8.265 ; Rise ; clk ; +; OUTPUT_B ; clk ; 8.025 ; 8.025 ; Rise ; clk ; +; OUTPUT_C ; clk ; 8.009 ; 8.009 ; Rise ; clk ; +; OUTPUT_D ; clk ; 8.229 ; 8.229 ; Rise ; clk ; +; OUTPUT_E ; clk ; 7.979 ; 7.979 ; Rise ; clk ; +; OUTPUT_F ; clk ; 8.232 ; 8.232 ; Rise ; clk ; +; OUTPUT_G ; clk ; 8.237 ; 8.237 ; Rise ; clk ; +; OUTPUT_G2 ; clk ; 7.197 ; 7.197 ; Rise ; clk ; +; i[*] ; clk ; 7.171 ; 7.171 ; Rise ; clk ; +; i[0] ; clk ; 7.171 ; 7.171 ; Rise ; clk ; +; i[1] ; clk ; 8.552 ; 8.552 ; Rise ; clk ; +; i[2] ; clk ; 7.966 ; 7.966 ; Rise ; clk ; +; i[3] ; clk ; 7.967 ; 7.967 ; Rise ; clk ; +; pin_name1 ; clk ; 6.896 ; 6.896 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++--------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; INPUT_A1 ; overflow ; 11.949 ; 11.949 ; 11.949 ; 11.949 ; +; INPUT_A2 ; overflow ; 8.152 ; 8.152 ; 8.152 ; 8.152 ; +; INPUT_A3 ; overflow ; 11.545 ; 11.545 ; 11.545 ; 11.545 ; +; INPUT_A4 ; overflow ; 10.775 ; 10.775 ; 10.775 ; 10.775 ; +; INPUT_B1 ; overflow ; 12.196 ; 12.196 ; 12.196 ; 12.196 ; +; INPUT_B2 ; overflow ; 11.891 ; 11.891 ; 11.891 ; 11.891 ; +; INPUT_B3 ; overflow ; 11.925 ; 11.925 ; 11.925 ; 11.925 ; +; INPUT_B4 ; overflow ; 8.607 ; 8.607 ; 8.607 ; 8.607 ; +; isAdd ; overflow ; 12.198 ; 12.198 ; 12.198 ; 12.198 ; ++------------+-------------+--------+--------+--------+--------+ + + ++--------------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; INPUT_A1 ; overflow ; 11.949 ; 11.949 ; 11.949 ; 11.949 ; +; INPUT_A2 ; overflow ; 8.152 ; 8.152 ; 8.152 ; 8.152 ; +; INPUT_A3 ; overflow ; 11.128 ; 11.128 ; 11.128 ; 11.128 ; +; INPUT_A4 ; overflow ; 10.775 ; 10.775 ; 10.775 ; 10.775 ; +; INPUT_B1 ; overflow ; 12.196 ; 12.196 ; 12.196 ; 12.196 ; +; INPUT_B2 ; overflow ; 11.891 ; 11.891 ; 11.891 ; 11.891 ; +; INPUT_B3 ; overflow ; 11.571 ; 11.571 ; 11.571 ; 11.571 ; +; INPUT_B4 ; overflow ; 8.607 ; 8.607 ; 8.607 ; 8.607 ; +; isAdd ; overflow ; 11.213 ; 11.213 ; 11.213 ; 11.213 ; ++------------+-------------+--------+--------+--------+--------+ + + +---------------------------- +; Fast Model Setup Summary ; +---------------------------- +No paths to report. + + +--------------------------- +; Fast Model Hold Summary ; +--------------------------- +No paths to report. + + +------------------------------- +; Fast Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Fast Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Fast Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clk ; -1.380 ; -5.380 ; ++-------+--------+-----------------------+ + + ++-------------------------------------------------------------------------------------------------------+ +; Fast Model Minimum Pulse Width: 'clk' ; ++--------+--------------+----------------+------------------+-------+------------+----------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+----------------------+ +; -1.380 ; 1.000 ; 2.380 ; Port Rate ; clk ; Rise ; clk ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; 74171:inst1|1 ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|1 ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; 74171:inst1|15 ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|15 ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; 74171:inst1|16 ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|16 ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; 74171:inst1|8 ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; 74171:inst1|8 ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|15|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|15|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|16|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|16|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|1|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|1|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|8|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|8|clk ; ++--------+--------------+----------------+------------------+-------+------------+----------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; INPUT_A1 ; clk ; 2.172 ; 2.172 ; Rise ; clk ; +; INPUT_A2 ; clk ; 0.091 ; 0.091 ; Rise ; clk ; +; INPUT_A3 ; clk ; 2.015 ; 2.015 ; Rise ; clk ; +; INPUT_A4 ; clk ; 1.768 ; 1.768 ; Rise ; clk ; +; INPUT_B1 ; clk ; 2.252 ; 2.252 ; Rise ; clk ; +; INPUT_B2 ; clk ; 2.133 ; 2.133 ; Rise ; clk ; +; INPUT_B3 ; clk ; 2.172 ; 2.172 ; Rise ; clk ; +; INPUT_B4 ; clk ; 0.221 ; 0.221 ; Rise ; clk ; +; isAdd ; clk ; 2.281 ; 2.281 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; INPUT_A1 ; clk ; -1.487 ; -1.487 ; Rise ; clk ; +; INPUT_A2 ; clk ; 0.219 ; 0.219 ; Rise ; clk ; +; INPUT_A3 ; clk ; -1.759 ; -1.759 ; Rise ; clk ; +; INPUT_A4 ; clk ; -1.648 ; -1.648 ; Rise ; clk ; +; INPUT_B1 ; clk ; -1.451 ; -1.451 ; Rise ; clk ; +; INPUT_B2 ; clk ; -1.552 ; -1.552 ; Rise ; clk ; +; INPUT_B3 ; clk ; -1.918 ; -1.918 ; Rise ; clk ; +; INPUT_B4 ; clk ; -0.101 ; -0.101 ; Rise ; clk ; +; isAdd ; clk ; -1.593 ; -1.593 ; Rise ; clk ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; OUTPUT_A ; clk ; 4.532 ; 4.532 ; Rise ; clk ; +; OUTPUT_B ; clk ; 4.443 ; 4.443 ; Rise ; clk ; +; OUTPUT_C ; clk ; 4.431 ; 4.431 ; Rise ; clk ; +; OUTPUT_D ; clk ; 4.388 ; 4.388 ; Rise ; clk ; +; OUTPUT_E ; clk ; 4.306 ; 4.306 ; Rise ; clk ; +; OUTPUT_F ; clk ; 4.497 ; 4.497 ; Rise ; clk ; +; OUTPUT_G ; clk ; 4.506 ; 4.506 ; Rise ; clk ; +; OUTPUT_G2 ; clk ; 3.896 ; 3.896 ; Rise ; clk ; +; i[*] ; clk ; 4.630 ; 4.630 ; Rise ; clk ; +; i[0] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; i[1] ; clk ; 4.630 ; 4.630 ; Rise ; clk ; +; i[2] ; clk ; 4.404 ; 4.404 ; Rise ; clk ; +; i[3] ; clk ; 4.414 ; 4.414 ; Rise ; clk ; +; pin_name1 ; clk ; 3.775 ; 3.775 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; OUTPUT_A ; clk ; 4.303 ; 4.303 ; Rise ; clk ; +; OUTPUT_B ; clk ; 4.211 ; 4.211 ; Rise ; clk ; +; OUTPUT_C ; clk ; 4.195 ; 4.195 ; Rise ; clk ; +; OUTPUT_D ; clk ; 4.269 ; 4.269 ; Rise ; clk ; +; OUTPUT_E ; clk ; 4.181 ; 4.181 ; Rise ; clk ; +; OUTPUT_F ; clk ; 4.269 ; 4.269 ; Rise ; clk ; +; OUTPUT_G ; clk ; 4.274 ; 4.274 ; Rise ; clk ; +; OUTPUT_G2 ; clk ; 3.896 ; 3.896 ; Rise ; clk ; +; i[*] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; i[0] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; i[1] ; clk ; 4.404 ; 4.404 ; Rise ; clk ; +; i[2] ; clk ; 4.175 ; 4.175 ; Rise ; clk ; +; i[3] ; clk ; 4.178 ; 4.178 ; Rise ; clk ; +; pin_name1 ; clk ; 3.775 ; 3.775 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; INPUT_A1 ; overflow ; 5.868 ; 5.868 ; 5.868 ; 5.868 ; +; INPUT_A2 ; overflow ; 3.787 ; 3.787 ; 3.787 ; 3.787 ; +; INPUT_A3 ; overflow ; 5.711 ; 5.711 ; 5.711 ; 5.711 ; +; INPUT_A4 ; overflow ; 5.462 ; 5.462 ; 5.462 ; 5.462 ; +; INPUT_B1 ; overflow ; 5.948 ; 5.948 ; 5.948 ; 5.948 ; +; INPUT_B2 ; overflow ; 5.829 ; 5.829 ; 5.829 ; 5.829 ; +; INPUT_B3 ; overflow ; 5.868 ; 5.868 ; 5.868 ; 5.868 ; +; INPUT_B4 ; overflow ; 3.917 ; 3.917 ; 3.917 ; 3.917 ; +; isAdd ; overflow ; 5.977 ; 5.977 ; 5.977 ; 5.977 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; INPUT_A1 ; overflow ; 5.868 ; 5.868 ; 5.868 ; 5.868 ; +; INPUT_A2 ; overflow ; 3.787 ; 3.787 ; 3.787 ; 3.787 ; +; INPUT_A3 ; overflow ; 5.567 ; 5.567 ; 5.567 ; 5.567 ; +; INPUT_A4 ; overflow ; 5.462 ; 5.462 ; 5.462 ; 5.462 ; +; INPUT_B1 ; overflow ; 5.948 ; 5.948 ; 5.948 ; 5.948 ; +; INPUT_B2 ; overflow ; 5.829 ; 5.829 ; 5.829 ; 5.829 ; +; INPUT_B3 ; overflow ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; +; INPUT_B4 ; overflow ; 3.917 ; 3.917 ; 3.917 ; 3.917 ; +; isAdd ; overflow ; 5.619 ; 5.619 ; 5.619 ; 5.619 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; -1.631 ; +; clk ; N/A ; N/A ; N/A ; N/A ; -1.631 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -6.519 ; +; clk ; N/A ; N/A ; N/A ; N/A ; -6.519 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; INPUT_A1 ; clk ; 5.170 ; 5.170 ; Rise ; clk ; +; INPUT_A2 ; clk ; 1.373 ; 1.373 ; Rise ; clk ; +; INPUT_A3 ; clk ; 4.766 ; 4.766 ; Rise ; clk ; +; INPUT_A4 ; clk ; 4.003 ; 4.003 ; Rise ; clk ; +; INPUT_B1 ; clk ; 5.417 ; 5.417 ; Rise ; clk ; +; INPUT_B2 ; clk ; 5.112 ; 5.112 ; Rise ; clk ; +; INPUT_B3 ; clk ; 5.146 ; 5.146 ; Rise ; clk ; +; INPUT_B4 ; clk ; 1.836 ; 1.836 ; Rise ; clk ; +; isAdd ; clk ; 5.419 ; 5.419 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; INPUT_A1 ; clk ; -1.487 ; -1.487 ; Rise ; clk ; +; INPUT_A2 ; clk ; 0.219 ; 0.219 ; Rise ; clk ; +; INPUT_A3 ; clk ; -1.759 ; -1.759 ; Rise ; clk ; +; INPUT_A4 ; clk ; -1.648 ; -1.648 ; Rise ; clk ; +; INPUT_B1 ; clk ; -1.451 ; -1.451 ; Rise ; clk ; +; INPUT_B2 ; clk ; -1.552 ; -1.552 ; Rise ; clk ; +; INPUT_B3 ; clk ; -1.918 ; -1.918 ; Rise ; clk ; +; INPUT_B4 ; clk ; -0.101 ; -0.101 ; Rise ; clk ; +; isAdd ; clk ; -1.593 ; -1.593 ; Rise ; clk ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; OUTPUT_A ; clk ; 8.898 ; 8.898 ; Rise ; clk ; +; OUTPUT_B ; clk ; 8.691 ; 8.691 ; Rise ; clk ; +; OUTPUT_C ; clk ; 8.634 ; 8.634 ; Rise ; clk ; +; OUTPUT_D ; clk ; 8.553 ; 8.553 ; Rise ; clk ; +; OUTPUT_E ; clk ; 8.341 ; 8.341 ; Rise ; clk ; +; OUTPUT_F ; clk ; 8.895 ; 8.895 ; Rise ; clk ; +; OUTPUT_G ; clk ; 8.903 ; 8.903 ; Rise ; clk ; +; OUTPUT_G2 ; clk ; 7.197 ; 7.197 ; Rise ; clk ; +; i[*] ; clk ; 9.209 ; 9.209 ; Rise ; clk ; +; i[0] ; clk ; 7.171 ; 7.171 ; Rise ; clk ; +; i[1] ; clk ; 9.209 ; 9.209 ; Rise ; clk ; +; i[2] ; clk ; 8.631 ; 8.631 ; Rise ; clk ; +; i[3] ; clk ; 8.629 ; 8.629 ; Rise ; clk ; +; pin_name1 ; clk ; 6.896 ; 6.896 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; OUTPUT_A ; clk ; 4.303 ; 4.303 ; Rise ; clk ; +; OUTPUT_B ; clk ; 4.211 ; 4.211 ; Rise ; clk ; +; OUTPUT_C ; clk ; 4.195 ; 4.195 ; Rise ; clk ; +; OUTPUT_D ; clk ; 4.269 ; 4.269 ; Rise ; clk ; +; OUTPUT_E ; clk ; 4.181 ; 4.181 ; Rise ; clk ; +; OUTPUT_F ; clk ; 4.269 ; 4.269 ; Rise ; clk ; +; OUTPUT_G ; clk ; 4.274 ; 4.274 ; Rise ; clk ; +; OUTPUT_G2 ; clk ; 3.896 ; 3.896 ; Rise ; clk ; +; i[*] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; i[0] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; i[1] ; clk ; 4.404 ; 4.404 ; Rise ; clk ; +; i[2] ; clk ; 4.175 ; 4.175 ; Rise ; clk ; +; i[3] ; clk ; 4.178 ; 4.178 ; Rise ; clk ; +; pin_name1 ; clk ; 3.775 ; 3.775 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++--------------------------------------------------------------+ +; Progagation Delay ; ++------------+-------------+--------+--------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+--------+--------+--------+ +; INPUT_A1 ; overflow ; 11.949 ; 11.949 ; 11.949 ; 11.949 ; +; INPUT_A2 ; overflow ; 8.152 ; 8.152 ; 8.152 ; 8.152 ; +; INPUT_A3 ; overflow ; 11.545 ; 11.545 ; 11.545 ; 11.545 ; +; INPUT_A4 ; overflow ; 10.775 ; 10.775 ; 10.775 ; 10.775 ; +; INPUT_B1 ; overflow ; 12.196 ; 12.196 ; 12.196 ; 12.196 ; +; INPUT_B2 ; overflow ; 11.891 ; 11.891 ; 11.891 ; 11.891 ; +; INPUT_B3 ; overflow ; 11.925 ; 11.925 ; 11.925 ; 11.925 ; +; INPUT_B4 ; overflow ; 8.607 ; 8.607 ; 8.607 ; 8.607 ; +; isAdd ; overflow ; 12.198 ; 12.198 ; 12.198 ; 12.198 ; ++------------+-------------+--------+--------+--------+--------+ + + ++----------------------------------------------------------+ +; Minimum Progagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; INPUT_A1 ; overflow ; 5.868 ; 5.868 ; 5.868 ; 5.868 ; +; INPUT_A2 ; overflow ; 3.787 ; 3.787 ; 3.787 ; 3.787 ; +; INPUT_A3 ; overflow ; 5.567 ; 5.567 ; 5.567 ; 5.567 ; +; INPUT_A4 ; overflow ; 5.462 ; 5.462 ; 5.462 ; 5.462 ; +; INPUT_B1 ; overflow ; 5.948 ; 5.948 ; 5.948 ; 5.948 ; +; INPUT_B2 ; overflow ; 5.829 ; 5.829 ; 5.829 ; 5.829 ; +; INPUT_B3 ; overflow ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; +; INPUT_B4 ; overflow ; 3.917 ; 3.917 ; 3.917 ; 3.917 ; +; isAdd ; overflow ; 5.619 ; 5.619 ; 5.619 ; 5.619 ; ++------------+-------------+-------+-------+-------+-------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 10 ; 10 ; +; Unconstrained Input Port Paths ; 36 ; 36 ; +; Unconstrained Output Ports ; 14 ; 14 ; +; Unconstrained Output Port Paths ; 49 ; 49 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 17:05:43 2020 +Info: Command: quartus_sta YL_adder -c YL_adder +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name clk clk +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case minimum pulse width slack is -1.631 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.631 -6.519 clk +Info (332001): The selected device family is not supported by the report_metastability command. +Info: Analyzing Fast Model +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case minimum pulse width slack is -1.380 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.380 -5.380 clk +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 4557 megabytes + Info: Processing ended: Mon May 04 17:05:44 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/YL_adder/output_files/YL_adder.sta.summary b/YL_adder/output_files/YL_adder.sta.summary new file mode 100644 index 0000000..ec7b6cc --- /dev/null +++ b/YL_adder/output_files/YL_adder.sta.summary @@ -0,0 +1,13 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow Model Minimum Pulse Width 'clk' +Slack : -1.631 +TNS : -6.519 + +Type : Fast Model Minimum Pulse Width 'clk' +Slack : -1.380 +TNS : -5.380 + +------------------------------------------------------------ diff --git a/YL_adder/overflow.bsf b/YL_adder/overflow.bsf new file mode 100644 index 0000000..5d225d8 --- /dev/null +++ b/YL_adder/overflow.bsf @@ -0,0 +1,57 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 136 128) + (text "overflow" (rect 5 0 39 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "iA" (rect 0 0 9 12)(font "Arial" )) + (text "iA" (rect 21 27 30 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "iB" (rect 0 0 7 12)(font "Arial" )) + (text "iB" (rect 21 43 28 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "o" (rect 0 0 4 12)(font "Arial" )) + (text "o" (rect 21 59 25 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 120 32) + (output) + (text "v" (rect 0 0 5 12)(font "Arial" )) + (text "v" (rect 94 27 99 39)(font "Arial" )) + (line (pt 120 32)(pt 104 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 104 96)(line_width 1)) + ) +) diff --git a/YL_adder/overflow.tdf b/YL_adder/overflow.tdf new file mode 100644 index 0000000..5bb2384 --- /dev/null +++ b/YL_adder/overflow.tdf @@ -0,0 +1,12 @@ +SUBDESIGN overflow +( + iA, iB, o : input; + v : output; +) +BEGIN + if (iA == VCC & iB == VCC & o == GND)#(iA == GND & iB == GND & o == VCC) THEN + v = VCC; + ELSE + v = GND; + END IF; +END; \ No newline at end of file diff --git a/YL_adder/segment.bsf b/YL_adder/segment.bsf new file mode 100644 index 0000000..3ce2e29 --- /dev/null +++ b/YL_adder/segment.bsf @@ -0,0 +1,85 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 144 192) + (text "segment" (rect 5 0 39 12)(font "Arial" )) + (text "inst" (rect 8 160 20 172)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "i[3..0]" (rect 0 0 21 12)(font "Arial" )) + (text "i[3..0]" (rect 21 27 42 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 128 32) + (output) + (text "a" (rect 0 0 4 12)(font "Arial" )) + (text "a" (rect 103 27 107 39)(font "Arial" )) + (line (pt 128 32)(pt 112 32)(line_width 1)) + ) + (port + (pt 128 48) + (output) + (text "b" (rect 0 0 4 12)(font "Arial" )) + (text "b" (rect 103 43 107 55)(font "Arial" )) + (line (pt 128 48)(pt 112 48)(line_width 1)) + ) + (port + (pt 128 64) + (output) + (text "c" (rect 0 0 4 12)(font "Arial" )) + (text "c" (rect 103 59 107 71)(font "Arial" )) + (line (pt 128 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 128 80) + (output) + (text "d" (rect 0 0 4 12)(font "Arial" )) + (text "d" (rect 103 75 107 87)(font "Arial" )) + (line (pt 128 80)(pt 112 80)(line_width 1)) + ) + (port + (pt 128 96) + (output) + (text "e" (rect 0 0 4 12)(font "Arial" )) + (text "e" (rect 103 91 107 103)(font "Arial" )) + (line (pt 128 96)(pt 112 96)(line_width 1)) + ) + (port + (pt 128 112) + (output) + (text "f" (rect 0 0 3 12)(font "Arial" )) + (text "f" (rect 104 107 107 119)(font "Arial" )) + (line (pt 128 112)(pt 112 112)(line_width 1)) + ) + (port + (pt 128 128) + (output) + (text "g" (rect 0 0 4 12)(font "Arial" )) + (text "g" (rect 103 123 107 135)(font "Arial" )) + (line (pt 128 128)(pt 112 128)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 112 160)(line_width 1)) + ) +) diff --git a/YL_adder/segment.tdf b/YL_adder/segment.tdf new file mode 100644 index 0000000..3d3ab0d --- /dev/null +++ b/YL_adder/segment.tdf @@ -0,0 +1,28 @@ +% 0 1 2 3 4 5 6 7 8 9 A b C d E F % +% % +SUBDESIGN segment +( + i[3..0] : INPUT; + a, b, c, d, e, f, g : OUTPUT; +) +BEGIN + TABLE + i[3..0] => a, b, c, d, e, f, g; + H"0" => 1, 1, 1, 1, 1, 1, 0; + H"1" => 0, 1, 1, 0, 0, 0, 0; + H"2" => 1, 1, 0, 1, 1, 0, 1; + H"3" => 1, 1, 1, 1, 0, 0, 1; + H"4" => 0, 1, 1, 0, 0, 1, 1; + H"5" => 1, 0, 1, 1, 0, 1, 1; + H"6" => 1, 0, 1, 1, 1, 1, 1; + H"7" => 1, 1, 1, 0, 0, 0, 0; + H"8" => 1, 1, 1, 1, 1, 1, 1; + H"9" => 1, 1, 1, 1, 0, 1, 1; + H"A" => 1, 1, 1, 0, 1, 1, 1; + H"B" => 0, 0, 1, 1, 1, 1, 1; + H"C" => 1, 0, 0, 1, 1, 1, 0; + H"D" => 0, 1, 1, 1, 1, 0, 1; + H"E" => 1, 0, 0, 1, 1, 1, 1; + H"F" => 1, 0, 0, 0, 1, 1, 1; + END TABLE; +END; diff --git a/YL_adder/sign.bsf b/YL_adder/sign.bsf new file mode 100644 index 0000000..a944dd0 --- /dev/null +++ b/YL_adder/sign.bsf @@ -0,0 +1,85 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 136 192) + (text "sign" (rect 5 0 20 12)(font "Arial" )) + (text "inst" (rect 8 160 20 172)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "sign" (rect 0 0 15 12)(font "Arial" )) + (text "sign" (rect 21 27 36 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 120 32) + (output) + (text "a" (rect 0 0 4 12)(font "Arial" )) + (text "a" (rect 95 27 99 39)(font "Arial" )) + (line (pt 120 32)(pt 104 32)(line_width 1)) + ) + (port + (pt 120 48) + (output) + (text "b" (rect 0 0 4 12)(font "Arial" )) + (text "b" (rect 95 43 99 55)(font "Arial" )) + (line (pt 120 48)(pt 104 48)(line_width 1)) + ) + (port + (pt 120 64) + (output) + (text "c" (rect 0 0 4 12)(font "Arial" )) + (text "c" (rect 95 59 99 71)(font "Arial" )) + (line (pt 120 64)(pt 104 64)(line_width 1)) + ) + (port + (pt 120 80) + (output) + (text "d" (rect 0 0 4 12)(font "Arial" )) + (text "d" (rect 95 75 99 87)(font "Arial" )) + (line (pt 120 80)(pt 104 80)(line_width 1)) + ) + (port + (pt 120 96) + (output) + (text "e" (rect 0 0 4 12)(font "Arial" )) + (text "e" (rect 95 91 99 103)(font "Arial" )) + (line (pt 120 96)(pt 104 96)(line_width 1)) + ) + (port + (pt 120 112) + (output) + (text "f" (rect 0 0 3 12)(font "Arial" )) + (text "f" (rect 96 107 99 119)(font "Arial" )) + (line (pt 120 112)(pt 104 112)(line_width 1)) + ) + (port + (pt 120 128) + (output) + (text "g" (rect 0 0 4 12)(font "Arial" )) + (text "g" (rect 95 123 99 135)(font "Arial" )) + (line (pt 120 128)(pt 104 128)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 104 160)(line_width 1)) + ) +) diff --git a/YL_adder/sign.tdf b/YL_adder/sign.tdf new file mode 100644 index 0000000..c202efb --- /dev/null +++ b/YL_adder/sign.tdf @@ -0,0 +1,25 @@ +% 0 1 2 3 4 5 6 7 8 9 A b C d E F % +% % +SUBDESIGN sign +( + sign : INPUT; + a, b, c, d, e, f, g : OUTPUT; +) +BEGIN + + DEFAULTS + a = VCC; + b = VCC; + c = VCC; + d = VCC; + e = VCC; + f = VCC; + g = VCC; + END DEFAULTS; + + IF sign THEN + g = GND; + ELSE + g = VCC; + END iF; +END; diff --git a/YL_adder/simulation/modelsim/YL_adder.sft b/YL_adder/simulation/modelsim/YL_adder.sft new file mode 100644 index 0000000..d59d08b --- /dev/null +++ b/YL_adder/simulation/modelsim/YL_adder.sft @@ -0,0 +1,5 @@ +set tool_name "ModelSim-Altera (Verilog)" +set corner_file_list { + {{"Slow Model"} {YL_adder.vo YL_adder_v.sdo}} + {{"Fast Model"} {YL_adder_fast.vo YL_adder_v_fast.sdo}} +} diff --git a/YL_adder/simulation/modelsim/YL_adder.vo b/YL_adder/simulation/modelsim/YL_adder.vo new file mode 100644 index 0000000..76f39d1 --- /dev/null +++ b/YL_adder/simulation/modelsim/YL_adder.vo @@ -0,0 +1,1747 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/04/2020 17:05:47" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_adder ( + OUTPUT_A, + i, + reset, + INPUT_B1, + INPUT_B2, + INPUT_B3, + INPUT_B4, + isAdd, + INPUT_A1, + INPUT_A2, + INPUT_A3, + INPUT_A4, + clk, + OUTPUT_B, + OUTPUT_C, + OUTPUT_D, + OUTPUT_E, + OUTPUT_F, + OUTPUT_G, + OUTPUT_A2, + OUTPUT_B2, + OUTPUT_C2, + OUTPUT_D2, + OUTPUT_E2, + OUTPUT_F2, + OUTPUT_G2, + overflow, + pin_name1); +output OUTPUT_A; +output [3:0] i; +input reset; +input INPUT_B1; +input INPUT_B2; +input INPUT_B3; +input INPUT_B4; +input isAdd; +input INPUT_A1; +input INPUT_A2; +input INPUT_A3; +input INPUT_A4; +input clk; +output OUTPUT_B; +output OUTPUT_C; +output OUTPUT_D; +output OUTPUT_E; +output OUTPUT_F; +output OUTPUT_G; +output OUTPUT_A2; +output OUTPUT_B2; +output OUTPUT_C2; +output OUTPUT_D2; +output OUTPUT_E2; +output OUTPUT_F2; +output OUTPUT_G2; +output overflow; +output pin_name1; + +// Design Ports Information +// OUTPUT_A => Location: PIN_A17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[3] => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[2] => Location: PIN_G15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[1] => Location: PIN_C16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[0] => Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B => Location: PIN_H13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C => Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D => Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E => Location: PIN_D15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F => Location: PIN_E14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G => Location: PIN_F14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_A2 => Location: PIN_P18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B2 => Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C2 => Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D2 => Location: PIN_AA17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E2 => Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F2 => Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G2 => Location: PIN_F15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// overflow => Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// pin_name1 => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// INPUT_A4 => Location: PIN_D20, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B3 => Location: PIN_D14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// isAdd => Location: PIN_B18, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A3 => Location: PIN_D16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B2 => Location: PIN_E15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B1 => Location: PIN_G16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A1 => Location: PIN_H14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A2 => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B4 => Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// reset => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("YL_adder_v.sdo"); +// synopsys translate_on + +wire \inst|44~0_combout ; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \INPUT_B4~combout ; +wire \isAdd~combout ; +wire \inst21|o4~2_combout ; +wire \INPUT_A3~combout ; +wire \INPUT_B3~combout ; +wire \inst|21~0_combout ; +wire \INPUT_B2~combout ; +wire \inst21|o2~2_combout ; +wire \INPUT_A2~combout ; +wire \inst|25~combout ; +wire \inst|1~0_combout ; +wire \inst|45~combout ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \inst1|16~regout ; +wire \INPUT_B1~combout ; +wire \INPUT_A1~combout ; +wire \inst|18~0_combout ; +wire \inst|43~combout ; +wire \inst1|8~regout ; +wire \inst|42~combout ; +wire \inst1|1~regout ; +wire \inst|44~combout ; +wire \inst1|15~regout ; +wire \inst17|a~12_combout ; +wire \inst20|o[3]~15_combout ; +wire \inst20|o[2]~16_combout ; +wire \inst20|o[1]~17_combout ; +wire \inst17|b~3_combout ; +wire \inst17|c~1_combout ; +wire \inst17|d~0_combout ; +wire \inst17|e~0_combout ; +wire \inst17|f~0_combout ; +wire \inst17|g~0_combout ; +wire \INPUT_A4~combout ; +wire \inst23|v~1_combout ; + + +// Location: LCCOMB_X43_Y26_N6 +cycloneii_lcell_comb \inst|44~0 ( +// Equation(s): +// \inst|44~0_combout = \INPUT_A3~combout $ (\INPUT_B3~combout $ (\isAdd~combout )) + + .dataa(vcc), + .datab(\INPUT_A3~combout ), + .datac(\INPUT_B3~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|44~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|44~0 .lut_mask = 16'hC33C; +defparam \inst|44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B4~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B4~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B4)); +// synopsys translate_off +defparam \INPUT_B4~I .input_async_reset = "none"; +defparam \INPUT_B4~I .input_power_up = "low"; +defparam \INPUT_B4~I .input_register_mode = "none"; +defparam \INPUT_B4~I .input_sync_reset = "none"; +defparam \INPUT_B4~I .oe_async_reset = "none"; +defparam \INPUT_B4~I .oe_power_up = "low"; +defparam \INPUT_B4~I .oe_register_mode = "none"; +defparam \INPUT_B4~I .oe_sync_reset = "none"; +defparam \INPUT_B4~I .operation_mode = "input"; +defparam \INPUT_B4~I .output_async_reset = "none"; +defparam \INPUT_B4~I .output_power_up = "low"; +defparam \INPUT_B4~I .output_register_mode = "none"; +defparam \INPUT_B4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B18, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \isAdd~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\isAdd~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(isAdd)); +// synopsys translate_off +defparam \isAdd~I .input_async_reset = "none"; +defparam \isAdd~I .input_power_up = "low"; +defparam \isAdd~I .input_register_mode = "none"; +defparam \isAdd~I .input_sync_reset = "none"; +defparam \isAdd~I .oe_async_reset = "none"; +defparam \isAdd~I .oe_power_up = "low"; +defparam \isAdd~I .oe_register_mode = "none"; +defparam \isAdd~I .oe_sync_reset = "none"; +defparam \isAdd~I .operation_mode = "input"; +defparam \isAdd~I .output_async_reset = "none"; +defparam \isAdd~I .output_power_up = "low"; +defparam \isAdd~I .output_register_mode = "none"; +defparam \isAdd~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N2 +cycloneii_lcell_comb \inst21|o4~2 ( +// Equation(s): +// \inst21|o4~2_combout = \INPUT_B4~combout $ (\isAdd~combout ) + + .dataa(vcc), + .datab(\INPUT_B4~combout ), + .datac(vcc), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst21|o4~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst21|o4~2 .lut_mask = 16'h33CC; +defparam \inst21|o4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_D16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A3~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A3~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A3)); +// synopsys translate_off +defparam \INPUT_A3~I .input_async_reset = "none"; +defparam \INPUT_A3~I .input_power_up = "low"; +defparam \INPUT_A3~I .input_register_mode = "none"; +defparam \INPUT_A3~I .input_sync_reset = "none"; +defparam \INPUT_A3~I .oe_async_reset = "none"; +defparam \INPUT_A3~I .oe_power_up = "low"; +defparam \INPUT_A3~I .oe_register_mode = "none"; +defparam \INPUT_A3~I .oe_sync_reset = "none"; +defparam \INPUT_A3~I .operation_mode = "input"; +defparam \INPUT_A3~I .output_async_reset = "none"; +defparam \INPUT_A3~I .output_power_up = "low"; +defparam \INPUT_A3~I .output_register_mode = "none"; +defparam \INPUT_A3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B3~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B3~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B3)); +// synopsys translate_off +defparam \INPUT_B3~I .input_async_reset = "none"; +defparam \INPUT_B3~I .input_power_up = "low"; +defparam \INPUT_B3~I .input_register_mode = "none"; +defparam \INPUT_B3~I .input_sync_reset = "none"; +defparam \INPUT_B3~I .oe_async_reset = "none"; +defparam \INPUT_B3~I .oe_power_up = "low"; +defparam \INPUT_B3~I .oe_register_mode = "none"; +defparam \INPUT_B3~I .oe_sync_reset = "none"; +defparam \INPUT_B3~I .operation_mode = "input"; +defparam \INPUT_B3~I .output_async_reset = "none"; +defparam \INPUT_B3~I .output_power_up = "low"; +defparam \INPUT_B3~I .output_register_mode = "none"; +defparam \INPUT_B3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N24 +cycloneii_lcell_comb \inst|21~0 ( +// Equation(s): +// \inst|21~0_combout = (!\INPUT_A3~combout & (\INPUT_B3~combout $ (\isAdd~combout ))) + + .dataa(vcc), + .datab(\INPUT_A3~combout ), + .datac(\INPUT_B3~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|21~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|21~0 .lut_mask = 16'h0330; +defparam \inst|21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_E15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B2~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B2~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B2)); +// synopsys translate_off +defparam \INPUT_B2~I .input_async_reset = "none"; +defparam \INPUT_B2~I .input_power_up = "low"; +defparam \INPUT_B2~I .input_register_mode = "none"; +defparam \INPUT_B2~I .input_sync_reset = "none"; +defparam \INPUT_B2~I .oe_async_reset = "none"; +defparam \INPUT_B2~I .oe_power_up = "low"; +defparam \INPUT_B2~I .oe_register_mode = "none"; +defparam \INPUT_B2~I .oe_sync_reset = "none"; +defparam \INPUT_B2~I .operation_mode = "input"; +defparam \INPUT_B2~I .output_async_reset = "none"; +defparam \INPUT_B2~I .output_power_up = "low"; +defparam \INPUT_B2~I .output_register_mode = "none"; +defparam \INPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N18 +cycloneii_lcell_comb \inst21|o2~2 ( +// Equation(s): +// \inst21|o2~2_combout = \INPUT_B2~combout $ (\isAdd~combout ) + + .dataa(vcc), + .datab(\INPUT_B2~combout ), + .datac(vcc), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst21|o2~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst21|o2~2 .lut_mask = 16'h33CC; +defparam \inst21|o2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A2~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A2~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A2)); +// synopsys translate_off +defparam \INPUT_A2~I .input_async_reset = "none"; +defparam \INPUT_A2~I .input_power_up = "low"; +defparam \INPUT_A2~I .input_register_mode = "none"; +defparam \INPUT_A2~I .input_sync_reset = "none"; +defparam \INPUT_A2~I .oe_async_reset = "none"; +defparam \INPUT_A2~I .oe_power_up = "low"; +defparam \INPUT_A2~I .oe_register_mode = "none"; +defparam \INPUT_A2~I .oe_sync_reset = "none"; +defparam \INPUT_A2~I .operation_mode = "input"; +defparam \INPUT_A2~I .output_async_reset = "none"; +defparam \INPUT_A2~I .output_power_up = "low"; +defparam \INPUT_A2~I .output_register_mode = "none"; +defparam \INPUT_A2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N30 +cycloneii_lcell_comb \inst|25 ( +// Equation(s): +// \inst|25~combout = (\INPUT_A3~combout & (\INPUT_B3~combout $ (!\isAdd~combout ))) + + .dataa(vcc), + .datab(\INPUT_A3~combout ), + .datac(\INPUT_B3~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|25~combout ), + .cout()); +// synopsys translate_off +defparam \inst|25 .lut_mask = 16'hC00C; +defparam \inst|25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N0 +cycloneii_lcell_comb \inst|1~0 ( +// Equation(s): +// \inst|1~0_combout = (!\inst|25~combout & ((\inst|18~0_combout & ((\inst21|o2~2_combout ) # (!\INPUT_A2~combout ))) # (!\inst|18~0_combout & (\inst21|o2~2_combout & !\INPUT_A2~combout )))) + + .dataa(\inst|18~0_combout ), + .datab(\inst21|o2~2_combout ), + .datac(\INPUT_A2~combout ), + .datad(\inst|25~combout ), + .cin(gnd), + .combout(\inst|1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|1~0 .lut_mask = 16'h008E; +defparam \inst|1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N10 +cycloneii_lcell_comb \inst|45 ( +// Equation(s): +// \inst|45~combout = \INPUT_A4~combout $ (\inst21|o4~2_combout $ (((\inst|21~0_combout ) # (\inst|1~0_combout )))) + + .dataa(\INPUT_A4~combout ), + .datab(\inst21|o4~2_combout ), + .datac(\inst|21~0_combout ), + .datad(\inst|1~0_combout ), + .cin(gnd), + .combout(\inst|45~combout ), + .cout()); +// synopsys translate_off +defparam \inst|45 .lut_mask = 16'h9996; +defparam \inst|45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \reset~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\reset~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(reset)); +// synopsys translate_off +defparam \reset~I .input_async_reset = "none"; +defparam \reset~I .input_power_up = "low"; +defparam \reset~I .input_register_mode = "none"; +defparam \reset~I .input_sync_reset = "none"; +defparam \reset~I .oe_async_reset = "none"; +defparam \reset~I .oe_power_up = "low"; +defparam \reset~I .oe_register_mode = "none"; +defparam \reset~I .oe_sync_reset = "none"; +defparam \reset~I .operation_mode = "input"; +defparam \reset~I .output_async_reset = "none"; +defparam \reset~I .output_power_up = "low"; +defparam \reset~I .output_register_mode = "none"; +defparam \reset~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneii_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N11 +cycloneii_lcell_ff \inst1|16 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|45~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|16~regout )); + +// Location: PIN_G16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B1~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B1~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B1)); +// synopsys translate_off +defparam \INPUT_B1~I .input_async_reset = "none"; +defparam \INPUT_B1~I .input_power_up = "low"; +defparam \INPUT_B1~I .input_register_mode = "none"; +defparam \INPUT_B1~I .input_sync_reset = "none"; +defparam \INPUT_B1~I .oe_async_reset = "none"; +defparam \INPUT_B1~I .oe_power_up = "low"; +defparam \INPUT_B1~I .oe_register_mode = "none"; +defparam \INPUT_B1~I .oe_sync_reset = "none"; +defparam \INPUT_B1~I .operation_mode = "input"; +defparam \INPUT_B1~I .output_async_reset = "none"; +defparam \INPUT_B1~I .output_power_up = "low"; +defparam \INPUT_B1~I .output_register_mode = "none"; +defparam \INPUT_B1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A1~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A1~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A1)); +// synopsys translate_off +defparam \INPUT_A1~I .input_async_reset = "none"; +defparam \INPUT_A1~I .input_power_up = "low"; +defparam \INPUT_A1~I .input_register_mode = "none"; +defparam \INPUT_A1~I .input_sync_reset = "none"; +defparam \INPUT_A1~I .oe_async_reset = "none"; +defparam \INPUT_A1~I .oe_power_up = "low"; +defparam \INPUT_A1~I .oe_register_mode = "none"; +defparam \INPUT_A1~I .oe_sync_reset = "none"; +defparam \INPUT_A1~I .operation_mode = "input"; +defparam \INPUT_A1~I .output_async_reset = "none"; +defparam \INPUT_A1~I .output_power_up = "low"; +defparam \INPUT_A1~I .output_register_mode = "none"; +defparam \INPUT_A1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N28 +cycloneii_lcell_comb \inst|18~0 ( +// Equation(s): +// \inst|18~0_combout = (\INPUT_B1~combout & (!\INPUT_A1~combout )) # (!\INPUT_B1~combout & ((\isAdd~combout ))) + + .dataa(vcc), + .datab(\INPUT_B1~combout ), + .datac(\INPUT_A1~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|18~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|18~0 .lut_mask = 16'h3F0C; +defparam \inst|18~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N22 +cycloneii_lcell_comb \inst|43 ( +// Equation(s): +// \inst|43~combout = \INPUT_B2~combout $ (\inst|18~0_combout $ (\INPUT_A2~combout $ (\isAdd~combout ))) + + .dataa(\INPUT_B2~combout ), + .datab(\inst|18~0_combout ), + .datac(\INPUT_A2~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|43~combout ), + .cout()); +// synopsys translate_off +defparam \inst|43 .lut_mask = 16'h6996; +defparam \inst|43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N23 +cycloneii_lcell_ff \inst1|8 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|43~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|8~regout )); + +// Location: LCCOMB_X43_Y26_N12 +cycloneii_lcell_comb \inst|42 ( +// Equation(s): +// \inst|42~combout = \INPUT_A1~combout $ (\INPUT_B1~combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\INPUT_A1~combout ), + .datad(\INPUT_B1~combout ), + .cin(gnd), + .combout(\inst|42~combout ), + .cout()); +// synopsys translate_off +defparam \inst|42 .lut_mask = 16'h0FF0; +defparam \inst|42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N13 +cycloneii_lcell_ff \inst1|1 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|42~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|1~regout )); + +// Location: LCCOMB_X43_Y26_N8 +cycloneii_lcell_comb \inst|44 ( +// Equation(s): +// \inst|44~combout = \inst|44~0_combout $ (((\inst|18~0_combout & ((\inst21|o2~2_combout ) # (!\INPUT_A2~combout ))) # (!\inst|18~0_combout & (!\INPUT_A2~combout & \inst21|o2~2_combout )))) + + .dataa(\inst|44~0_combout ), + .datab(\inst|18~0_combout ), + .datac(\INPUT_A2~combout ), + .datad(\inst21|o2~2_combout ), + .cin(gnd), + .combout(\inst|44~combout ), + .cout()); +// synopsys translate_off +defparam \inst|44 .lut_mask = 16'h65A6; +defparam \inst|44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N9 +cycloneii_lcell_ff \inst1|15 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|44~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|15~regout )); + +// Location: LCCOMB_X39_Y26_N8 +cycloneii_lcell_comb \inst17|a~12 ( +// Equation(s): +// \inst17|a~12_combout = (\inst1|16~regout & (\inst1|15~regout & (\inst1|8~regout $ (!\inst1|1~regout )))) # (!\inst1|16~regout & (!\inst1|8~regout & (\inst1|1~regout $ (\inst1|15~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|a~12 .lut_mask = 16'h8310; +defparam \inst17|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N18 +cycloneii_lcell_comb \inst20|o[3]~15 ( +// Equation(s): +// \inst20|o[3]~15_combout = (\inst1|16~regout & (!\inst1|8~regout & (!\inst1|1~regout & !\inst1|15~regout ))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst20|o[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \inst20|o[3]~15 .lut_mask = 16'h0002; +defparam \inst20|o[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N12 +cycloneii_lcell_comb \inst20|o[2]~16 ( +// Equation(s): +// \inst20|o[2]~16_combout = \inst1|15~regout $ (((\inst1|16~regout & ((\inst1|8~regout ) # (\inst1|1~regout ))))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst20|o[2]~16_combout ), + .cout()); +// synopsys translate_off +defparam \inst20|o[2]~16 .lut_mask = 16'h57A8; +defparam \inst20|o[2]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N22 +cycloneii_lcell_comb \inst20|o[1]~17 ( +// Equation(s): +// \inst20|o[1]~17_combout = \inst1|8~regout $ (((\inst1|16~regout & \inst1|1~regout ))) + + .dataa(\inst1|16~regout ), + .datab(vcc), + .datac(\inst1|1~regout ), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst20|o[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \inst20|o[1]~17 .lut_mask = 16'h5FA0; +defparam \inst20|o[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N0 +cycloneii_lcell_comb \inst17|b~3 ( +// Equation(s): +// \inst17|b~3_combout = (\inst1|16~regout & (\inst1|8~regout & ((!\inst1|15~regout )))) # (!\inst1|16~regout & (\inst1|15~regout & (\inst1|8~regout $ (\inst1|1~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|b~3 .lut_mask = 16'h1488; +defparam \inst17|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N10 +cycloneii_lcell_comb \inst17|c~1 ( +// Equation(s): +// \inst17|c~1_combout = (\inst1|8~regout & (!\inst1|1~regout & (\inst1|16~regout $ (!\inst1|15~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|c~1 .lut_mask = 16'h0804; +defparam \inst17|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N20 +cycloneii_lcell_comb \inst17|d~0 ( +// Equation(s): +// \inst17|d~0_combout = (\inst1|8~regout & (\inst1|1~regout & \inst1|15~regout )) # (!\inst1|8~regout & (\inst1|1~regout $ (\inst1|15~regout ))) + + .dataa(vcc), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|d~0 .lut_mask = 16'hC330; +defparam \inst17|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N30 +cycloneii_lcell_comb \inst17|e~0 ( +// Equation(s): +// \inst17|e~0_combout = (\inst1|1~regout ) # ((!\inst1|8~regout & \inst1|15~regout )) + + .dataa(vcc), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|e~0 .lut_mask = 16'hF3F0; +defparam \inst17|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N24 +cycloneii_lcell_comb \inst17|f~0 ( +// Equation(s): +// \inst17|f~0_combout = (\inst1|8~regout & ((\inst1|16~regout & ((\inst1|15~regout ))) # (!\inst1|16~regout & ((\inst1|1~regout ) # (!\inst1|15~regout ))))) # (!\inst1|8~regout & (\inst1|1~regout & ((\inst1|16~regout ) # (!\inst1|15~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|f~0 .lut_mask = 16'hE874; +defparam \inst17|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N2 +cycloneii_lcell_comb \inst17|g~0 ( +// Equation(s): +// \inst17|g~0_combout = (\inst1|8~regout & (((!\inst1|15~regout ) # (!\inst1|1~regout )))) # (!\inst1|8~regout & ((\inst1|15~regout ) # ((\inst1|16~regout & !\inst1|1~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|g~0 .lut_mask = 16'h3FCE; +defparam \inst17|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_D20, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A4~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A4~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A4)); +// synopsys translate_off +defparam \INPUT_A4~I .input_async_reset = "none"; +defparam \INPUT_A4~I .input_power_up = "low"; +defparam \INPUT_A4~I .input_register_mode = "none"; +defparam \INPUT_A4~I .input_sync_reset = "none"; +defparam \INPUT_A4~I .oe_async_reset = "none"; +defparam \INPUT_A4~I .oe_power_up = "low"; +defparam \INPUT_A4~I .oe_register_mode = "none"; +defparam \INPUT_A4~I .oe_sync_reset = "none"; +defparam \INPUT_A4~I .operation_mode = "input"; +defparam \INPUT_A4~I .output_async_reset = "none"; +defparam \INPUT_A4~I .output_power_up = "low"; +defparam \INPUT_A4~I .output_register_mode = "none"; +defparam \INPUT_A4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N20 +cycloneii_lcell_comb \inst23|v~1 ( +// Equation(s): +// \inst23|v~1_combout = (\INPUT_A4~combout & (!\inst21|o4~2_combout & ((\inst|21~0_combout ) # (\inst|1~0_combout )))) # (!\INPUT_A4~combout & (\inst21|o4~2_combout & (!\inst|21~0_combout & !\inst|1~0_combout ))) + + .dataa(\INPUT_A4~combout ), + .datab(\inst21|o4~2_combout ), + .datac(\inst|21~0_combout ), + .datad(\inst|1~0_combout ), + .cin(gnd), + .combout(\inst23|v~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst23|v~1 .lut_mask = 16'h2224; +defparam \inst23|v~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_A17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A~I ( + .datain(\inst17|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A)); +// synopsys translate_off +defparam \OUTPUT_A~I .input_async_reset = "none"; +defparam \OUTPUT_A~I .input_power_up = "low"; +defparam \OUTPUT_A~I .input_register_mode = "none"; +defparam \OUTPUT_A~I .input_sync_reset = "none"; +defparam \OUTPUT_A~I .oe_async_reset = "none"; +defparam \OUTPUT_A~I .oe_power_up = "low"; +defparam \OUTPUT_A~I .oe_register_mode = "none"; +defparam \OUTPUT_A~I .oe_sync_reset = "none"; +defparam \OUTPUT_A~I .operation_mode = "output"; +defparam \OUTPUT_A~I .output_async_reset = "none"; +defparam \OUTPUT_A~I .output_power_up = "low"; +defparam \OUTPUT_A~I .output_register_mode = "none"; +defparam \OUTPUT_A~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[3]~I ( + .datain(\inst20|o[3]~15_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[3])); +// synopsys translate_off +defparam \i[3]~I .input_async_reset = "none"; +defparam \i[3]~I .input_power_up = "low"; +defparam \i[3]~I .input_register_mode = "none"; +defparam \i[3]~I .input_sync_reset = "none"; +defparam \i[3]~I .oe_async_reset = "none"; +defparam \i[3]~I .oe_power_up = "low"; +defparam \i[3]~I .oe_register_mode = "none"; +defparam \i[3]~I .oe_sync_reset = "none"; +defparam \i[3]~I .operation_mode = "output"; +defparam \i[3]~I .output_async_reset = "none"; +defparam \i[3]~I .output_power_up = "low"; +defparam \i[3]~I .output_register_mode = "none"; +defparam \i[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_G15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[2]~I ( + .datain(\inst20|o[2]~16_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[2])); +// synopsys translate_off +defparam \i[2]~I .input_async_reset = "none"; +defparam \i[2]~I .input_power_up = "low"; +defparam \i[2]~I .input_register_mode = "none"; +defparam \i[2]~I .input_sync_reset = "none"; +defparam \i[2]~I .oe_async_reset = "none"; +defparam \i[2]~I .oe_power_up = "low"; +defparam \i[2]~I .oe_register_mode = "none"; +defparam \i[2]~I .oe_sync_reset = "none"; +defparam \i[2]~I .operation_mode = "output"; +defparam \i[2]~I .output_async_reset = "none"; +defparam \i[2]~I .output_power_up = "low"; +defparam \i[2]~I .output_register_mode = "none"; +defparam \i[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[1]~I ( + .datain(\inst20|o[1]~17_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[1])); +// synopsys translate_off +defparam \i[1]~I .input_async_reset = "none"; +defparam \i[1]~I .input_power_up = "low"; +defparam \i[1]~I .input_register_mode = "none"; +defparam \i[1]~I .input_sync_reset = "none"; +defparam \i[1]~I .oe_async_reset = "none"; +defparam \i[1]~I .oe_power_up = "low"; +defparam \i[1]~I .oe_register_mode = "none"; +defparam \i[1]~I .oe_sync_reset = "none"; +defparam \i[1]~I .operation_mode = "output"; +defparam \i[1]~I .output_async_reset = "none"; +defparam \i[1]~I .output_power_up = "low"; +defparam \i[1]~I .output_register_mode = "none"; +defparam \i[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[0]~I ( + .datain(\inst1|1~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[0])); +// synopsys translate_off +defparam \i[0]~I .input_async_reset = "none"; +defparam \i[0]~I .input_power_up = "low"; +defparam \i[0]~I .input_register_mode = "none"; +defparam \i[0]~I .input_sync_reset = "none"; +defparam \i[0]~I .oe_async_reset = "none"; +defparam \i[0]~I .oe_power_up = "low"; +defparam \i[0]~I .oe_register_mode = "none"; +defparam \i[0]~I .oe_sync_reset = "none"; +defparam \i[0]~I .operation_mode = "output"; +defparam \i[0]~I .output_async_reset = "none"; +defparam \i[0]~I .output_power_up = "low"; +defparam \i[0]~I .output_register_mode = "none"; +defparam \i[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B~I ( + .datain(\inst17|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B)); +// synopsys translate_off +defparam \OUTPUT_B~I .input_async_reset = "none"; +defparam \OUTPUT_B~I .input_power_up = "low"; +defparam \OUTPUT_B~I .input_register_mode = "none"; +defparam \OUTPUT_B~I .input_sync_reset = "none"; +defparam \OUTPUT_B~I .oe_async_reset = "none"; +defparam \OUTPUT_B~I .oe_power_up = "low"; +defparam \OUTPUT_B~I .oe_register_mode = "none"; +defparam \OUTPUT_B~I .oe_sync_reset = "none"; +defparam \OUTPUT_B~I .operation_mode = "output"; +defparam \OUTPUT_B~I .output_async_reset = "none"; +defparam \OUTPUT_B~I .output_power_up = "low"; +defparam \OUTPUT_B~I .output_register_mode = "none"; +defparam \OUTPUT_B~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C~I ( + .datain(\inst17|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C)); +// synopsys translate_off +defparam \OUTPUT_C~I .input_async_reset = "none"; +defparam \OUTPUT_C~I .input_power_up = "low"; +defparam \OUTPUT_C~I .input_register_mode = "none"; +defparam \OUTPUT_C~I .input_sync_reset = "none"; +defparam \OUTPUT_C~I .oe_async_reset = "none"; +defparam \OUTPUT_C~I .oe_power_up = "low"; +defparam \OUTPUT_C~I .oe_register_mode = "none"; +defparam \OUTPUT_C~I .oe_sync_reset = "none"; +defparam \OUTPUT_C~I .operation_mode = "output"; +defparam \OUTPUT_C~I .output_async_reset = "none"; +defparam \OUTPUT_C~I .output_power_up = "low"; +defparam \OUTPUT_C~I .output_register_mode = "none"; +defparam \OUTPUT_C~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D~I ( + .datain(\inst17|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D)); +// synopsys translate_off +defparam \OUTPUT_D~I .input_async_reset = "none"; +defparam \OUTPUT_D~I .input_power_up = "low"; +defparam \OUTPUT_D~I .input_register_mode = "none"; +defparam \OUTPUT_D~I .input_sync_reset = "none"; +defparam \OUTPUT_D~I .oe_async_reset = "none"; +defparam \OUTPUT_D~I .oe_power_up = "low"; +defparam \OUTPUT_D~I .oe_register_mode = "none"; +defparam \OUTPUT_D~I .oe_sync_reset = "none"; +defparam \OUTPUT_D~I .operation_mode = "output"; +defparam \OUTPUT_D~I .output_async_reset = "none"; +defparam \OUTPUT_D~I .output_power_up = "low"; +defparam \OUTPUT_D~I .output_register_mode = "none"; +defparam \OUTPUT_D~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E~I ( + .datain(\inst17|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E)); +// synopsys translate_off +defparam \OUTPUT_E~I .input_async_reset = "none"; +defparam \OUTPUT_E~I .input_power_up = "low"; +defparam \OUTPUT_E~I .input_register_mode = "none"; +defparam \OUTPUT_E~I .input_sync_reset = "none"; +defparam \OUTPUT_E~I .oe_async_reset = "none"; +defparam \OUTPUT_E~I .oe_power_up = "low"; +defparam \OUTPUT_E~I .oe_register_mode = "none"; +defparam \OUTPUT_E~I .oe_sync_reset = "none"; +defparam \OUTPUT_E~I .operation_mode = "output"; +defparam \OUTPUT_E~I .output_async_reset = "none"; +defparam \OUTPUT_E~I .output_power_up = "low"; +defparam \OUTPUT_E~I .output_register_mode = "none"; +defparam \OUTPUT_E~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F~I ( + .datain(\inst17|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F)); +// synopsys translate_off +defparam \OUTPUT_F~I .input_async_reset = "none"; +defparam \OUTPUT_F~I .input_power_up = "low"; +defparam \OUTPUT_F~I .input_register_mode = "none"; +defparam \OUTPUT_F~I .input_sync_reset = "none"; +defparam \OUTPUT_F~I .oe_async_reset = "none"; +defparam \OUTPUT_F~I .oe_power_up = "low"; +defparam \OUTPUT_F~I .oe_register_mode = "none"; +defparam \OUTPUT_F~I .oe_sync_reset = "none"; +defparam \OUTPUT_F~I .operation_mode = "output"; +defparam \OUTPUT_F~I .output_async_reset = "none"; +defparam \OUTPUT_F~I .output_power_up = "low"; +defparam \OUTPUT_F~I .output_register_mode = "none"; +defparam \OUTPUT_F~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G~I ( + .datain(!\inst17|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G)); +// synopsys translate_off +defparam \OUTPUT_G~I .input_async_reset = "none"; +defparam \OUTPUT_G~I .input_power_up = "low"; +defparam \OUTPUT_G~I .input_register_mode = "none"; +defparam \OUTPUT_G~I .input_sync_reset = "none"; +defparam \OUTPUT_G~I .oe_async_reset = "none"; +defparam \OUTPUT_G~I .oe_power_up = "low"; +defparam \OUTPUT_G~I .oe_register_mode = "none"; +defparam \OUTPUT_G~I .oe_sync_reset = "none"; +defparam \OUTPUT_G~I .operation_mode = "output"; +defparam \OUTPUT_G~I .output_async_reset = "none"; +defparam \OUTPUT_G~I .output_power_up = "low"; +defparam \OUTPUT_G~I .output_register_mode = "none"; +defparam \OUTPUT_G~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A2)); +// synopsys translate_off +defparam \OUTPUT_A2~I .input_async_reset = "none"; +defparam \OUTPUT_A2~I .input_power_up = "low"; +defparam \OUTPUT_A2~I .input_register_mode = "none"; +defparam \OUTPUT_A2~I .input_sync_reset = "none"; +defparam \OUTPUT_A2~I .oe_async_reset = "none"; +defparam \OUTPUT_A2~I .oe_power_up = "low"; +defparam \OUTPUT_A2~I .oe_register_mode = "none"; +defparam \OUTPUT_A2~I .oe_sync_reset = "none"; +defparam \OUTPUT_A2~I .operation_mode = "output"; +defparam \OUTPUT_A2~I .output_async_reset = "none"; +defparam \OUTPUT_A2~I .output_power_up = "low"; +defparam \OUTPUT_A2~I .output_register_mode = "none"; +defparam \OUTPUT_A2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B2)); +// synopsys translate_off +defparam \OUTPUT_B2~I .input_async_reset = "none"; +defparam \OUTPUT_B2~I .input_power_up = "low"; +defparam \OUTPUT_B2~I .input_register_mode = "none"; +defparam \OUTPUT_B2~I .input_sync_reset = "none"; +defparam \OUTPUT_B2~I .oe_async_reset = "none"; +defparam \OUTPUT_B2~I .oe_power_up = "low"; +defparam \OUTPUT_B2~I .oe_register_mode = "none"; +defparam \OUTPUT_B2~I .oe_sync_reset = "none"; +defparam \OUTPUT_B2~I .operation_mode = "output"; +defparam \OUTPUT_B2~I .output_async_reset = "none"; +defparam \OUTPUT_B2~I .output_power_up = "low"; +defparam \OUTPUT_B2~I .output_register_mode = "none"; +defparam \OUTPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C2)); +// synopsys translate_off +defparam \OUTPUT_C2~I .input_async_reset = "none"; +defparam \OUTPUT_C2~I .input_power_up = "low"; +defparam \OUTPUT_C2~I .input_register_mode = "none"; +defparam \OUTPUT_C2~I .input_sync_reset = "none"; +defparam \OUTPUT_C2~I .oe_async_reset = "none"; +defparam \OUTPUT_C2~I .oe_power_up = "low"; +defparam \OUTPUT_C2~I .oe_register_mode = "none"; +defparam \OUTPUT_C2~I .oe_sync_reset = "none"; +defparam \OUTPUT_C2~I .operation_mode = "output"; +defparam \OUTPUT_C2~I .output_async_reset = "none"; +defparam \OUTPUT_C2~I .output_power_up = "low"; +defparam \OUTPUT_C2~I .output_register_mode = "none"; +defparam \OUTPUT_C2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D2)); +// synopsys translate_off +defparam \OUTPUT_D2~I .input_async_reset = "none"; +defparam \OUTPUT_D2~I .input_power_up = "low"; +defparam \OUTPUT_D2~I .input_register_mode = "none"; +defparam \OUTPUT_D2~I .input_sync_reset = "none"; +defparam \OUTPUT_D2~I .oe_async_reset = "none"; +defparam \OUTPUT_D2~I .oe_power_up = "low"; +defparam \OUTPUT_D2~I .oe_register_mode = "none"; +defparam \OUTPUT_D2~I .oe_sync_reset = "none"; +defparam \OUTPUT_D2~I .operation_mode = "output"; +defparam \OUTPUT_D2~I .output_async_reset = "none"; +defparam \OUTPUT_D2~I .output_power_up = "low"; +defparam \OUTPUT_D2~I .output_register_mode = "none"; +defparam \OUTPUT_D2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E2)); +// synopsys translate_off +defparam \OUTPUT_E2~I .input_async_reset = "none"; +defparam \OUTPUT_E2~I .input_power_up = "low"; +defparam \OUTPUT_E2~I .input_register_mode = "none"; +defparam \OUTPUT_E2~I .input_sync_reset = "none"; +defparam \OUTPUT_E2~I .oe_async_reset = "none"; +defparam \OUTPUT_E2~I .oe_power_up = "low"; +defparam \OUTPUT_E2~I .oe_register_mode = "none"; +defparam \OUTPUT_E2~I .oe_sync_reset = "none"; +defparam \OUTPUT_E2~I .operation_mode = "output"; +defparam \OUTPUT_E2~I .output_async_reset = "none"; +defparam \OUTPUT_E2~I .output_power_up = "low"; +defparam \OUTPUT_E2~I .output_register_mode = "none"; +defparam \OUTPUT_E2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F2)); +// synopsys translate_off +defparam \OUTPUT_F2~I .input_async_reset = "none"; +defparam \OUTPUT_F2~I .input_power_up = "low"; +defparam \OUTPUT_F2~I .input_register_mode = "none"; +defparam \OUTPUT_F2~I .input_sync_reset = "none"; +defparam \OUTPUT_F2~I .oe_async_reset = "none"; +defparam \OUTPUT_F2~I .oe_power_up = "low"; +defparam \OUTPUT_F2~I .oe_register_mode = "none"; +defparam \OUTPUT_F2~I .oe_sync_reset = "none"; +defparam \OUTPUT_F2~I .operation_mode = "output"; +defparam \OUTPUT_F2~I .output_async_reset = "none"; +defparam \OUTPUT_F2~I .output_power_up = "low"; +defparam \OUTPUT_F2~I .output_register_mode = "none"; +defparam \OUTPUT_F2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G2~I ( + .datain(\inst1|16~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G2)); +// synopsys translate_off +defparam \OUTPUT_G2~I .input_async_reset = "none"; +defparam \OUTPUT_G2~I .input_power_up = "low"; +defparam \OUTPUT_G2~I .input_register_mode = "none"; +defparam \OUTPUT_G2~I .input_sync_reset = "none"; +defparam \OUTPUT_G2~I .oe_async_reset = "none"; +defparam \OUTPUT_G2~I .oe_power_up = "low"; +defparam \OUTPUT_G2~I .oe_register_mode = "none"; +defparam \OUTPUT_G2~I .oe_sync_reset = "none"; +defparam \OUTPUT_G2~I .operation_mode = "output"; +defparam \OUTPUT_G2~I .output_async_reset = "none"; +defparam \OUTPUT_G2~I .output_power_up = "low"; +defparam \OUTPUT_G2~I .output_register_mode = "none"; +defparam \OUTPUT_G2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \overflow~I ( + .datain(\inst23|v~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(overflow)); +// synopsys translate_off +defparam \overflow~I .input_async_reset = "none"; +defparam \overflow~I .input_power_up = "low"; +defparam \overflow~I .input_register_mode = "none"; +defparam \overflow~I .input_sync_reset = "none"; +defparam \overflow~I .oe_async_reset = "none"; +defparam \overflow~I .oe_power_up = "low"; +defparam \overflow~I .oe_register_mode = "none"; +defparam \overflow~I .oe_sync_reset = "none"; +defparam \overflow~I .operation_mode = "output"; +defparam \overflow~I .output_async_reset = "none"; +defparam \overflow~I .output_power_up = "low"; +defparam \overflow~I .output_register_mode = "none"; +defparam \overflow~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \pin_name1~I ( + .datain(\inst1|1~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(pin_name1)); +// synopsys translate_off +defparam \pin_name1~I .input_async_reset = "none"; +defparam \pin_name1~I .input_power_up = "low"; +defparam \pin_name1~I .input_register_mode = "none"; +defparam \pin_name1~I .input_sync_reset = "none"; +defparam \pin_name1~I .oe_async_reset = "none"; +defparam \pin_name1~I .oe_power_up = "low"; +defparam \pin_name1~I .oe_register_mode = "none"; +defparam \pin_name1~I .oe_sync_reset = "none"; +defparam \pin_name1~I .operation_mode = "output"; +defparam \pin_name1~I .output_async_reset = "none"; +defparam \pin_name1~I .output_power_up = "low"; +defparam \pin_name1~I .output_register_mode = "none"; +defparam \pin_name1~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/YL_adder/simulation/modelsim/YL_adder_fast.vo b/YL_adder/simulation/modelsim/YL_adder_fast.vo new file mode 100644 index 0000000..3e9baee --- /dev/null +++ b/YL_adder/simulation/modelsim/YL_adder_fast.vo @@ -0,0 +1,1747 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/04/2020 17:05:47" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_adder ( + OUTPUT_A, + i, + reset, + INPUT_B1, + INPUT_B2, + INPUT_B3, + INPUT_B4, + isAdd, + INPUT_A1, + INPUT_A2, + INPUT_A3, + INPUT_A4, + clk, + OUTPUT_B, + OUTPUT_C, + OUTPUT_D, + OUTPUT_E, + OUTPUT_F, + OUTPUT_G, + OUTPUT_A2, + OUTPUT_B2, + OUTPUT_C2, + OUTPUT_D2, + OUTPUT_E2, + OUTPUT_F2, + OUTPUT_G2, + overflow, + pin_name1); +output OUTPUT_A; +output [3:0] i; +input reset; +input INPUT_B1; +input INPUT_B2; +input INPUT_B3; +input INPUT_B4; +input isAdd; +input INPUT_A1; +input INPUT_A2; +input INPUT_A3; +input INPUT_A4; +input clk; +output OUTPUT_B; +output OUTPUT_C; +output OUTPUT_D; +output OUTPUT_E; +output OUTPUT_F; +output OUTPUT_G; +output OUTPUT_A2; +output OUTPUT_B2; +output OUTPUT_C2; +output OUTPUT_D2; +output OUTPUT_E2; +output OUTPUT_F2; +output OUTPUT_G2; +output overflow; +output pin_name1; + +// Design Ports Information +// OUTPUT_A => Location: PIN_A17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[3] => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[2] => Location: PIN_G15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[1] => Location: PIN_C16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// i[0] => Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B => Location: PIN_H13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C => Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D => Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E => Location: PIN_D15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F => Location: PIN_E14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G => Location: PIN_F14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_A2 => Location: PIN_P18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B2 => Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C2 => Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D2 => Location: PIN_AA17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E2 => Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F2 => Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G2 => Location: PIN_F15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// overflow => Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// pin_name1 => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// INPUT_A4 => Location: PIN_D20, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B3 => Location: PIN_D14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// isAdd => Location: PIN_B18, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A3 => Location: PIN_D16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B2 => Location: PIN_E15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B1 => Location: PIN_G16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A1 => Location: PIN_H14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A2 => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B4 => Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// reset => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("YL_adder_v_fast.sdo"); +// synopsys translate_on + +wire \inst|44~0_combout ; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \INPUT_B4~combout ; +wire \isAdd~combout ; +wire \inst21|o4~2_combout ; +wire \INPUT_A3~combout ; +wire \INPUT_B3~combout ; +wire \inst|21~0_combout ; +wire \INPUT_B2~combout ; +wire \inst21|o2~2_combout ; +wire \INPUT_A2~combout ; +wire \inst|25~combout ; +wire \inst|1~0_combout ; +wire \inst|45~combout ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \inst1|16~regout ; +wire \INPUT_B1~combout ; +wire \INPUT_A1~combout ; +wire \inst|18~0_combout ; +wire \inst|43~combout ; +wire \inst1|8~regout ; +wire \inst|42~combout ; +wire \inst1|1~regout ; +wire \inst|44~combout ; +wire \inst1|15~regout ; +wire \inst17|a~12_combout ; +wire \inst20|o[3]~15_combout ; +wire \inst20|o[2]~16_combout ; +wire \inst20|o[1]~17_combout ; +wire \inst17|b~3_combout ; +wire \inst17|c~1_combout ; +wire \inst17|d~0_combout ; +wire \inst17|e~0_combout ; +wire \inst17|f~0_combout ; +wire \inst17|g~0_combout ; +wire \INPUT_A4~combout ; +wire \inst23|v~1_combout ; + + +// Location: LCCOMB_X43_Y26_N6 +cycloneii_lcell_comb \inst|44~0 ( +// Equation(s): +// \inst|44~0_combout = \INPUT_A3~combout $ (\INPUT_B3~combout $ (\isAdd~combout )) + + .dataa(vcc), + .datab(\INPUT_A3~combout ), + .datac(\INPUT_B3~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|44~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|44~0 .lut_mask = 16'hC33C; +defparam \inst|44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B4~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B4~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B4)); +// synopsys translate_off +defparam \INPUT_B4~I .input_async_reset = "none"; +defparam \INPUT_B4~I .input_power_up = "low"; +defparam \INPUT_B4~I .input_register_mode = "none"; +defparam \INPUT_B4~I .input_sync_reset = "none"; +defparam \INPUT_B4~I .oe_async_reset = "none"; +defparam \INPUT_B4~I .oe_power_up = "low"; +defparam \INPUT_B4~I .oe_register_mode = "none"; +defparam \INPUT_B4~I .oe_sync_reset = "none"; +defparam \INPUT_B4~I .operation_mode = "input"; +defparam \INPUT_B4~I .output_async_reset = "none"; +defparam \INPUT_B4~I .output_power_up = "low"; +defparam \INPUT_B4~I .output_register_mode = "none"; +defparam \INPUT_B4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B18, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \isAdd~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\isAdd~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(isAdd)); +// synopsys translate_off +defparam \isAdd~I .input_async_reset = "none"; +defparam \isAdd~I .input_power_up = "low"; +defparam \isAdd~I .input_register_mode = "none"; +defparam \isAdd~I .input_sync_reset = "none"; +defparam \isAdd~I .oe_async_reset = "none"; +defparam \isAdd~I .oe_power_up = "low"; +defparam \isAdd~I .oe_register_mode = "none"; +defparam \isAdd~I .oe_sync_reset = "none"; +defparam \isAdd~I .operation_mode = "input"; +defparam \isAdd~I .output_async_reset = "none"; +defparam \isAdd~I .output_power_up = "low"; +defparam \isAdd~I .output_register_mode = "none"; +defparam \isAdd~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N2 +cycloneii_lcell_comb \inst21|o4~2 ( +// Equation(s): +// \inst21|o4~2_combout = \INPUT_B4~combout $ (\isAdd~combout ) + + .dataa(vcc), + .datab(\INPUT_B4~combout ), + .datac(vcc), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst21|o4~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst21|o4~2 .lut_mask = 16'h33CC; +defparam \inst21|o4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_D16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A3~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A3~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A3)); +// synopsys translate_off +defparam \INPUT_A3~I .input_async_reset = "none"; +defparam \INPUT_A3~I .input_power_up = "low"; +defparam \INPUT_A3~I .input_register_mode = "none"; +defparam \INPUT_A3~I .input_sync_reset = "none"; +defparam \INPUT_A3~I .oe_async_reset = "none"; +defparam \INPUT_A3~I .oe_power_up = "low"; +defparam \INPUT_A3~I .oe_register_mode = "none"; +defparam \INPUT_A3~I .oe_sync_reset = "none"; +defparam \INPUT_A3~I .operation_mode = "input"; +defparam \INPUT_A3~I .output_async_reset = "none"; +defparam \INPUT_A3~I .output_power_up = "low"; +defparam \INPUT_A3~I .output_register_mode = "none"; +defparam \INPUT_A3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B3~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B3~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B3)); +// synopsys translate_off +defparam \INPUT_B3~I .input_async_reset = "none"; +defparam \INPUT_B3~I .input_power_up = "low"; +defparam \INPUT_B3~I .input_register_mode = "none"; +defparam \INPUT_B3~I .input_sync_reset = "none"; +defparam \INPUT_B3~I .oe_async_reset = "none"; +defparam \INPUT_B3~I .oe_power_up = "low"; +defparam \INPUT_B3~I .oe_register_mode = "none"; +defparam \INPUT_B3~I .oe_sync_reset = "none"; +defparam \INPUT_B3~I .operation_mode = "input"; +defparam \INPUT_B3~I .output_async_reset = "none"; +defparam \INPUT_B3~I .output_power_up = "low"; +defparam \INPUT_B3~I .output_register_mode = "none"; +defparam \INPUT_B3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N24 +cycloneii_lcell_comb \inst|21~0 ( +// Equation(s): +// \inst|21~0_combout = (!\INPUT_A3~combout & (\INPUT_B3~combout $ (\isAdd~combout ))) + + .dataa(vcc), + .datab(\INPUT_A3~combout ), + .datac(\INPUT_B3~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|21~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|21~0 .lut_mask = 16'h0330; +defparam \inst|21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_E15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B2~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B2~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B2)); +// synopsys translate_off +defparam \INPUT_B2~I .input_async_reset = "none"; +defparam \INPUT_B2~I .input_power_up = "low"; +defparam \INPUT_B2~I .input_register_mode = "none"; +defparam \INPUT_B2~I .input_sync_reset = "none"; +defparam \INPUT_B2~I .oe_async_reset = "none"; +defparam \INPUT_B2~I .oe_power_up = "low"; +defparam \INPUT_B2~I .oe_register_mode = "none"; +defparam \INPUT_B2~I .oe_sync_reset = "none"; +defparam \INPUT_B2~I .operation_mode = "input"; +defparam \INPUT_B2~I .output_async_reset = "none"; +defparam \INPUT_B2~I .output_power_up = "low"; +defparam \INPUT_B2~I .output_register_mode = "none"; +defparam \INPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N18 +cycloneii_lcell_comb \inst21|o2~2 ( +// Equation(s): +// \inst21|o2~2_combout = \INPUT_B2~combout $ (\isAdd~combout ) + + .dataa(vcc), + .datab(\INPUT_B2~combout ), + .datac(vcc), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst21|o2~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst21|o2~2 .lut_mask = 16'h33CC; +defparam \inst21|o2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A2~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A2~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A2)); +// synopsys translate_off +defparam \INPUT_A2~I .input_async_reset = "none"; +defparam \INPUT_A2~I .input_power_up = "low"; +defparam \INPUT_A2~I .input_register_mode = "none"; +defparam \INPUT_A2~I .input_sync_reset = "none"; +defparam \INPUT_A2~I .oe_async_reset = "none"; +defparam \INPUT_A2~I .oe_power_up = "low"; +defparam \INPUT_A2~I .oe_register_mode = "none"; +defparam \INPUT_A2~I .oe_sync_reset = "none"; +defparam \INPUT_A2~I .operation_mode = "input"; +defparam \INPUT_A2~I .output_async_reset = "none"; +defparam \INPUT_A2~I .output_power_up = "low"; +defparam \INPUT_A2~I .output_register_mode = "none"; +defparam \INPUT_A2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N30 +cycloneii_lcell_comb \inst|25 ( +// Equation(s): +// \inst|25~combout = (\INPUT_A3~combout & (\INPUT_B3~combout $ (!\isAdd~combout ))) + + .dataa(vcc), + .datab(\INPUT_A3~combout ), + .datac(\INPUT_B3~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|25~combout ), + .cout()); +// synopsys translate_off +defparam \inst|25 .lut_mask = 16'hC00C; +defparam \inst|25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N0 +cycloneii_lcell_comb \inst|1~0 ( +// Equation(s): +// \inst|1~0_combout = (!\inst|25~combout & ((\inst|18~0_combout & ((\inst21|o2~2_combout ) # (!\INPUT_A2~combout ))) # (!\inst|18~0_combout & (\inst21|o2~2_combout & !\INPUT_A2~combout )))) + + .dataa(\inst|18~0_combout ), + .datab(\inst21|o2~2_combout ), + .datac(\INPUT_A2~combout ), + .datad(\inst|25~combout ), + .cin(gnd), + .combout(\inst|1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|1~0 .lut_mask = 16'h008E; +defparam \inst|1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N10 +cycloneii_lcell_comb \inst|45 ( +// Equation(s): +// \inst|45~combout = \INPUT_A4~combout $ (\inst21|o4~2_combout $ (((\inst|21~0_combout ) # (\inst|1~0_combout )))) + + .dataa(\INPUT_A4~combout ), + .datab(\inst21|o4~2_combout ), + .datac(\inst|21~0_combout ), + .datad(\inst|1~0_combout ), + .cin(gnd), + .combout(\inst|45~combout ), + .cout()); +// synopsys translate_off +defparam \inst|45 .lut_mask = 16'h9996; +defparam \inst|45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \reset~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\reset~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(reset)); +// synopsys translate_off +defparam \reset~I .input_async_reset = "none"; +defparam \reset~I .input_power_up = "low"; +defparam \reset~I .input_register_mode = "none"; +defparam \reset~I .input_sync_reset = "none"; +defparam \reset~I .oe_async_reset = "none"; +defparam \reset~I .oe_power_up = "low"; +defparam \reset~I .oe_register_mode = "none"; +defparam \reset~I .oe_sync_reset = "none"; +defparam \reset~I .operation_mode = "input"; +defparam \reset~I .output_async_reset = "none"; +defparam \reset~I .output_power_up = "low"; +defparam \reset~I .output_register_mode = "none"; +defparam \reset~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneii_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N11 +cycloneii_lcell_ff \inst1|16 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|45~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|16~regout )); + +// Location: PIN_G16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B1~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B1~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B1)); +// synopsys translate_off +defparam \INPUT_B1~I .input_async_reset = "none"; +defparam \INPUT_B1~I .input_power_up = "low"; +defparam \INPUT_B1~I .input_register_mode = "none"; +defparam \INPUT_B1~I .input_sync_reset = "none"; +defparam \INPUT_B1~I .oe_async_reset = "none"; +defparam \INPUT_B1~I .oe_power_up = "low"; +defparam \INPUT_B1~I .oe_register_mode = "none"; +defparam \INPUT_B1~I .oe_sync_reset = "none"; +defparam \INPUT_B1~I .operation_mode = "input"; +defparam \INPUT_B1~I .output_async_reset = "none"; +defparam \INPUT_B1~I .output_power_up = "low"; +defparam \INPUT_B1~I .output_register_mode = "none"; +defparam \INPUT_B1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A1~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A1~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A1)); +// synopsys translate_off +defparam \INPUT_A1~I .input_async_reset = "none"; +defparam \INPUT_A1~I .input_power_up = "low"; +defparam \INPUT_A1~I .input_register_mode = "none"; +defparam \INPUT_A1~I .input_sync_reset = "none"; +defparam \INPUT_A1~I .oe_async_reset = "none"; +defparam \INPUT_A1~I .oe_power_up = "low"; +defparam \INPUT_A1~I .oe_register_mode = "none"; +defparam \INPUT_A1~I .oe_sync_reset = "none"; +defparam \INPUT_A1~I .operation_mode = "input"; +defparam \INPUT_A1~I .output_async_reset = "none"; +defparam \INPUT_A1~I .output_power_up = "low"; +defparam \INPUT_A1~I .output_register_mode = "none"; +defparam \INPUT_A1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N28 +cycloneii_lcell_comb \inst|18~0 ( +// Equation(s): +// \inst|18~0_combout = (\INPUT_B1~combout & (!\INPUT_A1~combout )) # (!\INPUT_B1~combout & ((\isAdd~combout ))) + + .dataa(vcc), + .datab(\INPUT_B1~combout ), + .datac(\INPUT_A1~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|18~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|18~0 .lut_mask = 16'h3F0C; +defparam \inst|18~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N22 +cycloneii_lcell_comb \inst|43 ( +// Equation(s): +// \inst|43~combout = \INPUT_B2~combout $ (\inst|18~0_combout $ (\INPUT_A2~combout $ (\isAdd~combout ))) + + .dataa(\INPUT_B2~combout ), + .datab(\inst|18~0_combout ), + .datac(\INPUT_A2~combout ), + .datad(\isAdd~combout ), + .cin(gnd), + .combout(\inst|43~combout ), + .cout()); +// synopsys translate_off +defparam \inst|43 .lut_mask = 16'h6996; +defparam \inst|43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N23 +cycloneii_lcell_ff \inst1|8 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|43~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|8~regout )); + +// Location: LCCOMB_X43_Y26_N12 +cycloneii_lcell_comb \inst|42 ( +// Equation(s): +// \inst|42~combout = \INPUT_A1~combout $ (\INPUT_B1~combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\INPUT_A1~combout ), + .datad(\INPUT_B1~combout ), + .cin(gnd), + .combout(\inst|42~combout ), + .cout()); +// synopsys translate_off +defparam \inst|42 .lut_mask = 16'h0FF0; +defparam \inst|42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N13 +cycloneii_lcell_ff \inst1|1 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|42~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|1~regout )); + +// Location: LCCOMB_X43_Y26_N8 +cycloneii_lcell_comb \inst|44 ( +// Equation(s): +// \inst|44~combout = \inst|44~0_combout $ (((\inst|18~0_combout & ((\inst21|o2~2_combout ) # (!\INPUT_A2~combout ))) # (!\inst|18~0_combout & (!\INPUT_A2~combout & \inst21|o2~2_combout )))) + + .dataa(\inst|44~0_combout ), + .datab(\inst|18~0_combout ), + .datac(\INPUT_A2~combout ), + .datad(\inst21|o2~2_combout ), + .cin(gnd), + .combout(\inst|44~combout ), + .cout()); +// synopsys translate_off +defparam \inst|44 .lut_mask = 16'h65A6; +defparam \inst|44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N9 +cycloneii_lcell_ff \inst1|15 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|44~combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|15~regout )); + +// Location: LCCOMB_X39_Y26_N8 +cycloneii_lcell_comb \inst17|a~12 ( +// Equation(s): +// \inst17|a~12_combout = (\inst1|16~regout & (\inst1|15~regout & (\inst1|8~regout $ (!\inst1|1~regout )))) # (!\inst1|16~regout & (!\inst1|8~regout & (\inst1|1~regout $ (\inst1|15~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|a~12 .lut_mask = 16'h8310; +defparam \inst17|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N18 +cycloneii_lcell_comb \inst20|o[3]~15 ( +// Equation(s): +// \inst20|o[3]~15_combout = (\inst1|16~regout & (!\inst1|8~regout & (!\inst1|1~regout & !\inst1|15~regout ))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst20|o[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \inst20|o[3]~15 .lut_mask = 16'h0002; +defparam \inst20|o[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N12 +cycloneii_lcell_comb \inst20|o[2]~16 ( +// Equation(s): +// \inst20|o[2]~16_combout = \inst1|15~regout $ (((\inst1|16~regout & ((\inst1|8~regout ) # (\inst1|1~regout ))))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst20|o[2]~16_combout ), + .cout()); +// synopsys translate_off +defparam \inst20|o[2]~16 .lut_mask = 16'h57A8; +defparam \inst20|o[2]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N22 +cycloneii_lcell_comb \inst20|o[1]~17 ( +// Equation(s): +// \inst20|o[1]~17_combout = \inst1|8~regout $ (((\inst1|16~regout & \inst1|1~regout ))) + + .dataa(\inst1|16~regout ), + .datab(vcc), + .datac(\inst1|1~regout ), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst20|o[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \inst20|o[1]~17 .lut_mask = 16'h5FA0; +defparam \inst20|o[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N0 +cycloneii_lcell_comb \inst17|b~3 ( +// Equation(s): +// \inst17|b~3_combout = (\inst1|16~regout & (\inst1|8~regout & ((!\inst1|15~regout )))) # (!\inst1|16~regout & (\inst1|15~regout & (\inst1|8~regout $ (\inst1|1~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|b~3 .lut_mask = 16'h1488; +defparam \inst17|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N10 +cycloneii_lcell_comb \inst17|c~1 ( +// Equation(s): +// \inst17|c~1_combout = (\inst1|8~regout & (!\inst1|1~regout & (\inst1|16~regout $ (!\inst1|15~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|c~1 .lut_mask = 16'h0804; +defparam \inst17|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N20 +cycloneii_lcell_comb \inst17|d~0 ( +// Equation(s): +// \inst17|d~0_combout = (\inst1|8~regout & (\inst1|1~regout & \inst1|15~regout )) # (!\inst1|8~regout & (\inst1|1~regout $ (\inst1|15~regout ))) + + .dataa(vcc), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|d~0 .lut_mask = 16'hC330; +defparam \inst17|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N30 +cycloneii_lcell_comb \inst17|e~0 ( +// Equation(s): +// \inst17|e~0_combout = (\inst1|1~regout ) # ((!\inst1|8~regout & \inst1|15~regout )) + + .dataa(vcc), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|e~0 .lut_mask = 16'hF3F0; +defparam \inst17|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N24 +cycloneii_lcell_comb \inst17|f~0 ( +// Equation(s): +// \inst17|f~0_combout = (\inst1|8~regout & ((\inst1|16~regout & ((\inst1|15~regout ))) # (!\inst1|16~regout & ((\inst1|1~regout ) # (!\inst1|15~regout ))))) # (!\inst1|8~regout & (\inst1|1~regout & ((\inst1|16~regout ) # (!\inst1|15~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|f~0 .lut_mask = 16'hE874; +defparam \inst17|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y26_N2 +cycloneii_lcell_comb \inst17|g~0 ( +// Equation(s): +// \inst17|g~0_combout = (\inst1|8~regout & (((!\inst1|15~regout ) # (!\inst1|1~regout )))) # (!\inst1|8~regout & ((\inst1|15~regout ) # ((\inst1|16~regout & !\inst1|1~regout )))) + + .dataa(\inst1|16~regout ), + .datab(\inst1|8~regout ), + .datac(\inst1|1~regout ), + .datad(\inst1|15~regout ), + .cin(gnd), + .combout(\inst17|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|g~0 .lut_mask = 16'h3FCE; +defparam \inst17|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_D20, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A4~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A4~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A4)); +// synopsys translate_off +defparam \INPUT_A4~I .input_async_reset = "none"; +defparam \INPUT_A4~I .input_power_up = "low"; +defparam \INPUT_A4~I .input_register_mode = "none"; +defparam \INPUT_A4~I .input_sync_reset = "none"; +defparam \INPUT_A4~I .oe_async_reset = "none"; +defparam \INPUT_A4~I .oe_power_up = "low"; +defparam \INPUT_A4~I .oe_register_mode = "none"; +defparam \INPUT_A4~I .oe_sync_reset = "none"; +defparam \INPUT_A4~I .operation_mode = "input"; +defparam \INPUT_A4~I .output_async_reset = "none"; +defparam \INPUT_A4~I .output_power_up = "low"; +defparam \INPUT_A4~I .output_register_mode = "none"; +defparam \INPUT_A4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N20 +cycloneii_lcell_comb \inst23|v~1 ( +// Equation(s): +// \inst23|v~1_combout = (\INPUT_A4~combout & (!\inst21|o4~2_combout & ((\inst|21~0_combout ) # (\inst|1~0_combout )))) # (!\INPUT_A4~combout & (\inst21|o4~2_combout & (!\inst|21~0_combout & !\inst|1~0_combout ))) + + .dataa(\INPUT_A4~combout ), + .datab(\inst21|o4~2_combout ), + .datac(\inst|21~0_combout ), + .datad(\inst|1~0_combout ), + .cin(gnd), + .combout(\inst23|v~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst23|v~1 .lut_mask = 16'h2224; +defparam \inst23|v~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_A17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A~I ( + .datain(\inst17|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A)); +// synopsys translate_off +defparam \OUTPUT_A~I .input_async_reset = "none"; +defparam \OUTPUT_A~I .input_power_up = "low"; +defparam \OUTPUT_A~I .input_register_mode = "none"; +defparam \OUTPUT_A~I .input_sync_reset = "none"; +defparam \OUTPUT_A~I .oe_async_reset = "none"; +defparam \OUTPUT_A~I .oe_power_up = "low"; +defparam \OUTPUT_A~I .oe_register_mode = "none"; +defparam \OUTPUT_A~I .oe_sync_reset = "none"; +defparam \OUTPUT_A~I .operation_mode = "output"; +defparam \OUTPUT_A~I .output_async_reset = "none"; +defparam \OUTPUT_A~I .output_power_up = "low"; +defparam \OUTPUT_A~I .output_register_mode = "none"; +defparam \OUTPUT_A~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[3]~I ( + .datain(\inst20|o[3]~15_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[3])); +// synopsys translate_off +defparam \i[3]~I .input_async_reset = "none"; +defparam \i[3]~I .input_power_up = "low"; +defparam \i[3]~I .input_register_mode = "none"; +defparam \i[3]~I .input_sync_reset = "none"; +defparam \i[3]~I .oe_async_reset = "none"; +defparam \i[3]~I .oe_power_up = "low"; +defparam \i[3]~I .oe_register_mode = "none"; +defparam \i[3]~I .oe_sync_reset = "none"; +defparam \i[3]~I .operation_mode = "output"; +defparam \i[3]~I .output_async_reset = "none"; +defparam \i[3]~I .output_power_up = "low"; +defparam \i[3]~I .output_register_mode = "none"; +defparam \i[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_G15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[2]~I ( + .datain(\inst20|o[2]~16_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[2])); +// synopsys translate_off +defparam \i[2]~I .input_async_reset = "none"; +defparam \i[2]~I .input_power_up = "low"; +defparam \i[2]~I .input_register_mode = "none"; +defparam \i[2]~I .input_sync_reset = "none"; +defparam \i[2]~I .oe_async_reset = "none"; +defparam \i[2]~I .oe_power_up = "low"; +defparam \i[2]~I .oe_register_mode = "none"; +defparam \i[2]~I .oe_sync_reset = "none"; +defparam \i[2]~I .operation_mode = "output"; +defparam \i[2]~I .output_async_reset = "none"; +defparam \i[2]~I .output_power_up = "low"; +defparam \i[2]~I .output_register_mode = "none"; +defparam \i[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[1]~I ( + .datain(\inst20|o[1]~17_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[1])); +// synopsys translate_off +defparam \i[1]~I .input_async_reset = "none"; +defparam \i[1]~I .input_power_up = "low"; +defparam \i[1]~I .input_register_mode = "none"; +defparam \i[1]~I .input_sync_reset = "none"; +defparam \i[1]~I .oe_async_reset = "none"; +defparam \i[1]~I .oe_power_up = "low"; +defparam \i[1]~I .oe_register_mode = "none"; +defparam \i[1]~I .oe_sync_reset = "none"; +defparam \i[1]~I .operation_mode = "output"; +defparam \i[1]~I .output_async_reset = "none"; +defparam \i[1]~I .output_power_up = "low"; +defparam \i[1]~I .output_register_mode = "none"; +defparam \i[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \i[0]~I ( + .datain(\inst1|1~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(i[0])); +// synopsys translate_off +defparam \i[0]~I .input_async_reset = "none"; +defparam \i[0]~I .input_power_up = "low"; +defparam \i[0]~I .input_register_mode = "none"; +defparam \i[0]~I .input_sync_reset = "none"; +defparam \i[0]~I .oe_async_reset = "none"; +defparam \i[0]~I .oe_power_up = "low"; +defparam \i[0]~I .oe_register_mode = "none"; +defparam \i[0]~I .oe_sync_reset = "none"; +defparam \i[0]~I .operation_mode = "output"; +defparam \i[0]~I .output_async_reset = "none"; +defparam \i[0]~I .output_power_up = "low"; +defparam \i[0]~I .output_register_mode = "none"; +defparam \i[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B~I ( + .datain(\inst17|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B)); +// synopsys translate_off +defparam \OUTPUT_B~I .input_async_reset = "none"; +defparam \OUTPUT_B~I .input_power_up = "low"; +defparam \OUTPUT_B~I .input_register_mode = "none"; +defparam \OUTPUT_B~I .input_sync_reset = "none"; +defparam \OUTPUT_B~I .oe_async_reset = "none"; +defparam \OUTPUT_B~I .oe_power_up = "low"; +defparam \OUTPUT_B~I .oe_register_mode = "none"; +defparam \OUTPUT_B~I .oe_sync_reset = "none"; +defparam \OUTPUT_B~I .operation_mode = "output"; +defparam \OUTPUT_B~I .output_async_reset = "none"; +defparam \OUTPUT_B~I .output_power_up = "low"; +defparam \OUTPUT_B~I .output_register_mode = "none"; +defparam \OUTPUT_B~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C~I ( + .datain(\inst17|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C)); +// synopsys translate_off +defparam \OUTPUT_C~I .input_async_reset = "none"; +defparam \OUTPUT_C~I .input_power_up = "low"; +defparam \OUTPUT_C~I .input_register_mode = "none"; +defparam \OUTPUT_C~I .input_sync_reset = "none"; +defparam \OUTPUT_C~I .oe_async_reset = "none"; +defparam \OUTPUT_C~I .oe_power_up = "low"; +defparam \OUTPUT_C~I .oe_register_mode = "none"; +defparam \OUTPUT_C~I .oe_sync_reset = "none"; +defparam \OUTPUT_C~I .operation_mode = "output"; +defparam \OUTPUT_C~I .output_async_reset = "none"; +defparam \OUTPUT_C~I .output_power_up = "low"; +defparam \OUTPUT_C~I .output_register_mode = "none"; +defparam \OUTPUT_C~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D~I ( + .datain(\inst17|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D)); +// synopsys translate_off +defparam \OUTPUT_D~I .input_async_reset = "none"; +defparam \OUTPUT_D~I .input_power_up = "low"; +defparam \OUTPUT_D~I .input_register_mode = "none"; +defparam \OUTPUT_D~I .input_sync_reset = "none"; +defparam \OUTPUT_D~I .oe_async_reset = "none"; +defparam \OUTPUT_D~I .oe_power_up = "low"; +defparam \OUTPUT_D~I .oe_register_mode = "none"; +defparam \OUTPUT_D~I .oe_sync_reset = "none"; +defparam \OUTPUT_D~I .operation_mode = "output"; +defparam \OUTPUT_D~I .output_async_reset = "none"; +defparam \OUTPUT_D~I .output_power_up = "low"; +defparam \OUTPUT_D~I .output_register_mode = "none"; +defparam \OUTPUT_D~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E~I ( + .datain(\inst17|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E)); +// synopsys translate_off +defparam \OUTPUT_E~I .input_async_reset = "none"; +defparam \OUTPUT_E~I .input_power_up = "low"; +defparam \OUTPUT_E~I .input_register_mode = "none"; +defparam \OUTPUT_E~I .input_sync_reset = "none"; +defparam \OUTPUT_E~I .oe_async_reset = "none"; +defparam \OUTPUT_E~I .oe_power_up = "low"; +defparam \OUTPUT_E~I .oe_register_mode = "none"; +defparam \OUTPUT_E~I .oe_sync_reset = "none"; +defparam \OUTPUT_E~I .operation_mode = "output"; +defparam \OUTPUT_E~I .output_async_reset = "none"; +defparam \OUTPUT_E~I .output_power_up = "low"; +defparam \OUTPUT_E~I .output_register_mode = "none"; +defparam \OUTPUT_E~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F~I ( + .datain(\inst17|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F)); +// synopsys translate_off +defparam \OUTPUT_F~I .input_async_reset = "none"; +defparam \OUTPUT_F~I .input_power_up = "low"; +defparam \OUTPUT_F~I .input_register_mode = "none"; +defparam \OUTPUT_F~I .input_sync_reset = "none"; +defparam \OUTPUT_F~I .oe_async_reset = "none"; +defparam \OUTPUT_F~I .oe_power_up = "low"; +defparam \OUTPUT_F~I .oe_register_mode = "none"; +defparam \OUTPUT_F~I .oe_sync_reset = "none"; +defparam \OUTPUT_F~I .operation_mode = "output"; +defparam \OUTPUT_F~I .output_async_reset = "none"; +defparam \OUTPUT_F~I .output_power_up = "low"; +defparam \OUTPUT_F~I .output_register_mode = "none"; +defparam \OUTPUT_F~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G~I ( + .datain(!\inst17|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G)); +// synopsys translate_off +defparam \OUTPUT_G~I .input_async_reset = "none"; +defparam \OUTPUT_G~I .input_power_up = "low"; +defparam \OUTPUT_G~I .input_register_mode = "none"; +defparam \OUTPUT_G~I .input_sync_reset = "none"; +defparam \OUTPUT_G~I .oe_async_reset = "none"; +defparam \OUTPUT_G~I .oe_power_up = "low"; +defparam \OUTPUT_G~I .oe_register_mode = "none"; +defparam \OUTPUT_G~I .oe_sync_reset = "none"; +defparam \OUTPUT_G~I .operation_mode = "output"; +defparam \OUTPUT_G~I .output_async_reset = "none"; +defparam \OUTPUT_G~I .output_power_up = "low"; +defparam \OUTPUT_G~I .output_register_mode = "none"; +defparam \OUTPUT_G~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A2)); +// synopsys translate_off +defparam \OUTPUT_A2~I .input_async_reset = "none"; +defparam \OUTPUT_A2~I .input_power_up = "low"; +defparam \OUTPUT_A2~I .input_register_mode = "none"; +defparam \OUTPUT_A2~I .input_sync_reset = "none"; +defparam \OUTPUT_A2~I .oe_async_reset = "none"; +defparam \OUTPUT_A2~I .oe_power_up = "low"; +defparam \OUTPUT_A2~I .oe_register_mode = "none"; +defparam \OUTPUT_A2~I .oe_sync_reset = "none"; +defparam \OUTPUT_A2~I .operation_mode = "output"; +defparam \OUTPUT_A2~I .output_async_reset = "none"; +defparam \OUTPUT_A2~I .output_power_up = "low"; +defparam \OUTPUT_A2~I .output_register_mode = "none"; +defparam \OUTPUT_A2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B2)); +// synopsys translate_off +defparam \OUTPUT_B2~I .input_async_reset = "none"; +defparam \OUTPUT_B2~I .input_power_up = "low"; +defparam \OUTPUT_B2~I .input_register_mode = "none"; +defparam \OUTPUT_B2~I .input_sync_reset = "none"; +defparam \OUTPUT_B2~I .oe_async_reset = "none"; +defparam \OUTPUT_B2~I .oe_power_up = "low"; +defparam \OUTPUT_B2~I .oe_register_mode = "none"; +defparam \OUTPUT_B2~I .oe_sync_reset = "none"; +defparam \OUTPUT_B2~I .operation_mode = "output"; +defparam \OUTPUT_B2~I .output_async_reset = "none"; +defparam \OUTPUT_B2~I .output_power_up = "low"; +defparam \OUTPUT_B2~I .output_register_mode = "none"; +defparam \OUTPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C2)); +// synopsys translate_off +defparam \OUTPUT_C2~I .input_async_reset = "none"; +defparam \OUTPUT_C2~I .input_power_up = "low"; +defparam \OUTPUT_C2~I .input_register_mode = "none"; +defparam \OUTPUT_C2~I .input_sync_reset = "none"; +defparam \OUTPUT_C2~I .oe_async_reset = "none"; +defparam \OUTPUT_C2~I .oe_power_up = "low"; +defparam \OUTPUT_C2~I .oe_register_mode = "none"; +defparam \OUTPUT_C2~I .oe_sync_reset = "none"; +defparam \OUTPUT_C2~I .operation_mode = "output"; +defparam \OUTPUT_C2~I .output_async_reset = "none"; +defparam \OUTPUT_C2~I .output_power_up = "low"; +defparam \OUTPUT_C2~I .output_register_mode = "none"; +defparam \OUTPUT_C2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D2)); +// synopsys translate_off +defparam \OUTPUT_D2~I .input_async_reset = "none"; +defparam \OUTPUT_D2~I .input_power_up = "low"; +defparam \OUTPUT_D2~I .input_register_mode = "none"; +defparam \OUTPUT_D2~I .input_sync_reset = "none"; +defparam \OUTPUT_D2~I .oe_async_reset = "none"; +defparam \OUTPUT_D2~I .oe_power_up = "low"; +defparam \OUTPUT_D2~I .oe_register_mode = "none"; +defparam \OUTPUT_D2~I .oe_sync_reset = "none"; +defparam \OUTPUT_D2~I .operation_mode = "output"; +defparam \OUTPUT_D2~I .output_async_reset = "none"; +defparam \OUTPUT_D2~I .output_power_up = "low"; +defparam \OUTPUT_D2~I .output_register_mode = "none"; +defparam \OUTPUT_D2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E2)); +// synopsys translate_off +defparam \OUTPUT_E2~I .input_async_reset = "none"; +defparam \OUTPUT_E2~I .input_power_up = "low"; +defparam \OUTPUT_E2~I .input_register_mode = "none"; +defparam \OUTPUT_E2~I .input_sync_reset = "none"; +defparam \OUTPUT_E2~I .oe_async_reset = "none"; +defparam \OUTPUT_E2~I .oe_power_up = "low"; +defparam \OUTPUT_E2~I .oe_register_mode = "none"; +defparam \OUTPUT_E2~I .oe_sync_reset = "none"; +defparam \OUTPUT_E2~I .operation_mode = "output"; +defparam \OUTPUT_E2~I .output_async_reset = "none"; +defparam \OUTPUT_E2~I .output_power_up = "low"; +defparam \OUTPUT_E2~I .output_register_mode = "none"; +defparam \OUTPUT_E2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F2)); +// synopsys translate_off +defparam \OUTPUT_F2~I .input_async_reset = "none"; +defparam \OUTPUT_F2~I .input_power_up = "low"; +defparam \OUTPUT_F2~I .input_register_mode = "none"; +defparam \OUTPUT_F2~I .input_sync_reset = "none"; +defparam \OUTPUT_F2~I .oe_async_reset = "none"; +defparam \OUTPUT_F2~I .oe_power_up = "low"; +defparam \OUTPUT_F2~I .oe_register_mode = "none"; +defparam \OUTPUT_F2~I .oe_sync_reset = "none"; +defparam \OUTPUT_F2~I .operation_mode = "output"; +defparam \OUTPUT_F2~I .output_async_reset = "none"; +defparam \OUTPUT_F2~I .output_power_up = "low"; +defparam \OUTPUT_F2~I .output_register_mode = "none"; +defparam \OUTPUT_F2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_F15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G2~I ( + .datain(\inst1|16~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G2)); +// synopsys translate_off +defparam \OUTPUT_G2~I .input_async_reset = "none"; +defparam \OUTPUT_G2~I .input_power_up = "low"; +defparam \OUTPUT_G2~I .input_register_mode = "none"; +defparam \OUTPUT_G2~I .input_sync_reset = "none"; +defparam \OUTPUT_G2~I .oe_async_reset = "none"; +defparam \OUTPUT_G2~I .oe_power_up = "low"; +defparam \OUTPUT_G2~I .oe_register_mode = "none"; +defparam \OUTPUT_G2~I .oe_sync_reset = "none"; +defparam \OUTPUT_G2~I .operation_mode = "output"; +defparam \OUTPUT_G2~I .output_async_reset = "none"; +defparam \OUTPUT_G2~I .output_power_up = "low"; +defparam \OUTPUT_G2~I .output_register_mode = "none"; +defparam \OUTPUT_G2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \overflow~I ( + .datain(\inst23|v~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(overflow)); +// synopsys translate_off +defparam \overflow~I .input_async_reset = "none"; +defparam \overflow~I .input_power_up = "low"; +defparam \overflow~I .input_register_mode = "none"; +defparam \overflow~I .input_sync_reset = "none"; +defparam \overflow~I .oe_async_reset = "none"; +defparam \overflow~I .oe_power_up = "low"; +defparam \overflow~I .oe_register_mode = "none"; +defparam \overflow~I .oe_sync_reset = "none"; +defparam \overflow~I .operation_mode = "output"; +defparam \overflow~I .output_async_reset = "none"; +defparam \overflow~I .output_power_up = "low"; +defparam \overflow~I .output_register_mode = "none"; +defparam \overflow~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \pin_name1~I ( + .datain(\inst1|1~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(pin_name1)); +// synopsys translate_off +defparam \pin_name1~I .input_async_reset = "none"; +defparam \pin_name1~I .input_power_up = "low"; +defparam \pin_name1~I .input_register_mode = "none"; +defparam \pin_name1~I .input_sync_reset = "none"; +defparam \pin_name1~I .oe_async_reset = "none"; +defparam \pin_name1~I .oe_power_up = "low"; +defparam \pin_name1~I .oe_register_mode = "none"; +defparam \pin_name1~I .oe_sync_reset = "none"; +defparam \pin_name1~I .operation_mode = "output"; +defparam \pin_name1~I .output_async_reset = "none"; +defparam \pin_name1~I .output_power_up = "low"; +defparam \pin_name1~I .output_register_mode = "none"; +defparam \pin_name1~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/YL_adder/simulation/modelsim/YL_adder_modelsim.xrf b/YL_adder/simulation/modelsim/YL_adder_modelsim.xrf new file mode 100644 index 0000000..39fad90 --- /dev/null +++ b/YL_adder/simulation/modelsim/YL_adder_modelsim.xrf @@ -0,0 +1,75 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adder.bdf +source_file = 1, YL_7segment.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7segment_sign.tdf +source_file = 1, YL_7segment_sign.tdf +source_file = 1, YL_sign_to_unsign.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/operator.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/overflow.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adde.vwf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/db/YL_adder.cbx.xml +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/segment.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/encoder.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/others/maxplus2/74171.bdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/others/maxplus2/7483.bdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/sign.tdf +design_name = YL_adder +instance = comp, \inst|44~0 , inst|44~0, YL_adder, 1 +instance = comp, \clk~I , clk, YL_adder, 1 +instance = comp, \clk~clkctrl , clk~clkctrl, YL_adder, 1 +instance = comp, \INPUT_B4~I , INPUT_B4, YL_adder, 1 +instance = comp, \isAdd~I , isAdd, YL_adder, 1 +instance = comp, \inst21|o4~2 , inst21|o4~2, YL_adder, 1 +instance = comp, \INPUT_A3~I , INPUT_A3, YL_adder, 1 +instance = comp, \INPUT_B3~I , INPUT_B3, YL_adder, 1 +instance = comp, \inst|21~0 , inst|21~0, YL_adder, 1 +instance = comp, \INPUT_B2~I , INPUT_B2, YL_adder, 1 +instance = comp, \inst21|o2~2 , inst21|o2~2, YL_adder, 1 +instance = comp, \INPUT_A2~I , INPUT_A2, YL_adder, 1 +instance = comp, \inst|25 , inst|25, YL_adder, 1 +instance = comp, \inst|1~0 , inst|1~0, YL_adder, 1 +instance = comp, \inst|45 , inst|45, YL_adder, 1 +instance = comp, \reset~I , reset, YL_adder, 1 +instance = comp, \reset~clkctrl , reset~clkctrl, YL_adder, 1 +instance = comp, \inst1|16 , inst1|16, YL_adder, 1 +instance = comp, \INPUT_B1~I , INPUT_B1, YL_adder, 1 +instance = comp, \INPUT_A1~I , INPUT_A1, YL_adder, 1 +instance = comp, \inst|18~0 , inst|18~0, YL_adder, 1 +instance = comp, \inst|43 , inst|43, YL_adder, 1 +instance = comp, \inst1|8 , inst1|8, YL_adder, 1 +instance = comp, \inst|42 , inst|42, YL_adder, 1 +instance = comp, \inst1|1 , inst1|1, YL_adder, 1 +instance = comp, \inst|44 , inst|44, YL_adder, 1 +instance = comp, \inst1|15 , inst1|15, YL_adder, 1 +instance = comp, \inst17|a~12 , inst17|a~12, YL_adder, 1 +instance = comp, \inst20|o[3]~15 , inst20|o[3]~15, YL_adder, 1 +instance = comp, \inst20|o[2]~16 , inst20|o[2]~16, YL_adder, 1 +instance = comp, \inst20|o[1]~17 , inst20|o[1]~17, YL_adder, 1 +instance = comp, \inst17|b~3 , inst17|b~3, YL_adder, 1 +instance = comp, \inst17|c~1 , inst17|c~1, YL_adder, 1 +instance = comp, \inst17|d~0 , inst17|d~0, YL_adder, 1 +instance = comp, \inst17|e~0 , inst17|e~0, YL_adder, 1 +instance = comp, \inst17|f~0 , inst17|f~0, YL_adder, 1 +instance = comp, \inst17|g~0 , inst17|g~0, YL_adder, 1 +instance = comp, \INPUT_A4~I , INPUT_A4, YL_adder, 1 +instance = comp, \inst23|v~1 , inst23|v~1, YL_adder, 1 +instance = comp, \OUTPUT_A~I , OUTPUT_A, YL_adder, 1 +instance = comp, \i[3]~I , i[3], YL_adder, 1 +instance = comp, \i[2]~I , i[2], YL_adder, 1 +instance = comp, \i[1]~I , i[1], YL_adder, 1 +instance = comp, \i[0]~I , i[0], YL_adder, 1 +instance = comp, \OUTPUT_B~I , OUTPUT_B, YL_adder, 1 +instance = comp, \OUTPUT_C~I , OUTPUT_C, YL_adder, 1 +instance = comp, \OUTPUT_D~I , OUTPUT_D, YL_adder, 1 +instance = comp, \OUTPUT_E~I , OUTPUT_E, YL_adder, 1 +instance = comp, \OUTPUT_F~I , OUTPUT_F, YL_adder, 1 +instance = comp, \OUTPUT_G~I , OUTPUT_G, YL_adder, 1 +instance = comp, \OUTPUT_A2~I , OUTPUT_A2, YL_adder, 1 +instance = comp, \OUTPUT_B2~I , OUTPUT_B2, YL_adder, 1 +instance = comp, \OUTPUT_C2~I , OUTPUT_C2, YL_adder, 1 +instance = comp, \OUTPUT_D2~I , OUTPUT_D2, YL_adder, 1 +instance = comp, \OUTPUT_E2~I , OUTPUT_E2, YL_adder, 1 +instance = comp, \OUTPUT_F2~I , OUTPUT_F2, YL_adder, 1 +instance = comp, \OUTPUT_G2~I , OUTPUT_G2, YL_adder, 1 +instance = comp, \overflow~I , overflow, YL_adder, 1 +instance = comp, \pin_name1~I , pin_name1, YL_adder, 1 diff --git a/YL_adder/simulation/modelsim/YL_adder_v.sdo b/YL_adder/simulation/modelsim/YL_adder_v.sdo new file mode 100644 index 0000000..9742eca --- /dev/null +++ b/YL_adder/simulation/modelsim/YL_adder_v.sdo @@ -0,0 +1,765 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "YL_adder") + (DATE "05/04/2020 17:05:47") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|44\~0) + (DELAY + (ABSOLUTE + (PORT datab (5238:5238:5238) (5238:5238:5238)) + (PORT datac (5819:5819:5819) (5819:5819:5819)) + (PORT datad (5583:5583:5583) (5583:5583:5583)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE clk\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE clk\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (238:238:238) (238:238:238)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE clk\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (279:279:279) (279:279:279)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (239:239:239) (239:239:239)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (55:55:55)) + (HOLD d (posedge clk) (110:110:110)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE isAdd\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (873:873:873) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst21\|o4\~2) + (DELAY + (ABSOLUTE + (PORT datab (2272:2272:2272) (2272:2272:2272)) + (PORT datad (5583:5583:5583) (5583:5583:5583)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (843:843:843) (843:843:843)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (843:843:843) (843:843:843)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|21\~0) + (DELAY + (ABSOLUTE + (PORT datab (5240:5240:5240) (5240:5240:5240)) + (PORT datac (5822:5822:5822) (5822:5822:5822)) + (PORT datad (5578:5578:5578) (5578:5578:5578)) + (IOPATH datab combout (461:461:461) (461:461:461)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (843:843:843) (843:843:843)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst21\|o2\~2) + (DELAY + (ABSOLUTE + (PORT datab (5227:5227:5227) (5227:5227:5227)) + (PORT datad (5577:5577:5577) (5577:5577:5577)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|25) + (DELAY + (ABSOLUTE + (PORT datab (5240:5240:5240) (5240:5240:5240)) + (PORT datac (5819:5819:5819) (5819:5819:5819)) + (PORT datad (5580:5580:5580) (5580:5580:5580)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (553:553:553)) + (PORT datab (310:310:310) (310:310:310)) + (PORT datac (2335:2335:2335) (2335:2335:2335)) + (PORT datad (295:295:295) (295:295:295)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|45) + (DELAY + (ABSOLUTE + (PORT dataa (5406:5406:5406) (5406:5406:5406)) + (PORT datab (307:307:307) (307:307:307)) + (PORT datac (302:302:302) (302:302:302)) + (PORT datad (323:323:323) (323:323:323)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE reset\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (232:232:232) (232:232:232)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE reset\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (279:279:279) (279:279:279)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (239:239:239) (239:239:239)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (55:55:55)) + (HOLD d (posedge clk) (110:110:110)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|16) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (863:863:863) (863:863:863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (853:853:853) (853:853:853)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|18\~0) + (DELAY + (ABSOLUTE + (PORT datab (5246:5246:5246) (5246:5246:5246)) + (PORT datac (5208:5208:5208) (5208:5208:5208)) + (PORT datad (5581:5581:5581) (5581:5581:5581)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|43) + (DELAY + (ABSOLUTE + (PORT dataa (5253:5253:5253) (5253:5253:5253)) + (PORT datab (309:309:309) (309:309:309)) + (PORT datac (2329:2329:2329) (2329:2329:2329)) + (PORT datad (5577:5577:5577) (5577:5577:5577)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|8) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|42) + (DELAY + (ABSOLUTE + (PORT datac (5209:5209:5209) (5209:5209:5209)) + (PORT datad (5245:5245:5245) (5245:5245:5245)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|1) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|44) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (308:308:308)) + (PORT datab (311:311:311) (311:311:311)) + (PORT datac (2334:2334:2334) (2334:2334:2334)) + (PORT datad (305:305:305) (305:305:305)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|15) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1263:1263:1263)) + (PORT datab (991:991:991) (991:991:991)) + (PORT datac (980:980:980) (980:980:980)) + (PORT datad (964:964:964) (964:964:964)) + (IOPATH dataa combout (512:512:512) (512:512:512)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst20\|o\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1267:1267:1267)) + (PORT datab (981:981:981) (981:981:981)) + (PORT datac (989:989:989) (989:989:989)) + (PORT datad (970:970:970) (970:970:970)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (458:458:458) (458:458:458)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst20\|o\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1265:1265:1265)) + (PORT datab (988:988:988) (988:988:988)) + (PORT datac (983:983:983) (983:983:983)) + (PORT datad (967:967:967) (967:967:967)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst20\|o\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1267:1267:1267)) + (PORT datac (988:988:988) (988:988:988)) + (PORT datad (977:977:977) (977:977:977)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1263:1263:1263)) + (PORT datab (990:990:990) (990:990:990)) + (PORT datac (980:980:980) (980:980:980)) + (PORT datad (963:963:963) (963:963:963)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1264:1264:1264)) + (PORT datab (991:991:991) (991:991:991)) + (PORT datac (981:981:981) (981:981:981)) + (PORT datad (966:966:966) (966:966:966)) + (IOPATH dataa combout (505:505:505) (505:505:505)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|d\~0) + (DELAY + (ABSOLUTE + (PORT datab (980:980:980) (980:980:980)) + (PORT datac (989:989:989) (989:989:989)) + (PORT datad (969:969:969) (969:969:969)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|e\~0) + (DELAY + (ABSOLUTE + (PORT datab (987:987:987) (987:987:987)) + (PORT datac (987:987:987) (987:987:987)) + (PORT datad (968:968:968) (968:968:968)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (278:278:278) (278:278:278)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1267:1267:1267)) + (PORT datab (984:984:984) (984:984:984)) + (PORT datac (987:987:987) (987:987:987)) + (PORT datad (971:971:971) (971:971:971)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1262:1262:1262)) + (PORT datab (990:990:990) (990:990:990)) + (PORT datac (979:979:979) (979:979:979)) + (PORT datad (962:962:962) (962:962:962)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (864:864:864) (864:864:864)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst23\|v\~1) + (DELAY + (ABSOLUTE + (PORT dataa (5404:5404:5404) (5404:5404:5404)) + (PORT datab (310:310:310) (310:310:310)) + (PORT datac (300:300:300) (300:300:300)) + (PORT datad (329:329:329) (329:329:329)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (961:961:961) (961:961:961)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[3\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (688:688:688) (688:688:688)) + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[2\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (689:689:689) (689:689:689)) + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[1\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1255:1255:1255) (1255:1255:1255)) + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[0\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1019:1019:1019) (1019:1019:1019)) + (IOPATH datain padio (3006:3006:3006) (3006:3006:3006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (742:742:742) (742:742:742)) + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (743:743:743) (743:743:743)) + (IOPATH datain padio (2976:2976:2976) (2976:2976:2976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (960:960:960) (960:960:960)) + (IOPATH datain padio (2976:2976:2976) (2976:2976:2976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (701:701:701) (701:701:701)) + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (961:961:961) (961:961:961)) + (IOPATH datain padio (2976:2976:2976) (2976:2976:2976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (965:965:965) (965:965:965)) + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2976:2976:2976) (2976:2976:2976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3006:3006:3006) (3006:3006:3006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1055:1055:1055) (1055:1055:1055)) + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE overflow\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (946:946:946) (946:946:946)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE pin_name1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (754:754:754) (754:754:754)) + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) +) diff --git a/YL_adder/simulation/modelsim/YL_adder_v_fast.sdo b/YL_adder/simulation/modelsim/YL_adder_v_fast.sdo new file mode 100644 index 0000000..62ffd1e --- /dev/null +++ b/YL_adder/simulation/modelsim/YL_adder_v_fast.sdo @@ -0,0 +1,765 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "YL_adder") + (DATE "05/04/2020 17:05:47") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|44\~0) + (DELAY + (ABSOLUTE + (PORT datab (2833:2833:2833) (2833:2833:2833)) + (PORT datac (3060:3060:3060) (3060:3060:3060)) + (PORT datad (2979:2979:2979) (2979:2979:2979)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE clk\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE clk\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (186:186:186) (186:186:186)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE clk\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (260:260:260) (260:260:260)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (33:33:33)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE isAdd\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (475:475:475) (475:475:475)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst21\|o4\~2) + (DELAY + (ABSOLUTE + (PORT datab (981:981:981) (981:981:981)) + (PORT datad (2978:2978:2978) (2978:2978:2978)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (445:445:445) (445:445:445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (445:445:445) (445:445:445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|21\~0) + (DELAY + (ABSOLUTE + (PORT datab (2836:2836:2836) (2836:2836:2836)) + (PORT datac (3063:3063:3063) (3063:3063:3063)) + (PORT datad (2974:2974:2974) (2974:2974:2974)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (445:445:445) (445:445:445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst21\|o2\~2) + (DELAY + (ABSOLUTE + (PORT datab (2829:2829:2829) (2829:2829:2829)) + (PORT datad (2971:2971:2971) (2971:2971:2971)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|25) + (DELAY + (ABSOLUTE + (PORT datab (2836:2836:2836) (2836:2836:2836)) + (PORT datac (3063:3063:3063) (3063:3063:3063)) + (PORT datad (2976:2976:2976) (2976:2976:2976)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (197:197:197)) + (PORT datab (117:117:117) (117:117:117)) + (PORT datac (1023:1023:1023) (1023:1023:1023)) + (PORT datad (108:108:108) (108:108:108)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|45) + (DELAY + (ABSOLUTE + (PORT dataa (2918:2918:2918) (2918:2918:2918)) + (PORT datab (113:113:113) (113:113:113)) + (PORT datac (110:110:110) (110:110:110)) + (PORT datad (122:122:122) (122:122:122)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE reset\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (181:181:181) (181:181:181)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE reset\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (260:260:260) (260:260:260)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (33:33:33)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|16) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1047:1047:1047)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1037:1037:1037) (1037:1037:1037)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (465:465:465) (465:465:465)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (455:455:455) (455:455:455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|18\~0) + (DELAY + (ABSOLUTE + (PORT datab (2841:2841:2841) (2841:2841:2841)) + (PORT datac (2839:2839:2839) (2839:2839:2839)) + (PORT datad (2976:2976:2976) (2976:2976:2976)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|43) + (DELAY + (ABSOLUTE + (PORT dataa (2841:2841:2841) (2841:2841:2841)) + (PORT datab (111:111:111) (111:111:111)) + (PORT datac (1017:1017:1017) (1017:1017:1017)) + (PORT datad (2973:2973:2973) (2973:2973:2973)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|8) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1047:1047:1047)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1037:1037:1037) (1037:1037:1037)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|42) + (DELAY + (ABSOLUTE + (PORT datac (2839:2839:2839) (2839:2839:2839)) + (PORT datad (2841:2841:2841) (2841:2841:2841)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|1) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1047:1047:1047)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1037:1037:1037) (1037:1037:1037)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|44) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (109:109:109)) + (PORT datab (113:113:113) (113:113:113)) + (PORT datac (1022:1022:1022) (1022:1022:1022)) + (PORT datad (114:114:114) (114:114:114)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|15) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1047:1047:1047)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1037:1037:1037) (1037:1037:1037)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (503:503:503)) + (PORT datab (409:409:409) (409:409:409)) + (PORT datac (411:411:411) (411:411:411)) + (PORT datad (395:395:395) (395:395:395)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst20\|o\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (508:508:508)) + (PORT datab (403:403:403) (403:403:403)) + (PORT datac (418:418:418) (418:418:418)) + (PORT datad (400:400:400) (400:400:400)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst20\|o\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (504:504:504)) + (PORT datab (408:408:408) (408:408:408)) + (PORT datac (412:412:412) (412:412:412)) + (PORT datad (396:396:396) (396:396:396)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst20\|o\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (506:506:506)) + (PORT datac (417:417:417) (417:417:417)) + (PORT datad (401:401:401) (401:401:401)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (503:503:503)) + (PORT datab (410:410:410) (410:410:410)) + (PORT datac (408:408:408) (408:408:408)) + (PORT datad (392:392:392) (392:392:392)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (504:504:504)) + (PORT datab (408:408:408) (408:408:408)) + (PORT datac (412:412:412) (412:412:412)) + (PORT datad (396:396:396) (396:396:396)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|d\~0) + (DELAY + (ABSOLUTE + (PORT datab (402:402:402) (402:402:402)) + (PORT datac (417:417:417) (417:417:417)) + (PORT datad (399:399:399) (399:399:399)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|e\~0) + (DELAY + (ABSOLUTE + (PORT datab (406:406:406) (406:406:406)) + (PORT datac (414:414:414) (414:414:414)) + (PORT datad (397:397:397) (397:397:397)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (506:506:506)) + (PORT datab (404:404:404) (404:404:404)) + (PORT datac (416:416:416) (416:416:416)) + (PORT datad (399:399:399) (399:399:399)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (503:503:503)) + (PORT datab (409:409:409) (409:409:409)) + (PORT datac (408:408:408) (408:408:408)) + (PORT datad (392:392:392) (392:392:392)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (464:464:464) (464:464:464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst23\|v\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2915:2915:2915) (2915:2915:2915)) + (PORT datab (116:116:116) (116:116:116)) + (PORT datac (108:108:108) (108:108:108)) + (PORT datad (128:128:128) (128:128:128)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (361:361:361) (361:361:361)) + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[3\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (261:261:261) (261:261:261)) + (IOPATH datain padio (1513:1513:1513) (1513:1513:1513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[2\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (262:262:262) (262:262:262)) + (IOPATH datain padio (1513:1513:1513) (1513:1513:1513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[1\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (476:476:476) (476:476:476)) + (IOPATH datain padio (1523:1523:1523) (1523:1523:1523)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE i\[0\]\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (403:403:403) (403:403:403)) + (IOPATH datain padio (1533:1533:1533) (1533:1533:1533)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (292:292:292) (292:292:292)) + (IOPATH datain padio (1523:1523:1523) (1523:1523:1523)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (292:292:292) (292:292:292)) + (IOPATH datain padio (1503:1503:1503) (1503:1503:1503)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (363:363:363) (363:363:363)) + (IOPATH datain padio (1503:1503:1503) (1503:1503:1503)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (267:267:267) (267:267:267)) + (IOPATH datain padio (1513:1513:1513) (1513:1513:1513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (363:363:363) (363:363:363)) + (IOPATH datain padio (1503:1503:1503) (1503:1503:1503)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (365:365:365) (365:365:365)) + (IOPATH datain padio (1513:1513:1513) (1513:1513:1513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1513:1513:1513) (1513:1513:1513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1503:1503:1503) (1503:1503:1503)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1533:1533:1533) (1533:1533:1533)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (428:428:428) (428:428:428)) + (IOPATH datain padio (1523:1523:1523) (1523:1523:1523)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE overflow\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (353:353:353) (353:353:353)) + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE pin_name1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (307:307:307) (307:307:307)) + (IOPATH datain padio (1523:1523:1523) (1523:1523:1523)) + ) + ) + ) +) diff --git a/YL_adder/simulation/qsim/YL_adder.do b/YL_adder/simulation/qsim/YL_adder.do new file mode 100644 index 0000000..5a9b7cb --- /dev/null +++ b/YL_adder/simulation/qsim/YL_adder.do @@ -0,0 +1,10 @@ +onerror {quit -f} +vlib work +vlog -work work YL_adder.vo +vlog -work work YL_adder.vt +vsim -novopt -c -t 1ps -L cycloneii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.YL_adder_vlg_vec_tst +vcd file -direction YL_adder.msim.vcd +vcd add -internal YL_adder_vlg_vec_tst/* +vcd add -internal YL_adder_vlg_vec_tst/i1/* +add wave /* +run -all diff --git a/YL_adder/simulation/qsim/YL_adder.sim.vwf b/YL_adder/simulation/qsim/YL_adder.sim.vwf new file mode 100644 index 0000000..a7ac176 --- /dev/null +++ b/YL_adder/simulation/qsim/YL_adder.sim.vwf @@ -0,0 +1,1103 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 1000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_A4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("INPUT_B4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("isAdd") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("overflow") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("i") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("i[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +SIGNAL("i[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "i"; +} + +GROUP("INPUT_B") +{ + MEMBERS = "INPUT_B1", "INPUT_B2", "INPUT_B3", "INPUT_B4"; +} + +GROUP("INPUT_A") +{ + MEMBERS = "INPUT_A4", "INPUT_A3", "INPUT_A2", "INPUT_A1"; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("INPUT_A1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("INPUT_A2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_A3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_A4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("INPUT_B1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + NODE + { + REPEAT = 3; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("INPUT_B2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("INPUT_B3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("INPUT_B4") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 800.0; + LEVEL 1 FOR 200.0; + } + } +} + +TRANSITION_LIST("isAdd") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 50.0; + } +} + +TRANSITION_LIST("OUTPUT_A2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 50.0; + } +} + +TRANSITION_LIST("OUTPUT_B2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 610.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 350.0; + } +} + +TRANSITION_LIST("OUTPUT_C2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + NODE + { + REPEAT = 2; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 40.0; + } + LEVEL 1 FOR 100.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + } + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 50.0; + } +} + +TRANSITION_LIST("OUTPUT_D2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 140.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 150.0; + } +} + +TRANSITION_LIST("OUTPUT_E2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + NODE + { + REPEAT = 2; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + } + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + } +} + +TRANSITION_LIST("OUTPUT_F2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 110.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + } +} + +TRANSITION_LIST("OUTPUT_G2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 310.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 190.0; + } +} + +TRANSITION_LIST("overflow") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 600.0; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("i[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 810.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 150.0; + } +} + +TRANSITION_LIST("i[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 150.0; + } +} + +TRANSITION_LIST("i[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + } + LEVEL 0 FOR 90.0; + } +} + +TRANSITION_LIST("i[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + NODE + { + REPEAT = 4; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + } + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 50.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "isAdd"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_A1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 8; + TREE_LEVEL = 0; + CHILDREN = 9, 10, 11, 12; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "INPUT_B1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Signed; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 8; +} + +DISPLAY_LINE +{ + CHANNEL = "i"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 13; + TREE_LEVEL = 0; + CHILDREN = 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "i[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "i[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "overflow"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 27; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 28; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 29; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 30; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_F2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 31; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_G2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 32; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_adder/simulation/qsim/YL_adder.vo b/YL_adder/simulation/qsim/YL_adder.vo new file mode 100644 index 0000000..e023361 --- /dev/null +++ b/YL_adder/simulation/qsim/YL_adder.vo @@ -0,0 +1,1561 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/04/2020 16:45:16" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_adder ( + OUTPUT_A, + reset, + INPUT_B1, + INPUT_B2, + INPUT_B3, + INPUT_B4, + isAdd, + INPUT_A1, + INPUT_A2, + INPUT_A3, + INPUT_A4, + clk, + OUTPUT_B, + OUTPUT_C, + OUTPUT_D, + OUTPUT_E, + OUTPUT_F, + OUTPUT_G, + OUTPUT_A2, + OUTPUT_B2, + OUTPUT_C2, + OUTPUT_D2, + OUTPUT_E2, + OUTPUT_F2, + OUTPUT_G2, + overflow, + num); +output OUTPUT_A; +input reset; +input INPUT_B1; +input INPUT_B2; +input INPUT_B3; +input INPUT_B4; +input isAdd; +input INPUT_A1; +input INPUT_A2; +input INPUT_A3; +input INPUT_A4; +input clk; +output OUTPUT_B; +output OUTPUT_C; +output OUTPUT_D; +output OUTPUT_E; +output OUTPUT_F; +output OUTPUT_G; +output OUTPUT_A2; +output OUTPUT_B2; +output OUTPUT_C2; +output OUTPUT_D2; +output OUTPUT_E2; +output OUTPUT_F2; +output OUTPUT_G2; +output overflow; +output num; + +// Design Ports Information +// OUTPUT_A => Location: PIN_F15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B => Location: PIN_H13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D => Location: PIN_C20, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E => Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F => Location: PIN_D15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G => Location: PIN_D19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_A2 => Location: PIN_R16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_B2 => Location: PIN_AA20, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_C2 => Location: PIN_G17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_D2 => Location: PIN_E14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_E2 => Location: PIN_P18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_F2 => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// OUTPUT_G2 => Location: PIN_B18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// overflow => Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// num => Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// INPUT_A4 => Location: PIN_G16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B3 => Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// isAdd => Location: PIN_H14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A3 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B2 => Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B1 => Location: PIN_C16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A1 => Location: PIN_D16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_A2 => Location: PIN_G15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// INPUT_B4 => Location: PIN_E15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// reset => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("YL_adder_v.sdo"); +// synopsys translate_on + +wire \inst|51~0_combout ; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \INPUT_A1~combout ; +wire \INPUT_B1~combout ; +wire \inst|42~combout ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \inst1|1~regout ; +wire \INPUT_B4~combout ; +wire \isAdd~combout ; +wire \inst21|o4~2_combout ; +wire \INPUT_A3~combout ; +wire \INPUT_B3~combout ; +wire \inst|21~0_combout ; +wire \INPUT_A2~combout ; +wire \inst|25~combout ; +wire \INPUT_B2~combout ; +wire \inst21|o2~2_combout ; +wire \inst|1~0_combout ; +wire \inst|45~combout ; +wire \inst1|16~regout ; +wire \inst|44~0_combout ; +wire \inst|44~combout ; +wire \inst1|15~regout ; +wire \inst|43~0_combout ; +wire \inst|43~combout ; +wire \inst1|8~regout ; +wire \inst17|a~12_combout ; +wire \inst17|b~3_combout ; +wire \inst17|c~1_combout ; +wire \inst17|d~0_combout ; +wire \inst17|e~0_combout ; +wire \inst17|f~0_combout ; +wire \inst17|g~0_combout ; +wire \INPUT_A4~combout ; +wire \inst23|v~1_combout ; + + +// Location: LCCOMB_X43_Y26_N12 +cycloneii_lcell_comb \inst|51~0 ( +// Equation(s): +// \inst|51~0_combout = (\INPUT_B1~combout & (!\isAdd~combout )) # (!\INPUT_B1~combout & ((!\INPUT_A1~combout ))) + + .dataa(\isAdd~combout ), + .datab(vcc), + .datac(\INPUT_A1~combout ), + .datad(\INPUT_B1~combout ), + .cin(gnd), + .combout(\inst|51~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|51~0 .lut_mask = 16'h550F; +defparam \inst|51~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_D16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A1~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A1~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A1)); +// synopsys translate_off +defparam \INPUT_A1~I .input_async_reset = "none"; +defparam \INPUT_A1~I .input_power_up = "low"; +defparam \INPUT_A1~I .input_register_mode = "none"; +defparam \INPUT_A1~I .input_sync_reset = "none"; +defparam \INPUT_A1~I .oe_async_reset = "none"; +defparam \INPUT_A1~I .oe_power_up = "low"; +defparam \INPUT_A1~I .oe_register_mode = "none"; +defparam \INPUT_A1~I .oe_sync_reset = "none"; +defparam \INPUT_A1~I .operation_mode = "input"; +defparam \INPUT_A1~I .output_async_reset = "none"; +defparam \INPUT_A1~I .output_power_up = "low"; +defparam \INPUT_A1~I .output_register_mode = "none"; +defparam \INPUT_A1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B1~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B1~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B1)); +// synopsys translate_off +defparam \INPUT_B1~I .input_async_reset = "none"; +defparam \INPUT_B1~I .input_power_up = "low"; +defparam \INPUT_B1~I .input_register_mode = "none"; +defparam \INPUT_B1~I .input_sync_reset = "none"; +defparam \INPUT_B1~I .oe_async_reset = "none"; +defparam \INPUT_B1~I .oe_power_up = "low"; +defparam \INPUT_B1~I .oe_register_mode = "none"; +defparam \INPUT_B1~I .oe_sync_reset = "none"; +defparam \INPUT_B1~I .operation_mode = "input"; +defparam \INPUT_B1~I .output_async_reset = "none"; +defparam \INPUT_B1~I .output_power_up = "low"; +defparam \INPUT_B1~I .output_register_mode = "none"; +defparam \INPUT_B1~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N4 +cycloneii_lcell_comb \inst|42 ( +// Equation(s): +// \inst|42~combout = \INPUT_A1~combout $ (!\INPUT_B1~combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\INPUT_A1~combout ), + .datad(\INPUT_B1~combout ), + .cin(gnd), + .combout(\inst|42~combout ), + .cout()); +// synopsys translate_off +defparam \inst|42 .lut_mask = 16'hF00F; +defparam \inst|42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \reset~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\reset~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(reset)); +// synopsys translate_off +defparam \reset~I .input_async_reset = "none"; +defparam \reset~I .input_power_up = "low"; +defparam \reset~I .input_register_mode = "none"; +defparam \reset~I .input_sync_reset = "none"; +defparam \reset~I .oe_async_reset = "none"; +defparam \reset~I .oe_power_up = "low"; +defparam \reset~I .oe_register_mode = "none"; +defparam \reset~I .oe_sync_reset = "none"; +defparam \reset~I .operation_mode = "input"; +defparam \reset~I .output_async_reset = "none"; +defparam \reset~I .output_power_up = "low"; +defparam \reset~I .output_register_mode = "none"; +defparam \reset~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneii_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N5 +cycloneii_lcell_ff \inst1|1 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|42~combout ), + .sdata(gnd), + .aclr(!\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|1~regout )); + +// Location: PIN_E15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B4~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B4~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B4)); +// synopsys translate_off +defparam \INPUT_B4~I .input_async_reset = "none"; +defparam \INPUT_B4~I .input_power_up = "low"; +defparam \INPUT_B4~I .input_register_mode = "none"; +defparam \INPUT_B4~I .input_sync_reset = "none"; +defparam \INPUT_B4~I .oe_async_reset = "none"; +defparam \INPUT_B4~I .oe_power_up = "low"; +defparam \INPUT_B4~I .oe_register_mode = "none"; +defparam \INPUT_B4~I .oe_sync_reset = "none"; +defparam \INPUT_B4~I .operation_mode = "input"; +defparam \INPUT_B4~I .output_async_reset = "none"; +defparam \INPUT_B4~I .output_power_up = "low"; +defparam \INPUT_B4~I .output_register_mode = "none"; +defparam \INPUT_B4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \isAdd~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\isAdd~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(isAdd)); +// synopsys translate_off +defparam \isAdd~I .input_async_reset = "none"; +defparam \isAdd~I .input_power_up = "low"; +defparam \isAdd~I .input_register_mode = "none"; +defparam \isAdd~I .input_sync_reset = "none"; +defparam \isAdd~I .oe_async_reset = "none"; +defparam \isAdd~I .oe_power_up = "low"; +defparam \isAdd~I .oe_register_mode = "none"; +defparam \isAdd~I .oe_sync_reset = "none"; +defparam \isAdd~I .operation_mode = "input"; +defparam \isAdd~I .output_async_reset = "none"; +defparam \isAdd~I .output_power_up = "low"; +defparam \isAdd~I .output_register_mode = "none"; +defparam \isAdd~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N2 +cycloneii_lcell_comb \inst21|o4~2 ( +// Equation(s): +// \inst21|o4~2_combout = \INPUT_B4~combout $ (\isAdd~combout ) + + .dataa(vcc), + .datab(\INPUT_B4~combout ), + .datac(\isAdd~combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst21|o4~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst21|o4~2 .lut_mask = 16'h3C3C; +defparam \inst21|o4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A3~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A3~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A3)); +// synopsys translate_off +defparam \INPUT_A3~I .input_async_reset = "none"; +defparam \INPUT_A3~I .input_power_up = "low"; +defparam \INPUT_A3~I .input_register_mode = "none"; +defparam \INPUT_A3~I .input_sync_reset = "none"; +defparam \INPUT_A3~I .oe_async_reset = "none"; +defparam \INPUT_A3~I .oe_power_up = "low"; +defparam \INPUT_A3~I .oe_register_mode = "none"; +defparam \INPUT_A3~I .oe_sync_reset = "none"; +defparam \INPUT_A3~I .operation_mode = "input"; +defparam \INPUT_A3~I .output_async_reset = "none"; +defparam \INPUT_A3~I .output_power_up = "low"; +defparam \INPUT_A3~I .output_register_mode = "none"; +defparam \INPUT_A3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B3~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B3~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B3)); +// synopsys translate_off +defparam \INPUT_B3~I .input_async_reset = "none"; +defparam \INPUT_B3~I .input_power_up = "low"; +defparam \INPUT_B3~I .input_register_mode = "none"; +defparam \INPUT_B3~I .input_sync_reset = "none"; +defparam \INPUT_B3~I .oe_async_reset = "none"; +defparam \INPUT_B3~I .oe_power_up = "low"; +defparam \INPUT_B3~I .oe_register_mode = "none"; +defparam \INPUT_B3~I .oe_sync_reset = "none"; +defparam \INPUT_B3~I .operation_mode = "input"; +defparam \INPUT_B3~I .output_async_reset = "none"; +defparam \INPUT_B3~I .output_power_up = "low"; +defparam \INPUT_B3~I .output_register_mode = "none"; +defparam \INPUT_B3~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N8 +cycloneii_lcell_comb \inst|21~0 ( +// Equation(s): +// \inst|21~0_combout = (!\INPUT_A3~combout & (\isAdd~combout $ (\INPUT_B3~combout ))) + + .dataa(\isAdd~combout ), + .datab(vcc), + .datac(\INPUT_A3~combout ), + .datad(\INPUT_B3~combout ), + .cin(gnd), + .combout(\inst|21~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|21~0 .lut_mask = 16'h050A; +defparam \inst|21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_G15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A2~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A2~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A2)); +// synopsys translate_off +defparam \INPUT_A2~I .input_async_reset = "none"; +defparam \INPUT_A2~I .input_power_up = "low"; +defparam \INPUT_A2~I .input_register_mode = "none"; +defparam \INPUT_A2~I .input_sync_reset = "none"; +defparam \INPUT_A2~I .oe_async_reset = "none"; +defparam \INPUT_A2~I .oe_power_up = "low"; +defparam \INPUT_A2~I .oe_register_mode = "none"; +defparam \INPUT_A2~I .oe_sync_reset = "none"; +defparam \INPUT_A2~I .operation_mode = "input"; +defparam \INPUT_A2~I .output_async_reset = "none"; +defparam \INPUT_A2~I .output_power_up = "low"; +defparam \INPUT_A2~I .output_register_mode = "none"; +defparam \INPUT_A2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N6 +cycloneii_lcell_comb \inst|25 ( +// Equation(s): +// \inst|25~combout = (\INPUT_A3~combout & (\isAdd~combout $ (!\INPUT_B3~combout ))) + + .dataa(\isAdd~combout ), + .datab(vcc), + .datac(\INPUT_A3~combout ), + .datad(\INPUT_B3~combout ), + .cin(gnd), + .combout(\inst|25~combout ), + .cout()); +// synopsys translate_off +defparam \inst|25 .lut_mask = 16'hA050; +defparam \inst|25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_B2~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_B2~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_B2)); +// synopsys translate_off +defparam \INPUT_B2~I .input_async_reset = "none"; +defparam \INPUT_B2~I .input_power_up = "low"; +defparam \INPUT_B2~I .input_register_mode = "none"; +defparam \INPUT_B2~I .input_sync_reset = "none"; +defparam \INPUT_B2~I .oe_async_reset = "none"; +defparam \INPUT_B2~I .oe_power_up = "low"; +defparam \INPUT_B2~I .oe_register_mode = "none"; +defparam \INPUT_B2~I .oe_sync_reset = "none"; +defparam \INPUT_B2~I .operation_mode = "input"; +defparam \INPUT_B2~I .output_async_reset = "none"; +defparam \INPUT_B2~I .output_power_up = "low"; +defparam \INPUT_B2~I .output_register_mode = "none"; +defparam \INPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N10 +cycloneii_lcell_comb \inst21|o2~2 ( +// Equation(s): +// \inst21|o2~2_combout = \INPUT_B2~combout $ (\isAdd~combout ) + + .dataa(vcc), + .datab(\INPUT_B2~combout ), + .datac(\isAdd~combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst21|o2~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst21|o2~2 .lut_mask = 16'h3C3C; +defparam \inst21|o2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N0 +cycloneii_lcell_comb \inst|1~0 ( +// Equation(s): +// \inst|1~0_combout = (!\inst|25~combout & ((\inst|51~0_combout & ((\inst21|o2~2_combout ) # (!\INPUT_A2~combout ))) # (!\inst|51~0_combout & (!\INPUT_A2~combout & \inst21|o2~2_combout )))) + + .dataa(\inst|51~0_combout ), + .datab(\INPUT_A2~combout ), + .datac(\inst|25~combout ), + .datad(\inst21|o2~2_combout ), + .cin(gnd), + .combout(\inst|1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|1~0 .lut_mask = 16'h0B02; +defparam \inst|1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N18 +cycloneii_lcell_comb \inst|45 ( +// Equation(s): +// \inst|45~combout = \INPUT_A4~combout $ (\inst21|o4~2_combout $ (((\inst|21~0_combout ) # (\inst|1~0_combout )))) + + .dataa(\INPUT_A4~combout ), + .datab(\inst21|o4~2_combout ), + .datac(\inst|21~0_combout ), + .datad(\inst|1~0_combout ), + .cin(gnd), + .combout(\inst|45~combout ), + .cout()); +// synopsys translate_off +defparam \inst|45 .lut_mask = 16'h9996; +defparam \inst|45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N19 +cycloneii_lcell_ff \inst1|16 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|45~combout ), + .sdata(gnd), + .aclr(!\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|16~regout )); + +// Location: LCCOMB_X43_Y26_N22 +cycloneii_lcell_comb \inst|44~0 ( +// Equation(s): +// \inst|44~0_combout = \isAdd~combout $ (\INPUT_A3~combout $ (\INPUT_B3~combout )) + + .dataa(\isAdd~combout ), + .datab(vcc), + .datac(\INPUT_A3~combout ), + .datad(\INPUT_B3~combout ), + .cin(gnd), + .combout(\inst|44~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|44~0 .lut_mask = 16'hA55A; +defparam \inst|44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N24 +cycloneii_lcell_comb \inst|44 ( +// Equation(s): +// \inst|44~combout = \inst|44~0_combout $ (((\inst|51~0_combout & ((\inst21|o2~2_combout ) # (!\INPUT_A2~combout ))) # (!\inst|51~0_combout & (!\INPUT_A2~combout & \inst21|o2~2_combout )))) + + .dataa(\inst|51~0_combout ), + .datab(\inst|44~0_combout ), + .datac(\INPUT_A2~combout ), + .datad(\inst21|o2~2_combout ), + .cin(gnd), + .combout(\inst|44~combout ), + .cout()); +// synopsys translate_off +defparam \inst|44 .lut_mask = 16'h63C6; +defparam \inst|44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N25 +cycloneii_lcell_ff \inst1|15 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|44~combout ), + .sdata(gnd), + .aclr(!\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|15~regout )); + +// Location: LCCOMB_X43_Y26_N16 +cycloneii_lcell_comb \inst|43~0 ( +// Equation(s): +// \inst|43~0_combout = \INPUT_B2~combout $ (((!\INPUT_B1~combout & (\isAdd~combout $ (\INPUT_A1~combout ))))) + + .dataa(\isAdd~combout ), + .datab(\INPUT_B2~combout ), + .datac(\INPUT_A1~combout ), + .datad(\INPUT_B1~combout ), + .cin(gnd), + .combout(\inst|43~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|43~0 .lut_mask = 16'hCC96; +defparam \inst|43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N30 +cycloneii_lcell_comb \inst|43 ( +// Equation(s): +// \inst|43~combout = \INPUT_A2~combout $ (!\inst|43~0_combout ) + + .dataa(vcc), + .datab(\INPUT_A2~combout ), + .datac(\inst|43~0_combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst|43~combout ), + .cout()); +// synopsys translate_off +defparam \inst|43 .lut_mask = 16'hC3C3; +defparam \inst|43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X43_Y26_N31 +cycloneii_lcell_ff \inst1|8 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|43~combout ), + .sdata(gnd), + .aclr(!\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|8~regout )); + +// Location: LCCOMB_X42_Y26_N16 +cycloneii_lcell_comb \inst17|a~12 ( +// Equation(s): +// \inst17|a~12_combout = (\inst1|16~regout & (\inst1|15~regout & (\inst1|1~regout $ (!\inst1|8~regout )))) # (!\inst1|16~regout & (!\inst1|8~regout & (\inst1|1~regout $ (\inst1|15~regout )))) + + .dataa(\inst1|1~regout ), + .datab(\inst1|16~regout ), + .datac(\inst1|15~regout ), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst17|a~12_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|a~12 .lut_mask = 16'h8052; +defparam \inst17|a~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X42_Y26_N2 +cycloneii_lcell_comb \inst17|b~3 ( +// Equation(s): +// \inst17|b~3_combout = (\inst1|16~regout & (((!\inst1|15~regout & \inst1|8~regout )))) # (!\inst1|16~regout & (\inst1|15~regout & (\inst1|1~regout $ (\inst1|8~regout )))) + + .dataa(\inst1|1~regout ), + .datab(\inst1|16~regout ), + .datac(\inst1|15~regout ), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst17|b~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|b~3 .lut_mask = 16'h1C20; +defparam \inst17|b~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X42_Y26_N28 +cycloneii_lcell_comb \inst17|c~1 ( +// Equation(s): +// \inst17|c~1_combout = (!\inst1|1~regout & (\inst1|8~regout & (\inst1|16~regout $ (!\inst1|15~regout )))) + + .dataa(\inst1|1~regout ), + .datab(\inst1|16~regout ), + .datac(\inst1|15~regout ), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst17|c~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|c~1 .lut_mask = 16'h4100; +defparam \inst17|c~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X42_Y26_N6 +cycloneii_lcell_comb \inst17|d~0 ( +// Equation(s): +// \inst17|d~0_combout = (\inst1|1~regout & (\inst1|15~regout $ (!\inst1|8~regout ))) # (!\inst1|1~regout & (\inst1|15~regout & !\inst1|8~regout )) + + .dataa(\inst1|1~regout ), + .datab(\inst1|15~regout ), + .datac(vcc), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst17|d~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|d~0 .lut_mask = 16'h8866; +defparam \inst17|d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X42_Y26_N0 +cycloneii_lcell_comb \inst17|e~0 ( +// Equation(s): +// \inst17|e~0_combout = (\inst1|1~regout ) # ((\inst1|15~regout & !\inst1|8~regout )) + + .dataa(\inst1|1~regout ), + .datab(\inst1|15~regout ), + .datac(vcc), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst17|e~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|e~0 .lut_mask = 16'hAAEE; +defparam \inst17|e~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X42_Y26_N18 +cycloneii_lcell_comb \inst17|f~0 ( +// Equation(s): +// \inst17|f~0_combout = (\inst1|8~regout & ((\inst1|16~regout & ((\inst1|15~regout ))) # (!\inst1|16~regout & ((\inst1|1~regout ) # (!\inst1|15~regout ))))) # (!\inst1|8~regout & (\inst1|1~regout & ((\inst1|16~regout ) # (!\inst1|15~regout )))) + + .dataa(\inst1|1~regout ), + .datab(\inst1|16~regout ), + .datac(\inst1|15~regout ), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst17|f~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|f~0 .lut_mask = 16'hE38A; +defparam \inst17|f~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X42_Y26_N12 +cycloneii_lcell_comb \inst17|g~0 ( +// Equation(s): +// \inst17|g~0_combout = (\inst1|1~regout & ((\inst1|15~regout $ (\inst1|8~regout )))) # (!\inst1|1~regout & ((\inst1|16~regout ) # ((\inst1|15~regout ) # (\inst1|8~regout )))) + + .dataa(\inst1|1~regout ), + .datab(\inst1|16~regout ), + .datac(\inst1|15~regout ), + .datad(\inst1|8~regout ), + .cin(gnd), + .combout(\inst17|g~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst17|g~0 .lut_mask = 16'h5FF4; +defparam \inst17|g~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_G16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \INPUT_A4~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\INPUT_A4~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(INPUT_A4)); +// synopsys translate_off +defparam \INPUT_A4~I .input_async_reset = "none"; +defparam \INPUT_A4~I .input_power_up = "low"; +defparam \INPUT_A4~I .input_register_mode = "none"; +defparam \INPUT_A4~I .input_sync_reset = "none"; +defparam \INPUT_A4~I .oe_async_reset = "none"; +defparam \INPUT_A4~I .oe_power_up = "low"; +defparam \INPUT_A4~I .oe_register_mode = "none"; +defparam \INPUT_A4~I .oe_sync_reset = "none"; +defparam \INPUT_A4~I .operation_mode = "input"; +defparam \INPUT_A4~I .output_async_reset = "none"; +defparam \INPUT_A4~I .output_power_up = "low"; +defparam \INPUT_A4~I .output_register_mode = "none"; +defparam \INPUT_A4~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X43_Y26_N28 +cycloneii_lcell_comb \inst23|v~1 ( +// Equation(s): +// \inst23|v~1_combout = (\INPUT_A4~combout & (!\inst21|o4~2_combout & ((\inst|21~0_combout ) # (\inst|1~0_combout )))) # (!\INPUT_A4~combout & (\inst21|o4~2_combout & (!\inst|21~0_combout & !\inst|1~0_combout ))) + + .dataa(\INPUT_A4~combout ), + .datab(\inst21|o4~2_combout ), + .datac(\inst|21~0_combout ), + .datad(\inst|1~0_combout ), + .cin(gnd), + .combout(\inst23|v~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst23|v~1 .lut_mask = 16'h2224; +defparam \inst23|v~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_F15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A~I ( + .datain(\inst17|a~12_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A)); +// synopsys translate_off +defparam \OUTPUT_A~I .input_async_reset = "none"; +defparam \OUTPUT_A~I .input_power_up = "low"; +defparam \OUTPUT_A~I .input_register_mode = "none"; +defparam \OUTPUT_A~I .input_sync_reset = "none"; +defparam \OUTPUT_A~I .oe_async_reset = "none"; +defparam \OUTPUT_A~I .oe_power_up = "low"; +defparam \OUTPUT_A~I .oe_register_mode = "none"; +defparam \OUTPUT_A~I .oe_sync_reset = "none"; +defparam \OUTPUT_A~I .operation_mode = "output"; +defparam \OUTPUT_A~I .output_async_reset = "none"; +defparam \OUTPUT_A~I .output_power_up = "low"; +defparam \OUTPUT_A~I .output_register_mode = "none"; +defparam \OUTPUT_A~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B~I ( + .datain(\inst17|b~3_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B)); +// synopsys translate_off +defparam \OUTPUT_B~I .input_async_reset = "none"; +defparam \OUTPUT_B~I .input_power_up = "low"; +defparam \OUTPUT_B~I .input_register_mode = "none"; +defparam \OUTPUT_B~I .input_sync_reset = "none"; +defparam \OUTPUT_B~I .oe_async_reset = "none"; +defparam \OUTPUT_B~I .oe_power_up = "low"; +defparam \OUTPUT_B~I .oe_register_mode = "none"; +defparam \OUTPUT_B~I .oe_sync_reset = "none"; +defparam \OUTPUT_B~I .operation_mode = "output"; +defparam \OUTPUT_B~I .output_async_reset = "none"; +defparam \OUTPUT_B~I .output_power_up = "low"; +defparam \OUTPUT_B~I .output_register_mode = "none"; +defparam \OUTPUT_B~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C~I ( + .datain(\inst17|c~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C)); +// synopsys translate_off +defparam \OUTPUT_C~I .input_async_reset = "none"; +defparam \OUTPUT_C~I .input_power_up = "low"; +defparam \OUTPUT_C~I .input_register_mode = "none"; +defparam \OUTPUT_C~I .input_sync_reset = "none"; +defparam \OUTPUT_C~I .oe_async_reset = "none"; +defparam \OUTPUT_C~I .oe_power_up = "low"; +defparam \OUTPUT_C~I .oe_register_mode = "none"; +defparam \OUTPUT_C~I .oe_sync_reset = "none"; +defparam \OUTPUT_C~I .operation_mode = "output"; +defparam \OUTPUT_C~I .output_async_reset = "none"; +defparam \OUTPUT_C~I .output_power_up = "low"; +defparam \OUTPUT_C~I .output_register_mode = "none"; +defparam \OUTPUT_C~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C20, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D~I ( + .datain(\inst17|d~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D)); +// synopsys translate_off +defparam \OUTPUT_D~I .input_async_reset = "none"; +defparam \OUTPUT_D~I .input_power_up = "low"; +defparam \OUTPUT_D~I .input_register_mode = "none"; +defparam \OUTPUT_D~I .input_sync_reset = "none"; +defparam \OUTPUT_D~I .oe_async_reset = "none"; +defparam \OUTPUT_D~I .oe_power_up = "low"; +defparam \OUTPUT_D~I .oe_register_mode = "none"; +defparam \OUTPUT_D~I .oe_sync_reset = "none"; +defparam \OUTPUT_D~I .operation_mode = "output"; +defparam \OUTPUT_D~I .output_async_reset = "none"; +defparam \OUTPUT_D~I .output_power_up = "low"; +defparam \OUTPUT_D~I .output_register_mode = "none"; +defparam \OUTPUT_D~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E~I ( + .datain(\inst17|e~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E)); +// synopsys translate_off +defparam \OUTPUT_E~I .input_async_reset = "none"; +defparam \OUTPUT_E~I .input_power_up = "low"; +defparam \OUTPUT_E~I .input_register_mode = "none"; +defparam \OUTPUT_E~I .input_sync_reset = "none"; +defparam \OUTPUT_E~I .oe_async_reset = "none"; +defparam \OUTPUT_E~I .oe_power_up = "low"; +defparam \OUTPUT_E~I .oe_register_mode = "none"; +defparam \OUTPUT_E~I .oe_sync_reset = "none"; +defparam \OUTPUT_E~I .operation_mode = "output"; +defparam \OUTPUT_E~I .output_async_reset = "none"; +defparam \OUTPUT_E~I .output_power_up = "low"; +defparam \OUTPUT_E~I .output_register_mode = "none"; +defparam \OUTPUT_E~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F~I ( + .datain(\inst17|f~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F)); +// synopsys translate_off +defparam \OUTPUT_F~I .input_async_reset = "none"; +defparam \OUTPUT_F~I .input_power_up = "low"; +defparam \OUTPUT_F~I .input_register_mode = "none"; +defparam \OUTPUT_F~I .input_sync_reset = "none"; +defparam \OUTPUT_F~I .oe_async_reset = "none"; +defparam \OUTPUT_F~I .oe_power_up = "low"; +defparam \OUTPUT_F~I .oe_register_mode = "none"; +defparam \OUTPUT_F~I .oe_sync_reset = "none"; +defparam \OUTPUT_F~I .operation_mode = "output"; +defparam \OUTPUT_F~I .output_async_reset = "none"; +defparam \OUTPUT_F~I .output_power_up = "low"; +defparam \OUTPUT_F~I .output_register_mode = "none"; +defparam \OUTPUT_F~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G~I ( + .datain(!\inst17|g~0_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G)); +// synopsys translate_off +defparam \OUTPUT_G~I .input_async_reset = "none"; +defparam \OUTPUT_G~I .input_power_up = "low"; +defparam \OUTPUT_G~I .input_register_mode = "none"; +defparam \OUTPUT_G~I .input_sync_reset = "none"; +defparam \OUTPUT_G~I .oe_async_reset = "none"; +defparam \OUTPUT_G~I .oe_power_up = "low"; +defparam \OUTPUT_G~I .oe_register_mode = "none"; +defparam \OUTPUT_G~I .oe_sync_reset = "none"; +defparam \OUTPUT_G~I .operation_mode = "output"; +defparam \OUTPUT_G~I .output_async_reset = "none"; +defparam \OUTPUT_G~I .output_power_up = "low"; +defparam \OUTPUT_G~I .output_register_mode = "none"; +defparam \OUTPUT_G~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_A2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_A2)); +// synopsys translate_off +defparam \OUTPUT_A2~I .input_async_reset = "none"; +defparam \OUTPUT_A2~I .input_power_up = "low"; +defparam \OUTPUT_A2~I .input_register_mode = "none"; +defparam \OUTPUT_A2~I .input_sync_reset = "none"; +defparam \OUTPUT_A2~I .oe_async_reset = "none"; +defparam \OUTPUT_A2~I .oe_power_up = "low"; +defparam \OUTPUT_A2~I .oe_register_mode = "none"; +defparam \OUTPUT_A2~I .oe_sync_reset = "none"; +defparam \OUTPUT_A2~I .operation_mode = "output"; +defparam \OUTPUT_A2~I .output_async_reset = "none"; +defparam \OUTPUT_A2~I .output_power_up = "low"; +defparam \OUTPUT_A2~I .output_register_mode = "none"; +defparam \OUTPUT_A2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA20, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_B2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_B2)); +// synopsys translate_off +defparam \OUTPUT_B2~I .input_async_reset = "none"; +defparam \OUTPUT_B2~I .input_power_up = "low"; +defparam \OUTPUT_B2~I .input_register_mode = "none"; +defparam \OUTPUT_B2~I .input_sync_reset = "none"; +defparam \OUTPUT_B2~I .oe_async_reset = "none"; +defparam \OUTPUT_B2~I .oe_power_up = "low"; +defparam \OUTPUT_B2~I .oe_register_mode = "none"; +defparam \OUTPUT_B2~I .oe_sync_reset = "none"; +defparam \OUTPUT_B2~I .operation_mode = "output"; +defparam \OUTPUT_B2~I .output_async_reset = "none"; +defparam \OUTPUT_B2~I .output_power_up = "low"; +defparam \OUTPUT_B2~I .output_register_mode = "none"; +defparam \OUTPUT_B2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_G17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_C2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_C2)); +// synopsys translate_off +defparam \OUTPUT_C2~I .input_async_reset = "none"; +defparam \OUTPUT_C2~I .input_power_up = "low"; +defparam \OUTPUT_C2~I .input_register_mode = "none"; +defparam \OUTPUT_C2~I .input_sync_reset = "none"; +defparam \OUTPUT_C2~I .oe_async_reset = "none"; +defparam \OUTPUT_C2~I .oe_power_up = "low"; +defparam \OUTPUT_C2~I .oe_register_mode = "none"; +defparam \OUTPUT_C2~I .oe_sync_reset = "none"; +defparam \OUTPUT_C2~I .operation_mode = "output"; +defparam \OUTPUT_C2~I .output_async_reset = "none"; +defparam \OUTPUT_C2~I .output_power_up = "low"; +defparam \OUTPUT_C2~I .output_register_mode = "none"; +defparam \OUTPUT_C2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_E14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_D2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_D2)); +// synopsys translate_off +defparam \OUTPUT_D2~I .input_async_reset = "none"; +defparam \OUTPUT_D2~I .input_power_up = "low"; +defparam \OUTPUT_D2~I .input_register_mode = "none"; +defparam \OUTPUT_D2~I .input_sync_reset = "none"; +defparam \OUTPUT_D2~I .oe_async_reset = "none"; +defparam \OUTPUT_D2~I .oe_power_up = "low"; +defparam \OUTPUT_D2~I .oe_register_mode = "none"; +defparam \OUTPUT_D2~I .oe_sync_reset = "none"; +defparam \OUTPUT_D2~I .operation_mode = "output"; +defparam \OUTPUT_D2~I .output_async_reset = "none"; +defparam \OUTPUT_D2~I .output_power_up = "low"; +defparam \OUTPUT_D2~I .output_register_mode = "none"; +defparam \OUTPUT_D2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_E2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_E2)); +// synopsys translate_off +defparam \OUTPUT_E2~I .input_async_reset = "none"; +defparam \OUTPUT_E2~I .input_power_up = "low"; +defparam \OUTPUT_E2~I .input_register_mode = "none"; +defparam \OUTPUT_E2~I .input_sync_reset = "none"; +defparam \OUTPUT_E2~I .oe_async_reset = "none"; +defparam \OUTPUT_E2~I .oe_power_up = "low"; +defparam \OUTPUT_E2~I .oe_register_mode = "none"; +defparam \OUTPUT_E2~I .oe_sync_reset = "none"; +defparam \OUTPUT_E2~I .operation_mode = "output"; +defparam \OUTPUT_E2~I .output_async_reset = "none"; +defparam \OUTPUT_E2~I .output_power_up = "low"; +defparam \OUTPUT_E2~I .output_register_mode = "none"; +defparam \OUTPUT_E2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_F2~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_F2)); +// synopsys translate_off +defparam \OUTPUT_F2~I .input_async_reset = "none"; +defparam \OUTPUT_F2~I .input_power_up = "low"; +defparam \OUTPUT_F2~I .input_register_mode = "none"; +defparam \OUTPUT_F2~I .input_sync_reset = "none"; +defparam \OUTPUT_F2~I .oe_async_reset = "none"; +defparam \OUTPUT_F2~I .oe_power_up = "low"; +defparam \OUTPUT_F2~I .oe_register_mode = "none"; +defparam \OUTPUT_F2~I .oe_sync_reset = "none"; +defparam \OUTPUT_F2~I .operation_mode = "output"; +defparam \OUTPUT_F2~I .output_async_reset = "none"; +defparam \OUTPUT_F2~I .output_power_up = "low"; +defparam \OUTPUT_F2~I .output_register_mode = "none"; +defparam \OUTPUT_F2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \OUTPUT_G2~I ( + .datain(\inst1|16~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(OUTPUT_G2)); +// synopsys translate_off +defparam \OUTPUT_G2~I .input_async_reset = "none"; +defparam \OUTPUT_G2~I .input_power_up = "low"; +defparam \OUTPUT_G2~I .input_register_mode = "none"; +defparam \OUTPUT_G2~I .input_sync_reset = "none"; +defparam \OUTPUT_G2~I .oe_async_reset = "none"; +defparam \OUTPUT_G2~I .oe_power_up = "low"; +defparam \OUTPUT_G2~I .oe_register_mode = "none"; +defparam \OUTPUT_G2~I .oe_sync_reset = "none"; +defparam \OUTPUT_G2~I .operation_mode = "output"; +defparam \OUTPUT_G2~I .output_async_reset = "none"; +defparam \OUTPUT_G2~I .output_power_up = "low"; +defparam \OUTPUT_G2~I .output_register_mode = "none"; +defparam \OUTPUT_G2~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \overflow~I ( + .datain(\inst23|v~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(overflow)); +// synopsys translate_off +defparam \overflow~I .input_async_reset = "none"; +defparam \overflow~I .input_power_up = "low"; +defparam \overflow~I .input_register_mode = "none"; +defparam \overflow~I .input_sync_reset = "none"; +defparam \overflow~I .oe_async_reset = "none"; +defparam \overflow~I .oe_power_up = "low"; +defparam \overflow~I .oe_register_mode = "none"; +defparam \overflow~I .oe_sync_reset = "none"; +defparam \overflow~I .operation_mode = "output"; +defparam \overflow~I .output_async_reset = "none"; +defparam \overflow~I .output_power_up = "low"; +defparam \overflow~I .output_register_mode = "none"; +defparam \overflow~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \num~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(num)); +// synopsys translate_off +defparam \num~I .input_async_reset = "none"; +defparam \num~I .input_power_up = "low"; +defparam \num~I .input_register_mode = "none"; +defparam \num~I .input_sync_reset = "none"; +defparam \num~I .oe_async_reset = "none"; +defparam \num~I .oe_power_up = "low"; +defparam \num~I .oe_register_mode = "none"; +defparam \num~I .oe_sync_reset = "none"; +defparam \num~I .operation_mode = "output"; +defparam \num~I .output_async_reset = "none"; +defparam \num~I .output_power_up = "low"; +defparam \num~I .output_register_mode = "none"; +defparam \num~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/YL_adder/simulation/qsim/YL_adder.vt b/YL_adder/simulation/qsim/YL_adder.vt new file mode 100644 index 0000000..cc39001 --- /dev/null +++ b/YL_adder/simulation/qsim/YL_adder.vt @@ -0,0 +1,758 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "05/04/2020 16:45:13" + +// Verilog Self-Checking Test Bench (with test vectors) for design : YL_adder +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module YL_adder_vlg_sample_tst( + clk, + INPUT_A1, + INPUT_A2, + INPUT_A3, + INPUT_A4, + INPUT_B1, + INPUT_B2, + INPUT_B3, + INPUT_B4, + isAdd, + reset, + sampler_tx +); +input clk; +input INPUT_A1; +input INPUT_A2; +input INPUT_A3; +input INPUT_A4; +input INPUT_B1; +input INPUT_B2; +input INPUT_B3; +input INPUT_B4; +input isAdd; +input reset; +output sampler_tx; + +reg sample; +time current_time; +always @(clk or INPUT_A1 or INPUT_A2 or INPUT_A3 or INPUT_A4 or INPUT_B1 or INPUT_B2 or INPUT_B3 or INPUT_B4 or isAdd or reset) + +begin + if ($realtime > 0) + begin + if ($realtime == 0 || $realtime != current_time) + begin + if (sample === 1'bx) + sample = 0; + else + sample = ~sample; + end + current_time = $realtime; + end +end + +assign sampler_tx = sample; +endmodule + +module YL_adder_vlg_check_tst ( + num, + OUTPUT_A, + OUTPUT_A2, + OUTPUT_B, + OUTPUT_B2, + OUTPUT_C, + OUTPUT_C2, + OUTPUT_D, + OUTPUT_D2, + OUTPUT_E, + OUTPUT_E2, + OUTPUT_F, + OUTPUT_F2, + OUTPUT_G, + OUTPUT_G2, + overflow, + sampler_rx +); +input num; +input OUTPUT_A; +input OUTPUT_A2; +input OUTPUT_B; +input OUTPUT_B2; +input OUTPUT_C; +input OUTPUT_C2; +input OUTPUT_D; +input OUTPUT_D2; +input OUTPUT_E; +input OUTPUT_E2; +input OUTPUT_F; +input OUTPUT_F2; +input OUTPUT_G; +input OUTPUT_G2; +input overflow; +input sampler_rx; + +reg num_expected; +reg OUTPUT_A_expected; +reg OUTPUT_A2_expected; +reg OUTPUT_B_expected; +reg OUTPUT_B2_expected; +reg OUTPUT_C_expected; +reg OUTPUT_C2_expected; +reg OUTPUT_D_expected; +reg OUTPUT_D2_expected; +reg OUTPUT_E_expected; +reg OUTPUT_E2_expected; +reg OUTPUT_F_expected; +reg OUTPUT_F2_expected; +reg OUTPUT_G_expected; +reg OUTPUT_G2_expected; +reg overflow_expected; + +reg num_prev; +reg OUTPUT_A_prev; +reg OUTPUT_A2_prev; +reg OUTPUT_B_prev; +reg OUTPUT_B2_prev; +reg OUTPUT_C_prev; +reg OUTPUT_C2_prev; +reg OUTPUT_D_prev; +reg OUTPUT_D2_prev; +reg OUTPUT_E_prev; +reg OUTPUT_E2_prev; +reg OUTPUT_F_prev; +reg OUTPUT_F2_prev; +reg OUTPUT_G_prev; +reg OUTPUT_G2_prev; +reg overflow_prev; + +reg num_expected_prev; +reg OUTPUT_A_expected_prev; +reg OUTPUT_A2_expected_prev; +reg OUTPUT_B_expected_prev; +reg OUTPUT_B2_expected_prev; +reg OUTPUT_C_expected_prev; +reg OUTPUT_C2_expected_prev; +reg OUTPUT_D_expected_prev; +reg OUTPUT_D2_expected_prev; +reg OUTPUT_E_expected_prev; +reg OUTPUT_E2_expected_prev; +reg OUTPUT_F_expected_prev; +reg OUTPUT_F2_expected_prev; +reg OUTPUT_G_expected_prev; +reg OUTPUT_G2_expected_prev; +reg overflow_expected_prev; + +reg last_num_exp; +reg last_OUTPUT_A_exp; +reg last_OUTPUT_A2_exp; +reg last_OUTPUT_B_exp; +reg last_OUTPUT_B2_exp; +reg last_OUTPUT_C_exp; +reg last_OUTPUT_C2_exp; +reg last_OUTPUT_D_exp; +reg last_OUTPUT_D2_exp; +reg last_OUTPUT_E_exp; +reg last_OUTPUT_E2_exp; +reg last_OUTPUT_F_exp; +reg last_OUTPUT_F2_exp; +reg last_OUTPUT_G_exp; +reg last_OUTPUT_G2_exp; +reg last_overflow_exp; + +reg trigger; + +integer i; +integer nummismatches; + +reg [1:16] on_first_change ; + + +initial +begin +trigger = 0; +i = 0; +nummismatches = 0; +on_first_change = 16'b1; +end + +// update real /o prevs + +always @(trigger) +begin + num_prev = num; + OUTPUT_A_prev = OUTPUT_A; + OUTPUT_A2_prev = OUTPUT_A2; + OUTPUT_B_prev = OUTPUT_B; + OUTPUT_B2_prev = OUTPUT_B2; + OUTPUT_C_prev = OUTPUT_C; + OUTPUT_C2_prev = OUTPUT_C2; + OUTPUT_D_prev = OUTPUT_D; + OUTPUT_D2_prev = OUTPUT_D2; + OUTPUT_E_prev = OUTPUT_E; + OUTPUT_E2_prev = OUTPUT_E2; + OUTPUT_F_prev = OUTPUT_F; + OUTPUT_F2_prev = OUTPUT_F2; + OUTPUT_G_prev = OUTPUT_G; + OUTPUT_G2_prev = OUTPUT_G2; + overflow_prev = overflow; +end + +// update expected /o prevs + +always @(trigger) +begin + num_expected_prev = num_expected; + OUTPUT_A_expected_prev = OUTPUT_A_expected; + OUTPUT_A2_expected_prev = OUTPUT_A2_expected; + OUTPUT_B_expected_prev = OUTPUT_B_expected; + OUTPUT_B2_expected_prev = OUTPUT_B2_expected; + OUTPUT_C_expected_prev = OUTPUT_C_expected; + OUTPUT_C2_expected_prev = OUTPUT_C2_expected; + OUTPUT_D_expected_prev = OUTPUT_D_expected; + OUTPUT_D2_expected_prev = OUTPUT_D2_expected; + OUTPUT_E_expected_prev = OUTPUT_E_expected; + OUTPUT_E2_expected_prev = OUTPUT_E2_expected; + OUTPUT_F_expected_prev = OUTPUT_F_expected; + OUTPUT_F2_expected_prev = OUTPUT_F2_expected; + OUTPUT_G_expected_prev = OUTPUT_G_expected; + OUTPUT_G2_expected_prev = OUTPUT_G2_expected; + overflow_expected_prev = overflow_expected; +end + + + +// expected num +initial +begin + num_expected = 1'bX; +end + +// expected OUTPUT_A +initial +begin + OUTPUT_A_expected = 1'bX; +end + +// expected OUTPUT_A2 +initial +begin + OUTPUT_A2_expected = 1'bX; +end + +// expected OUTPUT_B +initial +begin + OUTPUT_B_expected = 1'bX; +end + +// expected OUTPUT_B2 +initial +begin + OUTPUT_B2_expected = 1'bX; +end + +// expected OUTPUT_C +initial +begin + OUTPUT_C_expected = 1'bX; +end + +// expected OUTPUT_C2 +initial +begin + OUTPUT_C2_expected = 1'bX; +end + +// expected OUTPUT_D +initial +begin + OUTPUT_D_expected = 1'bX; +end + +// expected OUTPUT_D2 +initial +begin + OUTPUT_D2_expected = 1'bX; +end + +// expected OUTPUT_E +initial +begin + OUTPUT_E_expected = 1'bX; +end + +// expected OUTPUT_E2 +initial +begin + OUTPUT_E2_expected = 1'bX; +end + +// expected OUTPUT_F +initial +begin + OUTPUT_F_expected = 1'bX; +end + +// expected OUTPUT_F2 +initial +begin + OUTPUT_F2_expected = 1'bX; +end + +// expected OUTPUT_G +initial +begin + OUTPUT_G_expected = 1'bX; +end + +// expected OUTPUT_G2 +initial +begin + OUTPUT_G2_expected = 1'bX; +end + +// expected overflow +initial +begin + overflow_expected = 1'bX; +end +// generate trigger +always @(num_expected or num or OUTPUT_A_expected or OUTPUT_A or OUTPUT_A2_expected or OUTPUT_A2 or OUTPUT_B_expected or OUTPUT_B or OUTPUT_B2_expected or OUTPUT_B2 or OUTPUT_C_expected or OUTPUT_C or OUTPUT_C2_expected or OUTPUT_C2 or OUTPUT_D_expected or OUTPUT_D or OUTPUT_D2_expected or OUTPUT_D2 or OUTPUT_E_expected or OUTPUT_E or OUTPUT_E2_expected or OUTPUT_E2 or OUTPUT_F_expected or OUTPUT_F or OUTPUT_F2_expected or OUTPUT_F2 or OUTPUT_G_expected or OUTPUT_G or OUTPUT_G2_expected or OUTPUT_G2 or overflow_expected or overflow) +begin + trigger <= ~trigger; +end + +always @(posedge sampler_rx or negedge sampler_rx) +begin +`ifdef debug_tbench + $display("Scanning pattern %d @time = %t",i,$realtime ); + i = i + 1; + $display("| expected num = %b | expected OUTPUT_A = %b | expected OUTPUT_A2 = %b | expected OUTPUT_B = %b | expected OUTPUT_B2 = %b | expected OUTPUT_C = %b | expected OUTPUT_C2 = %b | expected OUTPUT_D = %b | expected OUTPUT_D2 = %b | expected OUTPUT_E = %b | expected OUTPUT_E2 = %b | expected OUTPUT_F = %b | expected OUTPUT_F2 = %b | expected OUTPUT_G = %b | expected OUTPUT_G2 = %b | expected overflow = %b | ",num_expected_prev,OUTPUT_A_expected_prev,OUTPUT_A2_expected_prev,OUTPUT_B_expected_prev,OUTPUT_B2_expected_prev,OUTPUT_C_expected_prev,OUTPUT_C2_expected_prev,OUTPUT_D_expected_prev,OUTPUT_D2_expected_prev,OUTPUT_E_expected_prev,OUTPUT_E2_expected_prev,OUTPUT_F_expected_prev,OUTPUT_F2_expected_prev,OUTPUT_G_expected_prev,OUTPUT_G2_expected_prev,overflow_expected_prev); + $display("| real num = %b | real OUTPUT_A = %b | real OUTPUT_A2 = %b | real OUTPUT_B = %b | real OUTPUT_B2 = %b | real OUTPUT_C = %b | real OUTPUT_C2 = %b | real OUTPUT_D = %b | real OUTPUT_D2 = %b | real OUTPUT_E = %b | real OUTPUT_E2 = %b | real OUTPUT_F = %b | real OUTPUT_F2 = %b | real OUTPUT_G = %b | real OUTPUT_G2 = %b | real overflow = %b | ",num_prev,OUTPUT_A_prev,OUTPUT_A2_prev,OUTPUT_B_prev,OUTPUT_B2_prev,OUTPUT_C_prev,OUTPUT_C2_prev,OUTPUT_D_prev,OUTPUT_D2_prev,OUTPUT_E_prev,OUTPUT_E2_prev,OUTPUT_F_prev,OUTPUT_F2_prev,OUTPUT_G_prev,OUTPUT_G2_prev,overflow_prev); +`endif + if ( + ( num_expected_prev !== 1'bx ) && ( num_prev !== num_expected_prev ) + && ((num_expected_prev !== last_num_exp) || + on_first_change[1]) + ) + begin + $display ("ERROR! Vector Mismatch for output port num :: @time = %t", $realtime); + $display (" Expected value = %b", num_expected_prev); + $display (" Real value = %b", num_prev); + nummismatches = nummismatches + 1; + on_first_change[1] = 1'b0; + last_num_exp = num_expected_prev; + end + if ( + ( OUTPUT_A_expected_prev !== 1'bx ) && ( OUTPUT_A_prev !== OUTPUT_A_expected_prev ) + && ((OUTPUT_A_expected_prev !== last_OUTPUT_A_exp) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_A :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_A_expected_prev); + $display (" Real value = %b", OUTPUT_A_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_OUTPUT_A_exp = OUTPUT_A_expected_prev; + end + if ( + ( OUTPUT_A2_expected_prev !== 1'bx ) && ( OUTPUT_A2_prev !== OUTPUT_A2_expected_prev ) + && ((OUTPUT_A2_expected_prev !== last_OUTPUT_A2_exp) || + on_first_change[3]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_A2 :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_A2_expected_prev); + $display (" Real value = %b", OUTPUT_A2_prev); + nummismatches = nummismatches + 1; + on_first_change[3] = 1'b0; + last_OUTPUT_A2_exp = OUTPUT_A2_expected_prev; + end + if ( + ( OUTPUT_B_expected_prev !== 1'bx ) && ( OUTPUT_B_prev !== OUTPUT_B_expected_prev ) + && ((OUTPUT_B_expected_prev !== last_OUTPUT_B_exp) || + on_first_change[4]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_B :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_B_expected_prev); + $display (" Real value = %b", OUTPUT_B_prev); + nummismatches = nummismatches + 1; + on_first_change[4] = 1'b0; + last_OUTPUT_B_exp = OUTPUT_B_expected_prev; + end + if ( + ( OUTPUT_B2_expected_prev !== 1'bx ) && ( OUTPUT_B2_prev !== OUTPUT_B2_expected_prev ) + && ((OUTPUT_B2_expected_prev !== last_OUTPUT_B2_exp) || + on_first_change[5]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_B2 :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_B2_expected_prev); + $display (" Real value = %b", OUTPUT_B2_prev); + nummismatches = nummismatches + 1; + on_first_change[5] = 1'b0; + last_OUTPUT_B2_exp = OUTPUT_B2_expected_prev; + end + if ( + ( OUTPUT_C_expected_prev !== 1'bx ) && ( OUTPUT_C_prev !== OUTPUT_C_expected_prev ) + && ((OUTPUT_C_expected_prev !== last_OUTPUT_C_exp) || + on_first_change[6]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_C :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_C_expected_prev); + $display (" Real value = %b", OUTPUT_C_prev); + nummismatches = nummismatches + 1; + on_first_change[6] = 1'b0; + last_OUTPUT_C_exp = OUTPUT_C_expected_prev; + end + if ( + ( OUTPUT_C2_expected_prev !== 1'bx ) && ( OUTPUT_C2_prev !== OUTPUT_C2_expected_prev ) + && ((OUTPUT_C2_expected_prev !== last_OUTPUT_C2_exp) || + on_first_change[7]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_C2 :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_C2_expected_prev); + $display (" Real value = %b", OUTPUT_C2_prev); + nummismatches = nummismatches + 1; + on_first_change[7] = 1'b0; + last_OUTPUT_C2_exp = OUTPUT_C2_expected_prev; + end + if ( + ( OUTPUT_D_expected_prev !== 1'bx ) && ( OUTPUT_D_prev !== OUTPUT_D_expected_prev ) + && ((OUTPUT_D_expected_prev !== last_OUTPUT_D_exp) || + on_first_change[8]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_D :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_D_expected_prev); + $display (" Real value = %b", OUTPUT_D_prev); + nummismatches = nummismatches + 1; + on_first_change[8] = 1'b0; + last_OUTPUT_D_exp = OUTPUT_D_expected_prev; + end + if ( + ( OUTPUT_D2_expected_prev !== 1'bx ) && ( OUTPUT_D2_prev !== OUTPUT_D2_expected_prev ) + && ((OUTPUT_D2_expected_prev !== last_OUTPUT_D2_exp) || + on_first_change[9]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_D2 :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_D2_expected_prev); + $display (" Real value = %b", OUTPUT_D2_prev); + nummismatches = nummismatches + 1; + on_first_change[9] = 1'b0; + last_OUTPUT_D2_exp = OUTPUT_D2_expected_prev; + end + if ( + ( OUTPUT_E_expected_prev !== 1'bx ) && ( OUTPUT_E_prev !== OUTPUT_E_expected_prev ) + && ((OUTPUT_E_expected_prev !== last_OUTPUT_E_exp) || + on_first_change[10]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_E :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_E_expected_prev); + $display (" Real value = %b", OUTPUT_E_prev); + nummismatches = nummismatches + 1; + on_first_change[10] = 1'b0; + last_OUTPUT_E_exp = OUTPUT_E_expected_prev; + end + if ( + ( OUTPUT_E2_expected_prev !== 1'bx ) && ( OUTPUT_E2_prev !== OUTPUT_E2_expected_prev ) + && ((OUTPUT_E2_expected_prev !== last_OUTPUT_E2_exp) || + on_first_change[11]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_E2 :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_E2_expected_prev); + $display (" Real value = %b", OUTPUT_E2_prev); + nummismatches = nummismatches + 1; + on_first_change[11] = 1'b0; + last_OUTPUT_E2_exp = OUTPUT_E2_expected_prev; + end + if ( + ( OUTPUT_F_expected_prev !== 1'bx ) && ( OUTPUT_F_prev !== OUTPUT_F_expected_prev ) + && ((OUTPUT_F_expected_prev !== last_OUTPUT_F_exp) || + on_first_change[12]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_F :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_F_expected_prev); + $display (" Real value = %b", OUTPUT_F_prev); + nummismatches = nummismatches + 1; + on_first_change[12] = 1'b0; + last_OUTPUT_F_exp = OUTPUT_F_expected_prev; + end + if ( + ( OUTPUT_F2_expected_prev !== 1'bx ) && ( OUTPUT_F2_prev !== OUTPUT_F2_expected_prev ) + && ((OUTPUT_F2_expected_prev !== last_OUTPUT_F2_exp) || + on_first_change[13]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_F2 :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_F2_expected_prev); + $display (" Real value = %b", OUTPUT_F2_prev); + nummismatches = nummismatches + 1; + on_first_change[13] = 1'b0; + last_OUTPUT_F2_exp = OUTPUT_F2_expected_prev; + end + if ( + ( OUTPUT_G_expected_prev !== 1'bx ) && ( OUTPUT_G_prev !== OUTPUT_G_expected_prev ) + && ((OUTPUT_G_expected_prev !== last_OUTPUT_G_exp) || + on_first_change[14]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_G :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_G_expected_prev); + $display (" Real value = %b", OUTPUT_G_prev); + nummismatches = nummismatches + 1; + on_first_change[14] = 1'b0; + last_OUTPUT_G_exp = OUTPUT_G_expected_prev; + end + if ( + ( OUTPUT_G2_expected_prev !== 1'bx ) && ( OUTPUT_G2_prev !== OUTPUT_G2_expected_prev ) + && ((OUTPUT_G2_expected_prev !== last_OUTPUT_G2_exp) || + on_first_change[15]) + ) + begin + $display ("ERROR! Vector Mismatch for output port OUTPUT_G2 :: @time = %t", $realtime); + $display (" Expected value = %b", OUTPUT_G2_expected_prev); + $display (" Real value = %b", OUTPUT_G2_prev); + nummismatches = nummismatches + 1; + on_first_change[15] = 1'b0; + last_OUTPUT_G2_exp = OUTPUT_G2_expected_prev; + end + if ( + ( overflow_expected_prev !== 1'bx ) && ( overflow_prev !== overflow_expected_prev ) + && ((overflow_expected_prev !== last_overflow_exp) || + on_first_change[16]) + ) + begin + $display ("ERROR! Vector Mismatch for output port overflow :: @time = %t", $realtime); + $display (" Expected value = %b", overflow_expected_prev); + $display (" Real value = %b", overflow_prev); + nummismatches = nummismatches + 1; + on_first_change[16] = 1'b0; + last_overflow_exp = overflow_expected_prev; + end + + trigger <= ~trigger; +end +initial + +begin +$timeformat(-12,3," ps",6); +#1000000; +if (nummismatches > 0) + $display ("%d mismatched vectors : Simulation failed !",nummismatches); +else + $display ("Simulation passed !"); +$finish; +end +endmodule + +module YL_adder_vlg_vec_tst(); +// constants +// general purpose registers +reg clk; +reg INPUT_A1; +reg INPUT_A2; +reg INPUT_A3; +reg INPUT_A4; +reg INPUT_B1; +reg INPUT_B2; +reg INPUT_B3; +reg INPUT_B4; +reg isAdd; +reg reset; +// wires +wire num; +wire OUTPUT_A; +wire OUTPUT_A2; +wire OUTPUT_B; +wire OUTPUT_B2; +wire OUTPUT_C; +wire OUTPUT_C2; +wire OUTPUT_D; +wire OUTPUT_D2; +wire OUTPUT_E; +wire OUTPUT_E2; +wire OUTPUT_F; +wire OUTPUT_F2; +wire OUTPUT_G; +wire OUTPUT_G2; +wire overflow; + +wire sampler; + +// assign statements (if any) +YL_adder i1 ( +// port map - connection between master ports and signals/registers + .clk(clk), + .INPUT_A1(INPUT_A1), + .INPUT_A2(INPUT_A2), + .INPUT_A3(INPUT_A3), + .INPUT_A4(INPUT_A4), + .INPUT_B1(INPUT_B1), + .INPUT_B2(INPUT_B2), + .INPUT_B3(INPUT_B3), + .INPUT_B4(INPUT_B4), + .isAdd(isAdd), + .num(num), + .OUTPUT_A(OUTPUT_A), + .OUTPUT_A2(OUTPUT_A2), + .OUTPUT_B(OUTPUT_B), + .OUTPUT_B2(OUTPUT_B2), + .OUTPUT_C(OUTPUT_C), + .OUTPUT_C2(OUTPUT_C2), + .OUTPUT_D(OUTPUT_D), + .OUTPUT_D2(OUTPUT_D2), + .OUTPUT_E(OUTPUT_E), + .OUTPUT_E2(OUTPUT_E2), + .OUTPUT_F(OUTPUT_F), + .OUTPUT_F2(OUTPUT_F2), + .OUTPUT_G(OUTPUT_G), + .OUTPUT_G2(OUTPUT_G2), + .overflow(overflow), + .reset(reset) +); + +// clk +always +begin + clk = 1'b0; + clk = #10000 1'b1; + #10000; +end + +// reset +initial +begin + reset = 1'b0; +end + +// isAdd +initial +begin + isAdd = 1'b0; +end + +// INPUT_A1 +initial +begin + INPUT_A1 = 1'b0; + INPUT_A1 = #400000 1'b1; + INPUT_A1 = #400000 1'b0; +end + +// INPUT_A2 +initial +begin + repeat(2) + begin + INPUT_A2 = 1'b0; + INPUT_A2 = #200000 1'b1; + # 200000; + end + INPUT_A2 = 1'b0; +end + +// INPUT_A3 +always +begin + INPUT_A3 = 1'b0; + INPUT_A3 = #100000 1'b1; + #100000; +end + +// INPUT_A4 +always +begin + INPUT_A4 = 1'b0; + INPUT_A4 = #50000 1'b1; + #50000; +end + +// INPUT_B1 +initial +begin + INPUT_B1 = 1'b0; +end + +// INPUT_B2 +initial +begin + INPUT_B2 = 1'b0; +end + +// INPUT_B3 +initial +begin + INPUT_B3 = 1'b0; +end + +// INPUT_B4 +initial +begin + INPUT_B4 = 1'b0; +end + +YL_adder_vlg_sample_tst tb_sample ( + .clk(clk), + .INPUT_A1(INPUT_A1), + .INPUT_A2(INPUT_A2), + .INPUT_A3(INPUT_A3), + .INPUT_A4(INPUT_A4), + .INPUT_B1(INPUT_B1), + .INPUT_B2(INPUT_B2), + .INPUT_B3(INPUT_B3), + .INPUT_B4(INPUT_B4), + .isAdd(isAdd), + .reset(reset), + .sampler_tx(sampler) +); + +YL_adder_vlg_check_tst tb_out( + .num(num), + .OUTPUT_A(OUTPUT_A), + .OUTPUT_A2(OUTPUT_A2), + .OUTPUT_B(OUTPUT_B), + .OUTPUT_B2(OUTPUT_B2), + .OUTPUT_C(OUTPUT_C), + .OUTPUT_C2(OUTPUT_C2), + .OUTPUT_D(OUTPUT_D), + .OUTPUT_D2(OUTPUT_D2), + .OUTPUT_E(OUTPUT_E), + .OUTPUT_E2(OUTPUT_E2), + .OUTPUT_F(OUTPUT_F), + .OUTPUT_F2(OUTPUT_F2), + .OUTPUT_G(OUTPUT_G), + .OUTPUT_G2(OUTPUT_G2), + .overflow(overflow), + .sampler_rx(sampler) +); +endmodule + diff --git a/YL_adder/simulation/qsim/YL_adder_v.sdo b/YL_adder/simulation/qsim/YL_adder_v.sdo new file mode 100644 index 0000000..3ef5b4b --- /dev/null +++ b/YL_adder/simulation/qsim/YL_adder_v.sdo @@ -0,0 +1,690 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "YL_adder") + (DATE "05/04/2020 16:45:16") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|51\~0) + (DELAY + (ABSOLUTE + (PORT dataa (5284:5284:5284) (5284:5284:5284)) + (PORT datac (5244:5244:5244) (5244:5244:5244)) + (PORT datad (5258:5258:5258) (5258:5258:5258)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE clk\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE clk\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (238:238:238) (238:238:238)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE clk\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (279:279:279) (279:279:279)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (239:239:239) (239:239:239)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (55:55:55)) + (HOLD d (posedge clk) (110:110:110)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (843:843:843) (843:843:843)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B1\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (853:853:853) (853:853:853)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|42) + (DELAY + (ABSOLUTE + (PORT datac (5243:5243:5243) (5243:5243:5243)) + (PORT datad (5259:5259:5259) (5259:5259:5259)) + (IOPATH datac combout (319:319:319) (319:319:319)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE reset\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (232:232:232) (232:232:232)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE reset\~clkctrl.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (279:279:279) (279:279:279)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (239:239:239) (239:239:239)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (55:55:55)) + (HOLD d (posedge clk) (110:110:110)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|1) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (843:843:843) (843:843:843)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE isAdd\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (853:853:853) (853:853:853)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst21\|o4\~2) + (DELAY + (ABSOLUTE + (PORT datab (5232:5232:5232) (5232:5232:5232)) + (PORT datac (5272:5272:5272) (5272:5272:5272)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (843:843:843) (843:843:843)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B3\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (873:873:873) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (5286:5286:5286) (5286:5286:5286)) + (PORT datac (5577:5577:5577) (5577:5577:5577)) + (PORT datad (5519:5519:5519) (5519:5519:5519)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (843:843:843) (843:843:843)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|25) + (DELAY + (ABSOLUTE + (PORT dataa (5287:5287:5287) (5287:5287:5287)) + (PORT datac (5577:5577:5577) (5577:5577:5577)) + (PORT datad (5519:5519:5519) (5519:5519:5519)) + (IOPATH dataa combout (513:513:513) (513:513:513)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (863:863:863) (863:863:863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst21\|o2\~2) + (DELAY + (ABSOLUTE + (PORT datab (5228:5228:5228) (5228:5228:5228)) + (PORT datac (5270:5270:5270) (5270:5270:5270)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (325:325:325)) + (PORT datab (5547:5547:5547) (5547:5547:5547)) + (PORT datac (524:524:524) (524:524:524)) + (PORT datad (301:301:301) (301:301:301)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (483:483:483) (483:483:483)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|45) + (DELAY + (ABSOLUTE + (PORT dataa (5246:5246:5246) (5246:5246:5246)) + (PORT datab (306:306:306) (306:306:306)) + (PORT datac (303:303:303) (303:303:303)) + (PORT datad (311:311:311) (311:311:311)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|16) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (5284:5284:5284) (5284:5284:5284)) + (PORT datac (5571:5571:5571) (5571:5571:5571)) + (PORT datad (5518:5518:5518) (5518:5518:5518)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|44) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (325:325:325)) + (PORT datab (298:298:298) (298:298:298)) + (PORT datac (5533:5533:5533) (5533:5533:5533)) + (PORT datad (303:303:303) (303:303:303)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|15) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (5284:5284:5284) (5284:5284:5284)) + (PORT datab (5232:5232:5232) (5232:5232:5232)) + (PORT datac (5245:5245:5245) (5245:5245:5245)) + (PORT datad (5255:5255:5255) (5255:5255:5255)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst\|43) + (DELAY + (ABSOLUTE + (PORT datab (5543:5543:5543) (5543:5543:5543)) + (PORT datac (294:294:294) (294:294:294)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE inst1\|8) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1605:1605:1605)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1609:1609:1609) (1609:1609:1609)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|a\~12) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (670:670:670)) + (PORT datab (643:643:643) (643:643:643)) + (PORT datac (905:905:905) (905:905:905)) + (PORT datad (599:599:599) (599:599:599)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|b\~3) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (662:662:662)) + (PORT datab (652:652:652) (652:652:652)) + (PORT datac (911:911:911) (911:911:911)) + (PORT datad (600:600:600) (600:600:600)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (483:483:483) (483:483:483)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|c\~1) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (668:668:668)) + (PORT datab (648:648:648) (648:648:648)) + (PORT datac (908:908:908) (908:908:908)) + (PORT datad (596:596:596) (596:596:596)) + (IOPATH dataa combout (449:449:449) (449:449:449)) + (IOPATH datab combout (485:485:485) (485:485:485)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (663:663:663)) + (PORT datab (633:633:633) (633:633:633)) + (PORT datad (599:599:599) (599:599:599)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|e\~0) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (662:662:662)) + (PORT datab (634:634:634) (634:634:634)) + (PORT datad (600:600:600) (600:600:600)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|f\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (669:669:669)) + (PORT datab (644:644:644) (644:644:644)) + (PORT datac (905:905:905) (905:905:905)) + (PORT datad (598:598:598) (598:598:598)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst17\|g\~0) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (665:665:665)) + (PORT datab (650:650:650) (650:650:650)) + (PORT datac (910:910:910) (910:910:910)) + (PORT datad (597:597:597) (597:597:597)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE INPUT_A4\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (863:863:863) (863:863:863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE inst23\|v\~1) + (DELAY + (ABSOLUTE + (PORT dataa (5248:5248:5248) (5248:5248:5248)) + (PORT datab (305:305:305) (305:305:305)) + (PORT datac (302:302:302) (302:302:302)) + (PORT datad (309:309:309) (309:309:309)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (516:516:516) (516:516:516)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (985:985:985) (985:985:985)) + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1039:1039:1039) (1039:1039:1039)) + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (678:678:678) (678:678:678)) + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1347:1347:1347) (1347:1347:1347)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1040:1040:1040) (1040:1040:1040)) + (IOPATH datain padio (2976:2976:2976) (2976:2976:2976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (976:976:976) (976:976:976)) + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1345:1345:1345) (1345:1345:1345)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_A2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_B2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_C2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_D2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2976:2976:2976) (2976:2976:2976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_E2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_F2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE OUTPUT_G2\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1014:1014:1014) (1014:1014:1014)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE overflow\~I.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (948:948:948) (948:948:948)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE num\~I.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3006:3006:3006) (3006:3006:3006)) + ) + ) + ) +) diff --git a/YL_dec_counter/YL_DecCounter.vwf b/YL_dec_counter/YL_DecCounter.vwf new file mode 100644 index 0000000..a053005 --- /dev/null +++ b/YL_dec_counter/YL_DecCounter.vwf @@ -0,0 +1,327 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clock") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("enc") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("rco") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 860.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 100.0; + } +} + +TRANSITION_LIST("clock") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 20; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("enc") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 240.0; + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 460.0; + } +} + +TRANSITION_LIST("rco") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clock"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "enc"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rco"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "value"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; + CHILDREN = 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "value[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 5; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_dec_counter/YL_DecCounter.vwf.temp b/YL_dec_counter/YL_DecCounter.vwf.temp new file mode 100644 index 0000000..fffa304 --- /dev/null +++ b/YL_dec_counter/YL_DecCounter.vwf.temp @@ -0,0 +1,326 @@ +/* Simulator = Quartus II Simulator */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clock") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("enc") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("rco") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 320.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 400.0; + } +} + +TRANSITION_LIST("clock") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 20; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("enc") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 240.0; + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("rco") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clock"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "enc"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rco"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "value"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; + CHILDREN = 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "value[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 5; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_dec_counter/YL_dec_counter.bdf b/YL_dec_counter/YL_dec_counter.bdf new file mode 100644 index 0000000..02aa4c5 --- /dev/null +++ b/YL_dec_counter/YL_dec_counter.bdf @@ -0,0 +1,101 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 40 112 208 128) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "enc" (rect 5 0 22 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 40 128 208 144) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "ent" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 40 144 208 160) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clock" (rect 5 0 30 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 40 160 208 176) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clear" (rect 5 0 28 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(connector + (pt 208 120) + (pt 232 120) +) +(connector + (pt 208 136) + (pt 232 136) +) +(connector + (pt 208 152) + (pt 232 152) +) +(connector + (pt 208 168) + (pt 232 168) +) diff --git a/YL_dec_counter/YL_dec_counter.qpf b/YL_dec_counter/YL_dec_counter.qpf new file mode 100644 index 0000000..c349e2a --- /dev/null +++ b/YL_dec_counter/YL_dec_counter.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 18:36:09 May 03, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "18:36:09 May 03, 2020" + +# Revisions + +PROJECT_REVISION = "YL_dec_counter" diff --git a/YL_dec_counter/YL_dec_counter.qsf b/YL_dec_counter/YL_dec_counter.qsf new file mode 100644 index 0000000..c2547ea --- /dev/null +++ b/YL_dec_counter/YL_dec_counter.qsf @@ -0,0 +1,64 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 18:36:09 May 03, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# YL_dec_counter_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY YL_dec_counter +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:36:09 MAY 03, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name BDF_FILE YL_dec_counter.bdf +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name AHDL_FILE YL_dec_counter.tdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_DecCounter.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SIMULATION_MODE FUNCTIONAL +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation +set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE 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zc2g+$fuNG?)aGzF?bzbHY>)9N8RCR@NS;(rWN?Bt^d@>#3R(As=b~kvS zJ+6BbA}QJoSPgVmZZbA_F7 literal 0 HcmV?d00001 diff --git a/YL_pulsar/db/YL_pulsar.db_info b/YL_pulsar/db/YL_pulsar.db_info new file mode 100644 index 0000000..1e870f3 --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Mon May 04 09:42:20 2020 diff --git a/YL_pulsar/db/YL_pulsar.eda.qmsg b/YL_pulsar/db/YL_pulsar.eda.qmsg new file mode 100644 index 0000000..b4d8018 --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588559815461 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588559815462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 10:36:55 2020 " "Processing started: Mon May 04 10:36:55 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588559815462 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588559815462 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off YL_pulsar -c YL_pulsar " "Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_pulsar -c YL_pulsar" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588559815462 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "YL_pulsar.vo C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/simulation/modelsim/ simulation " "Generated file YL_pulsar.vo in folder \"C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1588559816022 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4529 " "Peak virtual memory: 4529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588559816071 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 10:36:56 2020 " "Processing ended: Mon May 04 10:36:56 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588559816071 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588559816071 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588559816071 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588559816071 ""} diff --git a/YL_pulsar/db/YL_pulsar.eds_overflow b/YL_pulsar/db/YL_pulsar.eds_overflow new file mode 100644 index 0000000..8d9f781 --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.eds_overflow @@ -0,0 +1 @@ +118 \ No newline at end of file diff --git a/YL_pulsar/db/YL_pulsar.fit.qmsg b/YL_pulsar/db/YL_pulsar.fit.qmsg new file mode 100644 index 0000000..be09c5f --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.fit.qmsg @@ -0,0 +1,46 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1588559802374 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "YL_pulsar EP2C20F484C7 " "Selected device EP2C20F484C7 for design \"YL_pulsar\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1588559802383 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588559802435 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588559802436 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1588559802547 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1588559802562 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Device EP2C15AF484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588559803307 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Device EP2C35F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588559803307 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Device EP2C50F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588559803307 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1588559803307 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 22 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588559803309 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 23 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588559803309 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 24 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588559803309 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1588559803309 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 4 " "No exact pin location assignment(s) for 4 pins of 4 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "output " "Pin output not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { output } } } { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 120 464 640 136 "output" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 4 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588559803397 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "key " "Pin key not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { key } } } { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 184 80 248 200 "key" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 7 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588559803397 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 120 168 336 136 "clk" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 5 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588559803397 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "reset " "Pin reset not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { reset } } } { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 136 168 336 152 "reset" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 6 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588559803397 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1588559803397 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_pulsar.sdc " "Synopsys Design Constraints File file not found: 'YL_pulsar.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1588559803540 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1588559803541 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1588559803545 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588559803582 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 120 168 336 136 "clk" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 5 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588559803582 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) " "Automatically promoted node reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588559803582 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { reset } } } { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 136 168 336 152 "reset" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 0 { 0 ""} 0 6 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588559803582 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1588559803666 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588559803667 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588559803668 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588559803669 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588559803669 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1588559803670 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1588559803670 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1588559803670 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1588559803678 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1588559803679 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1588559803679 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.3V 1 1 0 " "Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 1 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1588559803681 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1588559803681 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1588559803681 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 39 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 31 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 39 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 35 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588559803682 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1588559803682 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1588559803682 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588559803689 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1588559805630 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588559805722 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1588559805738 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1588559806164 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588559806165 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1588559806246 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X12_Y0 X24_Y13 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X12_Y0 to location X24_Y13" { } { { "loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X12_Y0 to location X24_Y13"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X12_Y0 to location X24_Y13"} 12 0 13 14 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1588559807069 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1588559807069 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588559807374 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1588559807377 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1588559807377 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1588559807386 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588559807390 ""} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "output 0 " "Pin \"output\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588559807392 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1588559807392 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588559807505 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588559807514 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588559807660 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588559807965 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1588559808076 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.fit.smsg " "Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1588559808175 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4844 " "Peak virtual memory: 4844 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588559808485 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 10:36:48 2020 " "Processing ended: Mon May 04 10:36:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588559808485 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588559808485 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588559808485 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1588559808485 ""} diff --git a/YL_pulsar/db/YL_pulsar.fnsim.cdb b/YL_pulsar/db/YL_pulsar.fnsim.cdb new file mode 100644 index 0000000000000000000000000000000000000000..599f54378aeda552d8b5cf468ab4426f11377a24 GIT binary patch literal 3138 zcmeH}`#TegAIIepm5fq$atS9V3UkfMt&U7M=91V%?#yf`cgrZ9QyoMozBq=t#^%zD zB3sHWOBkEWtR2TK=Du8JY+vVl{)+GOoX_WZKCd4>&*%Na`+5KHIUyz{MwC8uFryCI z>VWP+kx|Hqa5V!XkUq#j%_;_o4pcKVGE~zy(K9gAGt@UQQgaQ8j70_nsX6-vpwtZ1 zTlRNwmt&ac0_(Mwtb{Q%VxyQ6%Lz0}D+!2K% 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No`uJICi_qA_#aIdkE;Lx literal 0 HcmV?d00001 diff --git a/YL_pulsar/db/YL_pulsar.fnsim.qmsg b/YL_pulsar/db/YL_pulsar.fnsim.qmsg new file mode 100644 index 0000000..67f5b13 --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.fnsim.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588561900618 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II 64-Bit " "Running Quartus II 64-Bit Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588561900619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 11:11:40 2020 " "Processing started: Mon May 04 11:11:40 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588561900619 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588561900619 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map YL_pulsar -c YL_pulsar --generate_functional_sim_netlist " "Command: quartus_map YL_pulsar -c YL_pulsar --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588561900620 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588561901575 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_pulsar.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_pulsar.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 pulsar " "Found entity 1: pulsar" { } { { "YL_pulsar.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588561901730 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588561901730 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_pulsar.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_pulsar.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_pulsar " "Found entity 1: YL_pulsar" { } { { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588561901740 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588561901740 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_pulsar " "Elaborating entity \"YL_pulsar\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588561901819 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulsar pulsar:inst " "Elaborating entity \"pulsar\" for hierarchy \"pulsar:inst\"" { } { { "YL_pulsar.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 96 336 464 208 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588561901825 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4578 " "Peak virtual memory: 4578 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588561901989 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 11:11:41 2020 " "Processing ended: Mon May 04 11:11:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588561901989 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588561901989 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588561901989 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588561901989 ""} diff --git a/YL_pulsar/db/YL_pulsar.hier_info b/YL_pulsar/db/YL_pulsar.hier_info new file mode 100644 index 0000000..fe9f984 --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.hier_info @@ -0,0 +1,21 @@ +|YL_pulsar +output <= pulsar:inst.o +clk => pulsar:inst.clk +reset => pulsar:inst.reset +key => inst99.IN0 + + +|YL_pulsar|pulsar:inst +clk => ss~0.IN1 +reset => ss~2.IN1 +key => _~6.IN0 +key => _~8.IN1 +key => _~9.IN0 +key => _~11.IN1 +key => _~12.IN0 +key => _~14.IN1 +key => _~15.IN0 +key => _~17.IN1 +o <= ss$o.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/YL_pulsar/db/YL_pulsar.hif b/YL_pulsar/db/YL_pulsar.hif new file mode 100644 index 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zr8ZU?N4*h&-YW^5SEfU6hO@|Y^Co0E^iVmAOt&YKsctD>>RD3uJ7#e82OLc&W0|H% A-v9sr literal 0 HcmV?d00001 diff --git a/YL_pulsar/db/YL_pulsar.map.logdb b/YL_pulsar/db/YL_pulsar.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/YL_pulsar/db/YL_pulsar.map.qmsg b/YL_pulsar/db/YL_pulsar.map.qmsg new file mode 100644 index 0000000..c485394 --- /dev/null +++ b/YL_pulsar/db/YL_pulsar.map.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588559798091 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588559798092 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 10:36:37 2020 " "Processing started: Mon May 04 10:36:37 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588559798092 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588559798092 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_pulsar -c YL_pulsar " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_pulsar -c YL_pulsar" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588559798092 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588559798726 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_pulsar.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_pulsar.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 pulsar " "Found entity 1: pulsar" { } { { "YL_pulsar.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588559798804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588559798804 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_pulsar.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_pulsar.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_pulsar " "Found entity 1: YL_pulsar" { } { { "YL_pulsar.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588559798812 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588559798812 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_pulsar " "Elaborating entity \"YL_pulsar\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588559798938 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulsar pulsar:inst " "Elaborating entity \"pulsar\" for hierarchy \"pulsar:inst\"" { } { { "YL_pulsar.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf" { { 96 336 464 208 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588559798952 ""} +{ "Warning" "WSMP_SMP_MACHINE_NON_UNIQUE_CODE_WARN" "\|YL_pulsar\|pulsar:inst\|s0 \|YL_pulsar\|pulsar:inst\|s1 " "State bit assignments are not unique for state \"\|YL_pulsar\|pulsar:inst\|s0\" and state \"\|YL_pulsar\|pulsar:inst\|s1\"" { } { { "YL_pulsar.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.tdf" 7 2 0 } } } 0 284004 "State bit assignments are not unique for state \"%1!s!\" and state \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588559799239 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1588559799608 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1588559799833 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588559799833 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1588559799946 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1588559799946 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1588559799946 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1588559799946 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4604 " "Peak virtual memory: 4604 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588559800038 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 10:36:40 2020 " "Processing ended: Mon May 04 10:36:40 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588559800038 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588559800038 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588559800038 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588559800038 ""} diff --git a/YL_pulsar/db/YL_pulsar.map.rdb b/YL_pulsar/db/YL_pulsar.map.rdb new file mode 100644 index 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"IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II 64-Bit " "Running Quartus II 64-Bit Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588562406104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 11:20:05 2020 " "Processing started: Mon May 04 11:20:05 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588562406104 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588562406104 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --simulation_results_format=VWF YL_pulsar -c YL_pulsar " "Command: quartus_sim --simulation_results_format=VWF YL_pulsar -c YL_pulsar" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588562406105 ""} +{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.vwf " "Using vector source file \"C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.vwf\"" { } { } 0 324025 "Using vector source file \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588562406504 ""} +{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|YL_pulsar\|pulsar:inst\|s3 " "Can't display state machine states -- register holding state machine bit \"\|YL_pulsar\|pulsar:inst\|s3\" was synthesized away" { } { } 0 328028 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "Quartus II" 0 -1 1588562406579 ""} +{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." { } { } 0 310004 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "Quartus II" 0 -1 1588562406586 ""} } { } 0 310003 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "Quartus II" 0 -1 1588562406586 ""} +{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Simulation partitioned into 1 sub-simulations" { } { } 0 310002 "Simulation partitioned into %1!d! sub-simulations" 0 0 "Quartus II" 0 -1 1588562406589 ""} +{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" " 100.00 % " "Simulation coverage is 100.00 %" { } { } 0 328053 "Simulation coverage is %1!s!" 0 0 "Quartus II" 0 -1 1588562406591 ""} +{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "400 " "Number of transitions in simulation is 400" { } { } 0 328052 "Number of transitions in simulation is %1!s!" 0 0 "Quartus II" 0 -1 1588562406592 ""} +{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "YL_pulsar.sim.vwf " "Vector file YL_pulsar.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." { } { } 0 324045 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0 "Quartus II" 0 -1 1588562406594 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Simulator was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4484 " "Peak virtual memory: 4484 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588562406654 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 11:20:06 2020 " "Processing ended: Mon May 04 11:20:06 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588562406654 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588562406654 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588562406654 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588562406654 ""} diff --git a/YL_pulsar/db/YL_pulsar.sim.rdb b/YL_pulsar/db/YL_pulsar.sim.rdb new file mode 100644 index 0000000000000000000000000000000000000000..d6114130116aae2bb3eec65bf9bcd9c47f325a9a GIT binary patch literal 2553 zcmVc4=c}AW&grYalToQ%WFLWnv&jWNCD1Z*HC&000000086&00000 z005=|00000008+300000004La>{wfGBexZnd#`#=i{8=lCFw3|TO-v?8$ZR7?S+B0 zE!5iG27L&q8A@h7Gn|kdxe6AW|J(va@7wQ?9Lw}v(gBrrfY_OVOS!JoaM|am6~mqs+o-0w9I1? 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A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588559814025 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588559814026 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814027 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814027 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588559814030 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588559814043 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.136 " "Worst-case setup slack is 0.136" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.136 0.000 clk " " 0.136 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814051 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588559814051 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.610 " "Worst-case hold slack is 0.610" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.610 0.000 clk " " 0.610 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814055 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588559814055 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588559814060 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588559814063 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588559814064 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -5.297 clk " " -1.631 -5.297 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814067 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588559814067 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588559814124 ""} +{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588559814127 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.641 " "Worst-case setup slack is 0.641" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.641 0.000 clk " " 0.641 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814170 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588559814170 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.235 " "Worst-case hold slack is 0.235" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814174 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814174 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.235 0.000 clk " " 0.235 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814174 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588559814174 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588559814180 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588559814187 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588559814187 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -4.380 clk " " -1.380 -4.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588559814194 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588559814194 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588559814218 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588559814243 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588559814244 ""} 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13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.sof + 6. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon May 04 10:36:51 2020 ; +; Revision Name ; YL_pulsar ; +; Top-level Entity Name ; YL_pulsar ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++--------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------------------------------------+ +; File Name ; ++--------------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.sof ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.pof ; ++--------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.sof ; ++----------------+-----------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------------------------------------------+ +; Device ; EP2C20F484C7 ; +; JTAG usercode ; 0x001B083D ; +; Checksum ; 0x001B083D ; ++----------------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.pof ; ++--------------------+-------------------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+-------------------------------------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1DD9EC68 ; +; Compression Ratio ; 3 ; ++--------------------+-------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 10:36:49 2020 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_pulsar -c YL_pulsar +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4558 megabytes + Info: Processing ended: Mon May 04 10:36:51 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_pulsar/output_files/YL_pulsar.done b/YL_pulsar/output_files/YL_pulsar.done new file mode 100644 index 0000000..6635fb5 --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.done @@ -0,0 +1 @@ +Mon May 04 10:36:56 2020 diff --git a/YL_pulsar/output_files/YL_pulsar.eda.rpt b/YL_pulsar/output_files/YL_pulsar.eda.rpt new file mode 100644 index 0000000..410b344 --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.eda.rpt @@ -0,0 +1,92 @@ +EDA Netlist Writer report for YL_pulsar +Mon May 04 10:36:56 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Mon May 04 10:36:56 2020 ; +; Revision Name ; YL_pulsar ; +; Top-level Entity Name ; YL_pulsar ; +; Family ; Cyclone II ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate netlist for functional simulation only ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++--------------------------------------------------------------------------------------+ +; Generated Files ; ++--------------------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/simulation/modelsim/YL_pulsar.vo ; ++--------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit EDA Netlist Writer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 10:36:55 2020 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_pulsar -c YL_pulsar +Info (204019): Generated file YL_pulsar.vo in folder "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4529 megabytes + Info: Processing ended: Mon May 04 10:36:56 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/YL_pulsar/output_files/YL_pulsar.fit.rpt b/YL_pulsar/output_files/YL_pulsar.fit.rpt new file mode 100644 index 0000000..cb115b8 --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.fit.rpt @@ -0,0 +1,1138 @@ +Fitter report for YL_pulsar +Mon May 04 10:36:48 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. Output Pin Default Load For Reported TCO + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Control Signals + 20. Global & Other Fast Signals + 21. Non-Global High Fan-Out Signals + 22. Other Routing Usage Summary + 23. LAB Logic Elements + 24. LAB-wide Signals + 25. LAB Signals Sourced + 26. LAB Signals Sourced Out + 27. LAB Distinct Inputs + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Mon May 04 10:36:48 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_pulsar ; +; Top-level Entity Name ; YL_pulsar ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 3 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 3 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 3 / 18,752 ( < 1 % ) ; +; Total registers ; 3 ; +; Total pins ; 4 / 315 ( 1 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C20F484C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 16 ( 0.00 % ) ; +; -- Achieved ; 0 / 16 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 13 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.pin. + + ++--------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 3 / 18,752 ( < 1 % ) ; +; -- Combinational with no register ; 0 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 3 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 3 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 3 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 3 / 19,649 ( < 1 % ) ; +; -- Dedicated logic registers ; 3 / 18,752 ( < 1 % ) ; +; -- I/O registers ; 0 / 897 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 1,172 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 4 / 315 ( 1 % ) ; +; -- Clock pins ; 1 / 8 ( 13 % ) ; +; ; ; +; Global signals ; 2 ; +; M4Ks ; 0 / 52 ( 0 % ) ; +; Total block memory bits ; 0 / 239,616 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 3 ; +; Highest non-global fan-out ; 3 ; +; Total fan-out ; 17 ; +; Average fan-out ; 1.13 ; ++---------------------------------------------+----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 3 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; -- Combinational with no register ; 0 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 3 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 3 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 3 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 3 ; 0 ; +; -- Dedicated logic registers ; 3 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 1172 ( < 1 % ) ; 0 / 1172 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 4 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; 0 / 52 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 2 / 20 ( 10 % ) ; 0 / 20 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 17 ; 0 ; +; -- Registered Connections ; 3 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 3 ; 0 ; +; -- Output Ports ; 1 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; clk ; M1 ; 1 ; 0 ; 13 ; 2 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; key ; R7 ; 1 ; 0 ; 9 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; reset ; M2 ; 1 ; 0 ; 13 ; 3 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; output ; P5 ; 1 ; 0 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; ++--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 4 / 41 ( 10 % ) ; 3.3V ; -- ; +; 2 ; 2 / 33 ( 6 % ) ; 3.3V ; -- ; +; 3 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; +; 4 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 5 ; 0 / 39 ( 0 % ) ; 3.3V ; -- ; +; 6 ; 1 / 36 ( 3 % ) ; 3.3V ; -- ; +; 7 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 8 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 306 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A8 ; 304 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A9 ; 298 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A10 ; 293 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A11 ; 287 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 265 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 251 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 249 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 82 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA4 ; 85 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA5 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA6 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA7 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA11 ; 122 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 130 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 144 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 83 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB4 ; 84 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB5 ; 88 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB6 ; 96 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB7 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB12 ; 127 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB13 ; 129 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 305 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B8 ; 303 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B9 ; 297 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B10 ; 292 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B11 ; 286 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B14 ; 278 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 264 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B18 ; 250 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C7 ; 315 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; 310 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C10 ; 296 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C14 ; 260 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D2 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D5 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D6 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 302 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 289 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 267 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 259 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; 255 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; 266 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E15 ; 256 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F4 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 276 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F13 ; 269 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 268 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 262 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 261 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 252 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H2 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; H4 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H6 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 274 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; 263 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H14 ; 257 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H15 ; 253 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J1 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J2 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; 258 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M1 ; 41 ; 1 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M2 ; 42 ; 1 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 55 ; 1 ; output ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P6 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 187 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R1 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R2 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R5 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R6 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R7 ; 54 ; 1 ; key ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R8 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R10 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R11 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; R21 ; 190 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R22 ; 191 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T1 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T2 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T3 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T5 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T6 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T7 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T8 ; 90 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T12 ; 131 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T15 ; 147 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 188 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T22 ; 189 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U1 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U2 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U3 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U4 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U8 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U21 ; 182 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U22 ; 183 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V9 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 180 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 181 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W2 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W7 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W8 ; 100 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W9 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W21 ; 174 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; 175 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y3 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y4 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y5 ; 86 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y6 ; 87 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y7 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y13 ; 133 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y21 ; 178 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 179 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------+--------------+ +; |YL_pulsar ; 3 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 (0) ; 0 (0) ; 3 (0) ; |YL_pulsar ; work ; +; |pulsar:inst| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |YL_pulsar|pulsar:inst ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++--------+----------+---------------+---------------+-----------------------+-----+ +; output ; Output ; -- ; -- ; -- ; -- ; +; key ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; clk ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; reset ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; ++--------+----------+---------------+---------------+-----------------------+-----+ + + ++-------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------+-------------------+---------+ +; key ; ; ; +; - pulsar:inst|s2~0 ; 0 ; 6 ; +; - pulsar:inst|s1~0 ; 0 ; 6 ; +; - pulsar:inst|s0~0 ; 0 ; 6 ; +; clk ; ; ; +; reset ; ; ; ++-------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 3 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; reset ; PIN_M2 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 3 ; Global Clock ; GCLK3 ; -- ; +; reset ; PIN_M2 ; 3 ; Global Clock ; GCLK1 ; -- ; ++-------+----------+---------+----------------------+------------------+---------------------------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++------------------+--------------+ +; Name ; Fan-Out ; ++------------------+--------------+ +; key ; 3 ; +; pulsar:inst|s0~0 ; 1 ; +; pulsar:inst|s1~0 ; 1 ; +; pulsar:inst|s0 ; 1 ; +; pulsar:inst|s2~0 ; 1 ; +; pulsar:inst|s1 ; 1 ; +; pulsar:inst|s2 ; 1 ; ++------------------+--------------+ + + ++----------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+----------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+----------------------+ +; Block interconnects ; 2 / 54,004 ( < 1 % ) ; +; C16 interconnects ; 0 / 2,100 ( 0 % ) ; +; C4 interconnects ; 0 / 36,000 ( 0 % ) ; +; Direct links ; 1 / 54,004 ( < 1 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Local interconnects ; 2 / 18,752 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,900 ( 0 % ) ; +; R4 interconnects ; 0 / 46,920 ( 0 % ) ; ++-----------------------------+----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 3.00) ; Number of LABs (Total = 1) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 1 ; +; 1 Clock ; 1 ; ++------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 6.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP2C20F484C7 for design "YL_pulsar" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP2C15AF484C7 is compatible + Info (176445): Device EP2C35F484C7 is compatible + Info (176445): Device EP2C50F484C7 is compatible +Info (169124): Fitter converted 3 user pins into dedicated programming pins + Info (169125): Pin ~ASDO~ is reserved at location C4 + Info (169125): Pin ~nCSO~ is reserved at location C3 + Info (169125): Pin ~LVDS91p/nCEO~ is reserved at location W20 +Critical Warning (169085): No exact pin location assignment(s) for 4 pins of 4 total pins + Info (169086): Pin output not assigned to an exact location on the device + Info (169086): Pin key not assigned to an exact location on the device + Info (169086): Pin clk not assigned to an exact location on the device + Info (169086): Pin reset not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_pulsar.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 1 input, 1 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X12_Y0 to location X24_Y13 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.20 seconds. +Info (306004): Started post-fitting delay annotation +Warning (306006): Found 1 output pins without output pin load capacitance assignment + Info (306007): Pin "output" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info (306005): Delay annotation completed successfully +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 4844 megabytes + Info: Processing ended: Mon May 04 10:36:48 2020 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:07 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/output_files/YL_pulsar.fit.smsg. + + diff --git a/YL_pulsar/output_files/YL_pulsar.fit.smsg b/YL_pulsar/output_files/YL_pulsar.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/YL_pulsar/output_files/YL_pulsar.fit.summary b/YL_pulsar/output_files/YL_pulsar.fit.summary new file mode 100644 index 0000000..4b87de7 --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon May 04 10:36:48 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_pulsar +Top-level Entity Name : YL_pulsar +Family : Cyclone II +Device : EP2C20F484C7 +Timing Models : Final +Total logic elements : 3 / 18,752 ( < 1 % ) + Total combinational functions : 3 / 18,752 ( < 1 % ) + Dedicated logic registers : 3 / 18,752 ( < 1 % ) +Total registers : 3 +Total pins : 4 / 315 ( 1 % ) +Total virtual pins : 0 +Total memory bits : 0 / 239,616 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/YL_pulsar/output_files/YL_pulsar.flow.rpt b/YL_pulsar/output_files/YL_pulsar.flow.rpt new file mode 100644 index 0000000..4044fbb --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.flow.rpt @@ -0,0 +1,128 @@ +Flow report for YL_pulsar +Mon May 04 10:36:56 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Mon May 04 10:36:56 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_pulsar ; +; Top-level Entity Name ; YL_pulsar ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 3 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 3 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 3 / 18,752 ( < 1 % ) ; +; Total registers ; 3 ; +; Total pins ; 4 / 315 ( 1 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 05/04/2020 10:36:38 ; +; Main task ; Compilation ; +; Revision Name ; YL_pulsar ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 345052807169.158855979822976 ; -- ; -- ; -- ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; On ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------------+---------------+-------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4593 MB ; 00:00:02 ; +; Fitter ; 00:00:08 ; 1.0 ; 4844 MB ; 00:00:06 ; +; Assembler ; 00:00:02 ; 1.0 ; 4558 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4541 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4518 MB ; 00:00:01 ; +; Total ; 00:00:15 ; -- ; -- ; 00:00:12 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off YL_pulsar -c YL_pulsar +quartus_fit --read_settings_files=off --write_settings_files=off YL_pulsar -c YL_pulsar +quartus_asm --read_settings_files=off --write_settings_files=off YL_pulsar -c YL_pulsar +quartus_sta YL_pulsar -c YL_pulsar +quartus_eda --read_settings_files=off --write_settings_files=off YL_pulsar -c YL_pulsar + + + diff --git a/YL_pulsar/output_files/YL_pulsar.jdi b/YL_pulsar/output_files/YL_pulsar.jdi new file mode 100644 index 0000000..905fff4 --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/YL_pulsar/output_files/YL_pulsar.map.rpt b/YL_pulsar/output_files/YL_pulsar.map.rpt new file mode 100644 index 0000000..0abaa51 --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.map.rpt @@ -0,0 +1,286 @@ +Analysis & Synthesis report for YL_pulsar +Mon May 04 10:36:39 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. State Machine - |YL_pulsar|pulsar:inst|ss + 9. Registers Removed During Synthesis + 10. General Register Statistics + 11. Elapsed Time Per Partition + 12. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon May 04 10:36:39 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_pulsar ; +; Top-level Entity Name ; YL_pulsar ; +; Family ; Cyclone II ; +; Total logic elements ; 3 ; +; Total combinational functions ; 3 ; +; Dedicated logic registers ; 3 ; +; Total registers ; 3 ; +; Total pins ; 4 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; YL_pulsar ; YL_pulsar ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------+---------+ +; YL_pulsar.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.tdf ; ; +; YL_pulsar.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf ; ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 3 ; +; ; ; +; Total combinational functions ; 3 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 3 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 3 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 3 ; +; -- Dedicated logic registers ; 3 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 4 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; key ; +; Maximum fan-out ; 3 ; +; Total fan-out ; 15 ; +; Average fan-out ; 1.50 ; ++---------------------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+ +; |YL_pulsar ; 3 (0) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; |YL_pulsar ; work ; +; |pulsar:inst| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_pulsar|pulsar:inst ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + +Encoding Type: One-Hot ++-------------------------------------------+ +; State Machine - |YL_pulsar|pulsar:inst|ss ; ++------+----+----+----+---------------------+ +; Name ; s3 ; s1 ; s0 ; s2 ; ++------+----+----+----+---------------------+ +; s0 ; 0 ; 0 ; 0 ; 0 ; +; s1 ; 0 ; 1 ; 1 ; 0 ; +; s2 ; 0 ; 0 ; 1 ; 1 ; +; s3 ; 1 ; 0 ; 1 ; 0 ; ++------+----+----+----+---------------------+ + + ++------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+--------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+--------------------+ +; pulsar:inst|s3 ; Lost fanout ; +; Total Number of Removed Registers = 1 ; ; ++---------------------------------------+--------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 3 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 3 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 10:36:37 2020 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_pulsar -c YL_pulsar +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file yl_pulsar.tdf + Info (12023): Found entity 1: pulsar +Info (12021): Found 1 design units, including 1 entities, in source file yl_pulsar.bdf + Info (12023): Found entity 1: YL_pulsar +Info (12127): Elaborating entity "YL_pulsar" for the top level hierarchy +Info (12128): Elaborating entity "pulsar" for hierarchy "pulsar:inst" +Warning (284004): State bit assignments are not unique for state "|YL_pulsar|pulsar:inst|s0" and state "|YL_pulsar|pulsar:inst|s1" +Info (17049): 1 registers lost all their fanouts during netlist optimizations. +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 7 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 3 input pins + Info (21059): Implemented 1 output pins + Info (21061): Implemented 3 logic cells +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 4604 megabytes + Info: Processing ended: Mon May 04 10:36:40 2020 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_pulsar/output_files/YL_pulsar.map.summary b/YL_pulsar/output_files/YL_pulsar.map.summary new file mode 100644 index 0000000..f640491 --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon May 04 10:36:39 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_pulsar +Top-level Entity Name : YL_pulsar +Family : Cyclone II +Total logic elements : 3 + Total combinational functions : 3 + Dedicated logic registers : 3 +Total registers : 3 +Total pins : 4 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/YL_pulsar/output_files/YL_pulsar.pin b/YL_pulsar/output_files/YL_pulsar.pin new file mode 100644 index 0000000..aa6bedf --- /dev/null +++ b/YL_pulsar/output_files/YL_pulsar.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "YL_pulsar" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +GND* : A11 : : : : 3 : +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +GND* : AA3 : : : : 8 : +GND* : AA4 : : : : 8 : +GND* : AA5 : : : : 8 : +GND* : AA6 : : : : 8 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +GND* : AA11 : : : : 8 : +GND* : AA12 : : : : 7 : +GND* : AA13 : : : : 7 : +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +GND* : AB3 : : : : 8 : +GND* : AB4 : : : : 8 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +GND* : AB12 : : : : 7 : +GND* : AB13 : : : : 7 : +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +GND* : B11 : : : : 3 : +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +GND* : B14 : : : : 4 : +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +GND* : B17 : : : : 4 : +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 2 : +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +GND* : C7 : : : : 3 : +GND : C8 : gnd : : : : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +GND* : C14 : : : : 4 : +GND : C15 : gnd : : : : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +GND* : C21 : : : : 5 : +GND* : C22 : : : : 5 : +GND* : D1 : : : : 2 : +GND* : D2 : : : : 2 : +GND* : D3 : : : : 2 : +GND* : D4 : : : : 2 : +GND* : D5 : : : : 2 : +GND* : D6 : : : : 2 : +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +GND* : D9 : : : : 3 : +GND : D10 : gnd : : : : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +GND* : D14 : : : : 4 : +GND* : D15 : : : : 4 : +GND* : D16 : : : : 4 : +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +GND* : D20 : : : : 5 : +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +GND* : E14 : : : : 4 : +GND* : E15 : : : : 4 : +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +GND* : F1 : : : : 2 : +GND* : F2 : : : : 2 : +GND* : F3 : : : : 2 : +GND* : F4 : : : : 2 : +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +GND* : F12 : : : : 4 : +GND* : F13 : : : : 4 : +GND* : F14 : : : : 4 : +GND* : F15 : : : : 4 : +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +GND* : G3 : : : : 2 : +GND : G4 : gnd : : : : +GND* : G5 : : : : 2 : +GND* : G6 : : : : 2 : +GND* : G7 : : : : 3 : +GND* : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +GND* : G15 : : : : 4 : +GND* : G16 : : : : 4 : +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +GND* : H4 : : : : 2 : +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +GND* : H12 : : : : 4 : +GND* : H13 : : : : 4 : +GND* : H14 : : : : 4 : +GND* : H15 : : : : 4 : +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +GND* : J1 : : : : 2 : +GND* : J2 : : : : 2 : +NC : J3 : : : : : +GND* : J4 : : : : 2 : +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +GND* : J14 : : : : 4 : +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +GND+ : L1 : : : : 2 : +GND+ : L2 : : : : 2 : +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +GND* : L8 : : : : 2 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +GND+ : L21 : : : : 5 : +GND+ : L22 : : : : 5 : +clk : M1 : input : 3.3-V LVTTL : : 1 : N +reset : M2 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +GND+ : M22 : : : : 6 : +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +output : P5 : output : 3.3-V LVTTL : : 1 : N +GND* : P6 : : : : 1 : +VCCIO1 : P7 : power : : 3.3V : 1 : +GND* : P8 : : : : 8 : +GND* : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +GND* : P18 : : : : 6 : +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +GND* : R1 : : : : 1 : +GND* : R2 : : : : 1 : +GND : R3 : gnd : : : : +NC : R4 : : : : : +GND* : R5 : : : : 1 : +GND* : R6 : : : : 1 : +key : R7 : input : 3.3-V LVTTL : : 1 : N +GND* : R8 : : : : 1 : +GND* : R9 : : : : 8 : +GND* : R10 : : : : 8 : +GND* : R11 : : : : 8 : +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +GND* : T1 : : : : 1 : +GND* : T2 : : : : 1 : +GND* : T3 : : : : 1 : +VCCIO1 : T4 : power : : 3.3V : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 8 : +GND* : T8 : : : : 8 : +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +GND* : T12 : : : : 7 : +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +GND* : T15 : : : : 7 : +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +GND* : U8 : : : : 8 : +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND : V3 : gnd : : : : +GND* : V4 : : : : 1 : +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +GND* : V8 : : : : 8 : +GND* : V9 : : : : 8 : +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +VCCIO8 : W6 : power : : 3.3V : 8 : +GND* : W7 : : : : 8 : +GND* : W8 : : : : 8 : +GND* : W9 : : : : 8 : +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 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z7Z3;phAh1c>>S8_FUKfo^BBcZsonvP&<BTH+ zlU{TD8rp)dVE}<8o|L?N*}UveASiIY^}^@d{daj(s`umRNoqL*&raC$Z`wGgk0;!} z+kE@}%xjwe^^0`cDPN*^^M5s){n!6tH$C#he^(DfGH|x>&i~z9^}qg4-06WU{u{U+ zMm5ye*bYK6^fKJO{?~DT8f Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// key => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// reset => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \key~combout ; +wire \inst|s0~0_combout ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \inst|s0~regout ; +wire \inst|s1~0_combout ; +wire \inst|s1~regout ; +wire \inst|s2~0_combout ; +wire \inst|s2~regout ; + + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \key~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\key~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(key)); +// synopsys translate_off +defparam \key~I .input_async_reset = "none"; +defparam \key~I .input_power_up = "low"; +defparam \key~I .input_register_mode = "none"; +defparam \key~I .input_sync_reset = "none"; +defparam \key~I .oe_async_reset = "none"; +defparam \key~I .oe_power_up = "low"; +defparam \key~I .oe_register_mode = "none"; +defparam \key~I .oe_sync_reset = "none"; +defparam \key~I .operation_mode = "input"; +defparam \key~I .output_async_reset = "none"; +defparam \key~I .output_power_up = "low"; +defparam \key~I .output_register_mode = "none"; +defparam \key~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y9_N0 +cycloneii_lcell_comb \inst|s0~0 ( +// Equation(s): +// \inst|s0~0_combout = !\key~combout + + .dataa(vcc), + .datab(vcc), + .datac(\key~combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst|s0~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|s0~0 .lut_mask = 16'h0F0F; +defparam \inst|s0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \reset~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\reset~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(reset)); +// synopsys translate_off +defparam \reset~I .input_async_reset = "none"; +defparam \reset~I .input_power_up = "low"; +defparam \reset~I .input_register_mode = "none"; +defparam \reset~I .input_sync_reset = "none"; +defparam \reset~I .oe_async_reset = "none"; +defparam \reset~I .oe_power_up = "low"; +defparam \reset~I .oe_register_mode = "none"; +defparam \reset~I .oe_sync_reset = "none"; +defparam \reset~I .operation_mode = "input"; +defparam \reset~I .output_async_reset = "none"; +defparam \reset~I .output_power_up = "low"; +defparam \reset~I .output_register_mode = "none"; +defparam \reset~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneii_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCFF_X1_Y9_N1 +cycloneii_lcell_ff \inst|s0 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|s0~0_combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|s0~regout )); + +// Location: LCCOMB_X1_Y9_N2 +cycloneii_lcell_comb \inst|s1~0 ( +// Equation(s): +// \inst|s1~0_combout = (!\key~combout & !\inst|s0~regout ) + + .dataa(vcc), + .datab(vcc), + .datac(\key~combout ), + .datad(\inst|s0~regout ), + .cin(gnd), + .combout(\inst|s1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|s1~0 .lut_mask = 16'h000F; +defparam \inst|s1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y9_N3 +cycloneii_lcell_ff \inst|s1 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|s1~0_combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|s1~regout )); + +// Location: LCCOMB_X1_Y9_N20 +cycloneii_lcell_comb \inst|s2~0 ( +// Equation(s): +// \inst|s2~0_combout = (!\key~combout & \inst|s1~regout ) + + .dataa(vcc), + .datab(vcc), + .datac(\key~combout ), + .datad(\inst|s1~regout ), + .cin(gnd), + .combout(\inst|s2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|s2~0 .lut_mask = 16'h0F00; +defparam \inst|s2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y9_N21 +cycloneii_lcell_ff \inst|s2 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|s2~0_combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|s2~regout )); + +// Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \output~I ( + .datain(\inst|s2~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(\output )); +// synopsys translate_off +defparam \output~I .input_async_reset = "none"; +defparam \output~I .input_power_up = "low"; +defparam \output~I .input_register_mode = "none"; +defparam \output~I .input_sync_reset = "none"; +defparam \output~I .oe_async_reset = "none"; +defparam \output~I .oe_power_up = "low"; +defparam \output~I .oe_register_mode = "none"; +defparam \output~I .oe_sync_reset = "none"; +defparam \output~I .operation_mode = "output"; +defparam \output~I .output_async_reset = "none"; +defparam \output~I .output_power_up = "low"; +defparam \output~I .output_register_mode = "none"; +defparam \output~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/YL_pulsar/simulation/modelsim/YL_pulsar_modelsim.xrf b/YL_pulsar/simulation/modelsim/YL_pulsar_modelsim.xrf new file mode 100644 index 0000000..f5d0edb --- /dev/null +++ b/YL_pulsar/simulation/modelsim/YL_pulsar_modelsim.xrf @@ -0,0 +1,18 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.bdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.vwf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/db/YL_pulsar.cbx.xml +design_name = YL_pulsar +instance = comp, \clk~I , clk, YL_pulsar, 1 +instance = comp, \clk~clkctrl , clk~clkctrl, YL_pulsar, 1 +instance = comp, \key~I , key, YL_pulsar, 1 +instance = comp, \inst|s0~0 , inst|s0~0, YL_pulsar, 1 +instance = comp, \reset~I , reset, YL_pulsar, 1 +instance = comp, \reset~clkctrl , reset~clkctrl, YL_pulsar, 1 +instance = comp, \inst|s0 , inst|s0, YL_pulsar, 1 +instance = comp, \inst|s1~0 , inst|s1~0, YL_pulsar, 1 +instance = comp, \inst|s1 , inst|s1, YL_pulsar, 1 +instance = comp, \inst|s2~0 , inst|s2~0, YL_pulsar, 1 +instance = comp, \inst|s2 , inst|s2, YL_pulsar, 1 +instance = comp, \output~I , output, YL_pulsar, 1 diff --git a/YL_pulsar/simulation/qsim/YL_pulsar.do b/YL_pulsar/simulation/qsim/YL_pulsar.do new file mode 100644 index 0000000..4113795 --- /dev/null +++ b/YL_pulsar/simulation/qsim/YL_pulsar.do @@ -0,0 +1,10 @@ +onerror {quit -f} +vlib work +vlog -work work YL_pulsar.vo +vlog -work work YL_pulsar.vt +vsim -novopt -c -t 1ps -L cycloneii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.YL_pulsar_vlg_vec_tst +vcd file -direction YL_pulsar.msim.vcd +vcd add -internal YL_pulsar_vlg_vec_tst/* +vcd add -internal YL_pulsar_vlg_vec_tst/i1/* +add wave /* +run -all diff --git a/YL_pulsar/simulation/qsim/YL_pulsar.sim.vwf b/YL_pulsar/simulation/qsim/YL_pulsar.sim.vwf new file mode 100644 index 0000000..de394c4 --- /dev/null +++ b/YL_pulsar/simulation/qsim/YL_pulsar.sim.vwf @@ -0,0 +1,207 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 1000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 2.5; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("key") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("output") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 8; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + NODE + { + REPEAT = 40; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("key") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 27.5; + LEVEL 1 FOR 62.5; + LEVEL 0 FOR 27.5; + LEVEL 1 FOR 42.5; + LEVEL 0 FOR 37.5; + LEVEL 1 FOR 152.5; + } +} + +TRANSITION_LIST("output") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 176.529; + NODE + { + REPEAT = 2; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 60.0; + } + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 123.471; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 520.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 460.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "key"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "output"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_pulsar/simulation/qsim/YL_pulsar.vo b/YL_pulsar/simulation/qsim/YL_pulsar.vo new file mode 100644 index 0000000..6de9466 --- /dev/null +++ b/YL_pulsar/simulation/qsim/YL_pulsar.vo @@ -0,0 +1,332 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/04/2020 10:34:41" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_pulsar ( + \output , + clk, + reset, + key); +output \output ; +input clk; +input reset; +input key; + +// Design Ports Information +// output => Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// key => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// reset => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \key~combout ; +wire \inst|s0~feeder_combout ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \inst|s0~regout ; +wire \inst|s1~0_combout ; +wire \inst|s1~regout ; +wire \inst|s2~0_combout ; +wire \inst|s2~regout ; + + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \key~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\key~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(key)); +// synopsys translate_off +defparam \key~I .input_async_reset = "none"; +defparam \key~I .input_power_up = "low"; +defparam \key~I .input_register_mode = "none"; +defparam \key~I .input_sync_reset = "none"; +defparam \key~I .oe_async_reset = "none"; +defparam \key~I .oe_power_up = "low"; +defparam \key~I .oe_register_mode = "none"; +defparam \key~I .oe_sync_reset = "none"; +defparam \key~I .operation_mode = "input"; +defparam \key~I .output_async_reset = "none"; +defparam \key~I .output_power_up = "low"; +defparam \key~I .output_register_mode = "none"; +defparam \key~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y9_N0 +cycloneii_lcell_comb \inst|s0~feeder ( +// Equation(s): +// \inst|s0~feeder_combout = \key~combout + + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\key~combout ), + .cin(gnd), + .combout(\inst|s0~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \inst|s0~feeder .lut_mask = 16'hFF00; +defparam \inst|s0~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \reset~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\reset~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(reset)); +// synopsys translate_off +defparam \reset~I .input_async_reset = "none"; +defparam \reset~I .input_power_up = "low"; +defparam \reset~I .input_register_mode = "none"; +defparam \reset~I .input_sync_reset = "none"; +defparam \reset~I .oe_async_reset = "none"; +defparam \reset~I .oe_power_up = "low"; +defparam \reset~I .oe_register_mode = "none"; +defparam \reset~I .oe_sync_reset = "none"; +defparam \reset~I .operation_mode = "input"; +defparam \reset~I .output_async_reset = "none"; +defparam \reset~I .output_power_up = "low"; +defparam \reset~I .output_register_mode = "none"; +defparam \reset~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneii_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCFF_X1_Y9_N1 +cycloneii_lcell_ff \inst|s0 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|s0~feeder_combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|s0~regout )); + +// Location: LCCOMB_X1_Y9_N2 +cycloneii_lcell_comb \inst|s1~0 ( +// Equation(s): +// \inst|s1~0_combout = (\key~combout & !\inst|s0~regout ) + + .dataa(\key~combout ), + .datab(vcc), + .datac(vcc), + .datad(\inst|s0~regout ), + .cin(gnd), + .combout(\inst|s1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|s1~0 .lut_mask = 16'h00AA; +defparam \inst|s1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y9_N3 +cycloneii_lcell_ff \inst|s1 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|s1~0_combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|s1~regout )); + +// Location: LCCOMB_X1_Y9_N20 +cycloneii_lcell_comb \inst|s2~0 ( +// Equation(s): +// \inst|s2~0_combout = (\key~combout & \inst|s1~regout ) + + .dataa(\key~combout ), + .datab(vcc), + .datac(vcc), + .datad(\inst|s1~regout ), + .cin(gnd), + .combout(\inst|s2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|s2~0 .lut_mask = 16'hAA00; +defparam \inst|s2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y9_N21 +cycloneii_lcell_ff \inst|s2 ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|s2~0_combout ), + .sdata(gnd), + .aclr(\reset~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|s2~regout )); + +// Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \output~I ( + .datain(\inst|s2~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(\output )); +// synopsys translate_off +defparam \output~I .input_async_reset = "none"; +defparam \output~I .input_power_up = "low"; +defparam \output~I .input_register_mode = "none"; +defparam \output~I .input_sync_reset = "none"; +defparam \output~I .oe_async_reset = "none"; +defparam \output~I .oe_power_up = "low"; +defparam \output~I .oe_register_mode = "none"; +defparam \output~I .oe_sync_reset = "none"; +defparam \output~I .operation_mode = "output"; +defparam \output~I .output_async_reset = "none"; +defparam \output~I .output_power_up = "low"; +defparam \output~I .output_register_mode = "none"; +defparam \output~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/YL_pulsar/simulation/qsim/YL_pulsar.vt b/YL_pulsar/simulation/qsim/YL_pulsar.vt new file mode 100644 index 0000000..3047b26 --- /dev/null +++ b/YL_pulsar/simulation/qsim/YL_pulsar.vt @@ -0,0 +1,270 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "05/04/2020 10:34:40" + +// Verilog Self-Checking Test Bench (with test vectors) for design : YL_pulsar +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module YL_pulsar_vlg_sample_tst( + clk, + key, + reset, + sampler_tx +); +input clk; +input key; +input reset; +output sampler_tx; + +reg sample; +time current_time; +always @(clk or key or reset) + +begin + if ($realtime > 0) + begin + if ($realtime == 0 || $realtime != current_time) + begin + if (sample === 1'bx) + sample = 0; + else + sample = ~sample; + end + current_time = $realtime; + end +end + +assign sampler_tx = sample; +endmodule + +module YL_pulsar_vlg_check_tst ( + output, + sampler_rx +); +input output; +input sampler_rx; + +reg output_expected; + +reg output_prev; + +reg output_expected_prev; + +reg last_output_exp; + +reg trigger; + +integer i; +integer nummismatches; + +reg [1:1] on_first_change ; + + +initial +begin +trigger = 0; +i = 0; +nummismatches = 0; +on_first_change = 1'b1; +end + +// update real /o prevs + +always @(trigger) +begin + output_prev = output; +end + +// update expected /o prevs + +always @(trigger) +begin + output_expected_prev = output_expected; +end + + + +// expected output +initial +begin + output_expected = 1'bX; +end +// generate trigger +always @(output_expected or output) +begin + trigger <= ~trigger; +end + +always @(posedge sampler_rx or negedge sampler_rx) +begin +`ifdef debug_tbench + $display("Scanning pattern %d @time = %t",i,$realtime ); + i = i + 1; + $display("| expected output = %b | ",output_expected_prev); + $display("| real output = %b | ",output_prev); +`endif + if ( + ( output_expected_prev !== 1'bx ) && ( output_prev !== output_expected_prev ) + && ((output_expected_prev !== last_output_exp) || + on_first_change[1]) + ) + begin + $display ("ERROR! Vector Mismatch for output port output :: @time = %t", $realtime); + $display (" Expected value = %b", output_expected_prev); + $display (" Real value = %b", output_prev); + nummismatches = nummismatches + 1; + on_first_change[1] = 1'b0; + last_output_exp = output_expected_prev; + end + + trigger <= ~trigger; +end +initial + +begin +$timeformat(-12,3," ps",6); +#1000000; +if (nummismatches > 0) + $display ("%d mismatched vectors : Simulation failed !",nummismatches); +else + $display ("Simulation passed !"); +$finish; +end +endmodule + +module YL_pulsar_vlg_vec_tst(); +// constants +// general purpose registers +reg clk; +reg key; +reg reset; +// wires +wire output; + +wire sampler; + +// assign statements (if any) +YL_pulsar i1 ( +// port map - connection between master ports and signals/registers + .clk(clk), + .key(key), + .\output (output), + .reset(reset) +); + +// clk +always +begin + clk = 1'b0; + clk = #10000 1'b1; + #10000; +end + +// key +initial +begin + key = 1'b1; + key = #40000 1'b0; + key = #2757 1'b1; + key = #3100 1'b0; + key = #6900 1'b1; + key = #3100 1'b0; + key = #4296 1'b1; + key = #3100 1'b0; + key = #6747 1'b1; + key = #1089 1'b0; + key = #6700 1'b1; + key = #3300 1'b0; + key = #6700 1'b1; + key = #3489 1'b0; + key = #6500 1'b1; + key = #3500 1'b0; + key = #6500 1'b1; + key = #6997 1'b0; + key = #13000 1'b1; + key = #2225 1'b0; + key = #1490 1'b1; + # 1633; + repeat(2) + begin + key = 1'b0; + key = #1700 1'b1; + # 1633; + end + key = 1'b0; + key = #211 1'b1; + key = #120000 1'b0; + key = #1157 1'b1; + # 3799; + repeat(2) + begin + key = 1'b0; + key = #2867 1'b1; + # 3799; + end + key = 1'b0; + key = #4533 1'b1; + key = #9800 1'b0; + key = #17005 1'b1; + key = #9000 1'b0; + key = #2116 1'b1; + # 3666; + repeat(2) + begin + key = 1'b0; + key = #3000 1'b1; + # 3666; + end + key = 1'b0; + key = #4244 1'b1; + # 2466; + repeat(2) + begin + key = 1'b0; + key = #4200 1'b1; + # 2466; + end + key = 1'b0; + key = #2218 1'b1; +end + +// reset +initial +begin + reset = 1'b0; +end + +YL_pulsar_vlg_sample_tst tb_sample ( + .clk(clk), + .key(key), + .reset(reset), + .sampler_tx(sampler) +); + +YL_pulsar_vlg_check_tst tb_out( + .output(output), + .sampler_rx(sampler) +); +endmodule + diff --git a/YL_pushcounter/7segment.bsf b/YL_pushcounter/7segment.bsf new file mode 100644 index 0000000..c9f4ae8 --- /dev/null +++ b/YL_pushcounter/7segment.bsf @@ -0,0 +1,85 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 144 192) + (text "7segment" (rect 5 0 43 12)(font "Arial" )) + (text "inst" (rect 8 160 20 172)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "i[3..0]" (rect 0 0 21 12)(font "Arial" )) + (text "i[3..0]" (rect 21 27 42 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 128 32) + (output) + (text "a" (rect 0 0 4 12)(font "Arial" )) + (text "a" (rect 103 27 107 39)(font "Arial" )) + (line (pt 128 32)(pt 112 32)(line_width 1)) + ) + (port + (pt 128 48) + (output) + (text "b" (rect 0 0 4 12)(font "Arial" )) + (text "b" (rect 103 43 107 55)(font "Arial" )) + (line (pt 128 48)(pt 112 48)(line_width 1)) + ) + (port + (pt 128 64) + (output) + (text "c" (rect 0 0 4 12)(font "Arial" )) + (text "c" (rect 103 59 107 71)(font "Arial" )) + (line (pt 128 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 128 80) + (output) + (text "d" (rect 0 0 4 12)(font "Arial" )) + (text "d" (rect 103 75 107 87)(font "Arial" )) + (line (pt 128 80)(pt 112 80)(line_width 1)) + ) + (port + (pt 128 96) + (output) + (text "e" (rect 0 0 4 12)(font "Arial" )) + (text "e" (rect 103 91 107 103)(font "Arial" )) + (line (pt 128 96)(pt 112 96)(line_width 1)) + ) + (port + (pt 128 112) + (output) + (text "f" (rect 0 0 3 12)(font "Arial" )) + (text "f" (rect 104 107 107 119)(font "Arial" )) + (line (pt 128 112)(pt 112 112)(line_width 1)) + ) + (port + (pt 128 128) + (output) + (text "g" (rect 0 0 4 12)(font "Arial" )) + (text "g" (rect 103 123 107 135)(font "Arial" )) + (line (pt 128 128)(pt 112 128)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 112 160)(line_width 1)) + ) +) diff --git a/YL_pushcounter/YL_7segment.tdf b/YL_pushcounter/YL_7segment.tdf new file mode 100644 index 0000000..5865cb1 --- /dev/null +++ b/YL_pushcounter/YL_7segment.tdf @@ -0,0 +1,28 @@ +% 0 1 2 3 4 5 6 7 8 9 A b C d E F % +% % +SUBDESIGN 7segment +( + i[3..0] : INPUT; + a, b, c, d, e, f, g : OUTPUT; +) +BEGIN + TABLE + i[3..0] => a, b, c, d, e, f, g; + H"0" => 1, 1, 1, 1, 1, 1, 0; + H"1" => 0, 1, 1, 0, 0, 0, 0; + H"2" => 1, 1, 0, 1, 1, 0, 1; + H"3" => 1, 1, 1, 1, 0, 0, 1; + H"4" => 0, 1, 1, 0, 0, 1, 1; + H"5" => 1, 0, 1, 1, 0, 1, 1; + H"6" => 1, 0, 1, 1, 1, 1, 1; + H"7" => 1, 1, 1, 0, 0, 0, 0; + H"8" => 1, 1, 1, 1, 1, 1, 1; + H"9" => 1, 1, 1, 1, 0, 1, 1; + H"A" => 1, 1, 1, 0, 1, 1, 1; + H"B" => 0, 0, 1, 1, 1, 1, 1; + H"C" => 1, 0, 0, 1, 1, 1, 0; + H"D" => 0, 1, 1, 1, 1, 0, 1; + H"E" => 1, 0, 0, 1, 1, 1, 1; + H"F" => 1, 0, 0, 0, 1, 1, 1; + END TABLE; +END; diff --git a/YL_pushcounter/YL_counter.tdf b/YL_pushcounter/YL_counter.tdf new file mode 100644 index 0000000..33f4b64 --- /dev/null +++ b/YL_pushcounter/YL_counter.tdf @@ -0,0 +1,25 @@ +SUBDESIGN dec_count +( + enc, ent, clk : INPUT; % two enables and the clock % + clear : INPUT; % Synchronous clear % + value[3..0] : OUTPUT; % Four output bits % + rco : OUTPUT; % ripple carry out % +) +VARIABLE + count[3..0] : DFF; % locally define 4 D-Flip-Flops for the count % +BEGIN + count[].clk = clk; % Connect the clock input to the DFF’s clock % + value[] = count[]; % connect the outputs of the DFFs to the outputs % + IF (clear) THEN % if clear is true clear the count i.e. % + count[].d = 0; % load the flipflops with zero % + ELSIF (enc & ent & (count[].q != 9)) THEN + % if both enables are true and the count does not % + count[].d = count[].q + 1; % equal nine then add one to the count value % + ELSIF (enc & ent & (count[].q == 9)) THEN + % if both enables are true and the count does % + count[].d = 0; % equal nine then load the flip flops with zero % + ELSE % with no enable keep the flips flops at the same value % + count[].d = count[].q; + END IF; + rco = ((count[].q == 9) & ent);% generate the rco when the count is nine and ent is true % +END; diff --git a/YL_pushcounter/YL_counter.tdf.bak b/YL_pushcounter/YL_counter.tdf.bak new file mode 100644 index 0000000..04a701c --- /dev/null +++ b/YL_pushcounter/YL_counter.tdf.bak @@ -0,0 +1,25 @@ +SUBDESIGN dec_count +( + enc, ent, clk : INPUT; % two enables and the clock % + clear : INPUT; % Synchronous clear % + value[3..0] : OUTPUT; % Four output bits % + rco : OUTPUT; % ripple carry out % +) +VARIABLE + count[3..0] : DFF; % locally define 4 D-Flip-Flops for the count % +BEGIN + count[].clk = clk; % Connect the clock input to the DFF’s clock % + value[] = count[]; % connect the outputs of the DFFs to the outputs % + IF (clear) THEN % if clear is true clear the count i.e. % + count[].d = 1; % load the flipflops with zero % + ELSIF (enc & ent & (count[].q != 9)) THEN + % if both enables are true and the count does not % + count[].d = count[].q + 1; % equal nine then add one to the count value % + ELSIF (enc & ent & (count[].q == 9)) THEN + % if both enables are true and the count does % + count[].d = 1; % equal nine then load the flip flops with zero % + ELSE % with no enable keep the flips flops at the same value % + count[].d = count[].q; + END IF; + rco = ((count[].q == 9) & ent);% generate the rco when the count is nine and ent is true % +END; diff --git a/YL_pushcounter/YL_pushcounter.bdf b/YL_pushcounter/YL_pushcounter.bdf new file mode 100644 index 0000000..2e46e6b --- /dev/null +++ b/YL_pushcounter/YL_pushcounter.bdf @@ -0,0 +1,828 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 72 104 240 120) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 19 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 16 120 72 136)) +) +(pin + (input) + (rect 72 120 240 136) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "reset" (rect 5 0 29 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 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(including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 11:29:00 May 04, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "11:29:00 May 04, 2020" + +# Revisions + +PROJECT_REVISION = "YL_pushcounter" diff --git a/YL_pushcounter/YL_pushcounter.qsf b/YL_pushcounter/YL_pushcounter.qsf new file mode 100644 index 0000000..308b19a --- /dev/null +++ b/YL_pushcounter/YL_pushcounter.qsf @@ -0,0 +1,74 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 11:29:00 May 04, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# YL_pushcounter_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY YL_pushcounter +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:29:00 MAY 04, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name AHDL_FILE YL_pushcounter.tdf +set_global_assignment -name BDF_FILE YL_pushcounter.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name AHDL_FILE YL_counter.tdf +set_global_assignment -name AHDL_FILE YL_7segment.tdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_R21 -to key +set_location_assignment PIN_J2 -to OUTPUT_A +set_location_assignment PIN_J1 -to OUTPUT_B +set_location_assignment PIN_H2 -to OUTPUT_C +set_location_assignment PIN_H1 -to OUTPUT_D +set_location_assignment PIN_F2 -to OUTPUT_E +set_location_assignment PIN_F1 -to OUTPUT_F +set_location_assignment PIN_E2 -to OUTPUT_G +set_location_assignment PIN_L22 -to reset +set_location_assignment PIN_L1 -to clk +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_pushcounter.vwf +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.vwf" \ No newline at end of file diff --git a/YL_pushcounter/YL_pushcounter.qws b/YL_pushcounter/YL_pushcounter.qws new file mode 100644 index 0000000000000000000000000000000000000000..15b693659bbb088f4e66f36fc1fd198e2efb2e64 GIT binary patch literal 6568 zcmeI0y>AmS7{;GVkjTh{7#J#qP=%DHNmGT7rJ^lUB_uuuB&4cME+uM9swCw@sB~vQ zObm#Dm6@&o0t+h>e+Y&0d!0K)Ih{&~5_&!2lYM^e_w3h?AHTM5VOn9hs4cCjt&Udp zOii`4iL^smRX$2*iSM+i8!G4lH9i_`^1Gyu)!>VQ?&t~SOVl*$L#6^`<h;AdJelvx&~594zVV4WBd)-Rna}<4Q-Pe^ZK=Vh$Yp&a232A3x0#F z&x-R1Jp_AmnqzgY=%wbte2zIN!`3ouHc$RKB~^0f2WrGT-e#8a3b|RH5^)XPI%yf* zIwgCFT-~ws_eYwR60w&bo-H z=lRfQHCo@x7~F89Y?*PxQ46`7c%>_{5_NyQNL_l ztpH^acKUG9IF~1`^Y}4bwc03G=g~C}lT5BU|8LlOpGX{)(#cih(9m4H0P(gU9SaKD z{ei8yPytvoHzTYc1C`yRN!eEcm7{W(-A3gaj<@WbuQ_0IyK~5;SSp(Xj#9adc9CVU z7Y?eQG)5x}n;3F%XwJd=L2`+OzQ!WhqMs>1tdlPCw#~J>#kPYly#v%A+3E*5kaBW5 zT&0b0X!?zTG?-%{;_ssJY4U&OV~0Hd+T`?8*`P_+UY%b5XFMhhK;=;$I}>(caul8% zH`!)589P3Ndz2HT|M9q))GO-b(5c8>E{?G&IdqQF=_ZxXlNc3No`wJI)P{{6c0Dcbw>9}m2{{K?$GXFU^y4Z#Imqn8^`VGsvK&=1( literal 0 HcmV?d00001 diff --git a/YL_pushcounter/YL_pushcounter.tdf b/YL_pushcounter/YL_pushcounter.tdf new file mode 100644 index 0000000..6292f61 --- /dev/null +++ b/YL_pushcounter/YL_pushcounter.tdf @@ -0,0 +1,35 @@ +SUBDESIGN pulsar +( + clk, reset, key : input; + o : output; +) +VARIABLE + ss: MACHINE OF BITS (o) WITH STATES ( + s0 = 0, + s1 = 0, + s2 = 1, + s3 = 0 + ); +BEGIN + ss.clk = clk; + ss.reset = reset; + + TABLE + % current current next % + ss, key => ss; + s0, 0 => s0; + s0, 1 => s1; + s1, 0 => s0; + s1, 1 => s2; + s2, 0 => s0; + s2, 1 => s3; + s3, 0 => s0; + s3, 1 => s3; + END TABLE; + +END; + + + + + \ No newline at end of file diff --git a/YL_pushcounter/YL_pushcounter.vwf b/YL_pushcounter/YL_pushcounter.vwf new file mode 100644 index 0000000..e5f5b69 --- /dev/null +++ b/YL_pushcounter/YL_pushcounter.vwf @@ -0,0 +1,499 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("key") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_C") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_D") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_E") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_F") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("OUTPUT_G") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("rco") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("value") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("key") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 420.0; + } +} + +TRANSITION_LIST("OUTPUT_A") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_B") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_C") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_D") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_E") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_F") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("OUTPUT_G") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("rco") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 700.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 280.0; + } +} + +TRANSITION_LIST("value[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("value[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "key"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "value"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7; +} + +DISPLAY_LINE +{ + CHANNEL = "value[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "value[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "value[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "value[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_C"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_D"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "OUTPUT_E"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + 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0000000000000000000000000000000000000000..3faf321402deb649e3f10a1ba60d956f60844cc3 GIT binary patch literal 230 zcmVuG0001ZoTZV$N&_(vhVT0nL+;((>`G7FJrq1tdQb|Ar;ui+HmsYC zlS!fA!mTnYS@F*6L#Wpt9%ScGe^frrJ1~%ke*P$h89b?-C~MLQeXx g pulsar:inst.clk +clk => dec_count:inst1.clk +reset => pulsar:inst.reset +reset => dec_count:inst1.clear +key => inst99.IN0 +OUTPUT_A <= inst3.DB_MAX_OUTPUT_PORT_TYPE +value[0] <= dec_count:inst1.value[0] +value[1] <= dec_count:inst1.value[1] +value[2] <= dec_count:inst1.value[2] +value[3] <= dec_count:inst1.value[3] +OUTPUT_B <= inst4.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_C <= inst5.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_D <= inst6.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_E <= inst7.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_F <= inst8.DB_MAX_OUTPUT_PORT_TYPE +OUTPUT_G <= inst9.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_pushcounter|dec_count:inst1 +enc => _.IN0 +enc => _.IN0 +ent => _.IN1 +ent => _.IN1 +ent => rco.IN1 +clk => count[3].CLK +clk => count[2].CLK +clk => count[1].CLK +clk => count[0].CLK +clear => _.IN0 +value[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE +value[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE +value[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE +value[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE +rco <= rco.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_pushcounter|pulsar:inst +clk => ss.IN1 +reset => ss.IN1 +key => _.IN0 +key => _.IN1 +key => _.IN0 +key => _.IN1 +key => _.IN0 +key => _.IN1 +key => _.IN0 +key => _.IN1 +o <= ss$o.DB_MAX_OUTPUT_PORT_TYPE + + +|YL_pushcounter|7segment:inst_ +i[0] => _.IN0 +i[0] => b~0.IN3 +i[0] => _.IN0 +i[0] => a~2.IN3 +i[0] => _.IN0 +i[0] => a~3.IN3 +i[0] => _.IN0 +i[0] => a~5.IN3 +i[0] => _.IN0 +i[0] => a~7.IN3 +i[0] => _.IN0 +i[0] => c~0.IN3 +i[0] => _.IN0 +i[0] => b~2.IN3 +i[0] => _.IN0 +i[0] => a~11.IN3 +i[1] => _.IN0 +i[1] => _.IN0 +i[1] => a~1.IN2 +i[1] => a~2.IN2 +i[1] => _.IN0 +i[1] => _.IN0 +i[1] => a~4.IN2 +i[1] => a~5.IN2 +i[1] => _.IN0 +i[1] => _.IN0 +i[1] => a~8.IN2 +i[1] => c~0.IN2 +i[1] => _.IN0 +i[1] => _.IN0 +i[1] => a~10.IN2 +i[1] => a~11.IN2 +i[2] => _.IN0 +i[2] => _.IN0 +i[2] => _.IN0 +i[2] => _.IN0 +i[2] => b~1.IN1 +i[2] => a~3.IN1 +i[2] => a~4.IN1 +i[2] => a~5.IN1 +i[2] => _.IN0 +i[2] => _.IN0 +i[2] => _.IN0 +i[2] => _.IN0 +i[2] => a~9.IN1 +i[2] => b~2.IN1 +i[2] => a~10.IN1 +i[2] => a~11.IN1 +i[3] => _.IN0 +i[3] => _.IN0 +i[3] => _.IN0 +i[3] => _.IN0 +i[3] => _.IN0 +i[3] => _.IN0 +i[3] => _.IN0 +i[3] => _.IN0 +i[3] => a~6.IN0 +i[3] => a~7.IN0 +i[3] => a~8.IN0 +i[3] => c~0.IN0 +i[3] => a~9.IN0 +i[3] => b~2.IN0 +i[3] => a~10.IN0 +i[3] => a~11.IN0 +a <= a.DB_MAX_OUTPUT_PORT_TYPE +b <= b.DB_MAX_OUTPUT_PORT_TYPE +c <= c.DB_MAX_OUTPUT_PORT_TYPE +d <= d.DB_MAX_OUTPUT_PORT_TYPE +e <= e.DB_MAX_OUTPUT_PORT_TYPE +f <= f.DB_MAX_OUTPUT_PORT_TYPE +g <= g.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/YL_pushcounter/db/YL_pushcounter.hif b/YL_pushcounter/db/YL_pushcounter.hif new file mode 100644 index 0000000000000000000000000000000000000000..618837f541cde4d50ba1aa6461d5f4aeeb37cded GIT binary patch literal 595 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst_4000700000000
inst3000100000000
inst14101511100000
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"*******************************************************************" 0 0 "Quartus II" 0 -1 1588563869580 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588563869580 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 11:44:29 2020 " "Processing started: Mon May 04 11:44:29 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588563869580 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588563869580 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_pushcounter -c YL_pushcounter " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_pushcounter -c YL_pushcounter" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588563869581 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588563870392 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_pushcounter.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_pushcounter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 pulsar " "Found entity 1: pulsar" { } { { "YL_pushcounter.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588563870491 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588563870491 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_pushcounter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_pushcounter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_pushcounter " "Found entity 1: YL_pushcounter" { } { { "YL_pushcounter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588563870502 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588563870502 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_counter.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dec_count " "Found entity 1: dec_count" { } { { "YL_counter.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_counter.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588563870514 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588563870514 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segment.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segment.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7segment " "Found entity 1: 7segment" { } { { "YL_7segment.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_7segment.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588563870536 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588563870536 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_pushcounter " "Elaborating entity \"YL_pushcounter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588563870634 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst1 " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst1\"" { } { { "YL_pushcounter.bdf" "inst1" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.bdf" { { 80 520 680 192 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588563870641 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulsar pulsar:inst " "Elaborating entity \"pulsar\" for hierarchy \"pulsar:inst\"" { } { { "YL_pushcounter.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.bdf" { { 80 272 400 192 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588563870649 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7segment 7segment:inst_ " "Elaborating entity \"7segment\" for hierarchy \"7segment:inst_\"" { } { { "YL_pushcounter.bdf" "inst_" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.bdf" { { 80 776 904 256 "inst_" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588563870655 ""} +{ "Warning" "WSMP_SMP_MACHINE_NON_UNIQUE_CODE_WARN" "\|YL_pushcounter\|pulsar:inst\|s0 \|YL_pushcounter\|pulsar:inst\|s1 " "State bit assignments are not unique for state \"\|YL_pushcounter\|pulsar:inst\|s0\" and state \"\|YL_pushcounter\|pulsar:inst\|s1\"" { } { { "YL_pushcounter.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.tdf" 7 2 0 } } } 0 284004 "State bit assignments are not unique for state \"%1!s!\" and state \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588563870906 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1588563871351 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1588563871585 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588563871585 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "35 " "Implemented 35 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1588563871690 ""} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Implemented 12 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1588563871690 ""} { "Info" "ICUT_CUT_TM_LCELLS" "20 " "Implemented 20 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1588563871690 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1588563871690 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4605 " "Peak virtual memory: 4605 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588563871724 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 11:44:31 2020 " "Processing ended: Mon May 04 11:44:31 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588563871724 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588563871724 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588563871724 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588563871724 ""} diff --git a/YL_pushcounter/db/YL_pushcounter.map.rdb b/YL_pushcounter/db/YL_pushcounter.map.rdb new file mode 100644 index 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06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588564569727 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 11:56:09 2020 " "Processing started: Mon May 04 11:56:09 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588564569727 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588564569727 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --simulation_results_format=VWF YL_pushcounter -c YL_pushcounter " "Command: quartus_sim --simulation_results_format=VWF YL_pushcounter -c YL_pushcounter" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588564569727 ""} +{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.vwf " "Using vector source file \"C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.vwf\"" { } { } 0 324025 "Using vector source file \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588564570064 ""} +{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|YL_pushcounter\|pulsar:inst\|s3 " "Can't display state machine states -- register holding state machine bit \"\|YL_pushcounter\|pulsar:inst\|s3\" was synthesized away" { } { } 0 328028 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "Quartus II" 0 -1 1588564570150 ""} +{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." { } { } 0 310004 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "Quartus II" 0 -1 1588564570158 ""} } { } 0 310003 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "Quartus II" 0 -1 1588564570158 ""} +{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Simulation partitioned into 1 sub-simulations" { } { } 0 310002 "Simulation partitioned into %1!d! sub-simulations" 0 0 "Quartus II" 0 -1 1588564570186 ""} +{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" " 77.27 % " "Simulation coverage is 77.27 %" { } { } 0 328053 "Simulation coverage is %1!s!" 0 0 "Quartus II" 0 -1 1588564570188 ""} +{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "364 " "Number of transitions in simulation is 364" { } { } 0 328052 "Number of transitions in simulation is %1!s!" 0 0 "Quartus II" 0 -1 1588564570188 ""} +{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "YL_pushcounter.sim.vwf " "Vector file YL_pushcounter.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." { } { } 0 324045 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0 "Quartus II" 0 -1 1588564570190 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Simulator was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4484 " "Peak virtual memory: 4484 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588564570266 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 11:56:10 2020 " "Processing ended: Mon May 04 11:56:10 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588564570266 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588564570266 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588564570266 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588564570266 ""} diff --git a/YL_pushcounter/db/YL_pushcounter.sim.rdb b/YL_pushcounter/db/YL_pushcounter.sim.rdb new file mode 100644 index 0000000000000000000000000000000000000000..b911f6d0abe820e65942e682888341601cc4c95f GIT binary patch literal 2984 zcmV;Z3s>|J000233jqKC0CNCy073u&09Ivkb7^mGATcv8FfK75LUn0uWFRs#G9WNE zFEKJNGB7bSAX8;>c4=c}AW&grYalToQ%WFLWnv&jWNCD1Z*Jf(00000005K<00000 z005=|00000005{900000004La>{|J6+sGA`dsn^NMek#ZZFdvYwj|q0y7_6nvK<)p zg|(7&5d;B6j%3yphsznt)gtiz&n-~&PQN!Z6e)_5C^;#x3lpHo;k^0Y%$qmwvR}P= z_3FR&uHjl+t9=iTbAONoj`BswKID;z74;RbwJ+hze=zvpxc`M4@1NrFDL}rCE(;>! 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%1!s!" 0 0 "Quartus II" 0 -1 1588563884911 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_pushcounter -c YL_pushcounter " "Command: quartus_sta YL_pushcounter -c YL_pushcounter" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588563884912 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588563885135 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588563885403 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588563885451 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588563885451 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_pushcounter.sdc " "Synopsys Design Constraints File file not found: 'YL_pushcounter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588563885571 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588563885572 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885573 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885573 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588563885576 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588563885594 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588563885600 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.228 " "Worst-case setup slack is -1.228" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.228 -4.456 clk " " -1.228 -4.456 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885603 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588563885603 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.445 " "Worst-case hold slack is 0.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885607 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885607 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.445 0.000 clk " " 0.445 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885607 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588563885607 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588563885611 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588563885614 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885626 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885626 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -10.185 clk " " -1.631 -10.185 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885626 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588563885626 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588563885658 ""} +{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588563885661 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.159 " "Worst-case setup slack is 0.159" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885683 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885683 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.159 0.000 clk " " 0.159 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885683 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588563885683 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885687 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885687 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " " 0.215 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885687 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588563885687 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588563885691 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588563885697 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588563885698 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -8.380 clk " " -1.380 -8.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588563885701 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588563885701 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588563885731 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588563885757 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588563885758 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4546 " "Peak virtual memory: 4546 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588563885842 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 11:44:45 2020 " "Processing ended: Mon May 04 11:44:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588563885842 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588563885842 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588563885842 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 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{ { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588563862094 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 11:44:21 2020 " "Processing started: Mon May 04 11:44:21 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588563862094 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588563862094 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_pushcounter -c YL_pushcounter --generate_symbol=C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_7segment.tdf " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_pushcounter -c YL_pushcounter --generate_symbol=C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_7segment.tdf" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588563862095 ""} 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a/YL_pushcounter/dec_count.bsf b/YL_pushcounter/dec_count.bsf new file mode 100644 index 0000000..ec6f971 --- /dev/null +++ b/YL_pushcounter/dec_count.bsf @@ -0,0 +1,71 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 176 128) + (text "dec_count" (rect 5 0 46 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "enc" (rect 0 0 14 12)(font "Arial" )) + (text "enc" (rect 21 27 35 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "ent" (rect 0 0 11 12)(font "Arial" )) + (text "ent" (rect 21 43 32 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 59 31 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "clear" (rect 0 0 18 12)(font "Arial" )) + (text "clear" (rect 21 75 39 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "value[3..0]" (rect 0 0 41 12)(font "Arial" )) + (text "value[3..0]" (rect 98 27 139 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 48) + (output) + (text "rco" (rect 0 0 12 12)(font "Arial" )) + (text "rco" (rect 127 43 139 55)(font "Arial" )) + (line (pt 160 48)(pt 144 48)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 144 96)(line_width 1)) + ) +) diff --git a/YL_pushcounter/incremental_db/README b/YL_pushcounter/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/YL_pushcounter/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.db_info b/YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.db_info new file mode 100644 index 0000000..f6dbd82 --- /dev/null +++ b/YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Mon May 04 11:40:08 2020 diff --git a/YL_pushcounter/incremental_db/compiled_partitions/YL_pushcounter.root_partition.cmp.ammdb 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Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.sof + 6. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon May 04 11:44:43 2020 ; +; Revision Name ; YL_pushcounter ; +; Top-level Entity Name ; YL_pushcounter ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.sof ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.pof ; ++------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.sof ; ++----------------+---------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------------------------------------------+ +; Device ; EP2C20F484C7 ; +; JTAG usercode ; 0x001B3D89 ; +; Checksum ; 0x001B3D89 ; ++----------------+---------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.pof ; ++--------------------+-----------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+-----------------------------------------------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1DD957E7 ; +; Compression Ratio ; 3 ; ++--------------------+-----------------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 11:44:41 2020 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_pushcounter -c YL_pushcounter +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4558 megabytes + Info: Processing ended: Mon May 04 11:44:43 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_pushcounter/output_files/YL_pushcounter.done b/YL_pushcounter/output_files/YL_pushcounter.done new file mode 100644 index 0000000..8243308 --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.done @@ -0,0 +1 @@ +Mon May 04 11:44:46 2020 diff --git a/YL_pushcounter/output_files/YL_pushcounter.fit.rpt b/YL_pushcounter/output_files/YL_pushcounter.fit.rpt new file mode 100644 index 0000000..06c111d --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.fit.rpt @@ -0,0 +1,1237 @@ +Fitter report for YL_pushcounter +Mon May 04 11:44:39 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. Output Pin Default Load For Reported TCO + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Control Signals + 20. Global & Other Fast Signals + 21. Non-Global High Fan-Out Signals + 22. Other Routing Usage Summary + 23. LAB Logic Elements + 24. LAB-wide Signals + 25. LAB Signals Sourced + 26. LAB Signals Sourced Out + 27. LAB Distinct Inputs + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Mon May 04 11:44:39 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_pushcounter ; +; Top-level Entity Name ; YL_pushcounter ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 20 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 20 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 7 / 18,752 ( < 1 % ) ; +; Total registers ; 7 ; +; Total pins ; 15 / 315 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C20F484C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 48 ( 0.00 % ) ; +; -- Achieved ; 0 / 48 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 45 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 20 / 18,752 ( < 1 % ) ; +; -- Combinational with no register ; 13 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 7 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 13 ; +; -- 3 input functions ; 3 ; +; -- <=2 input functions ; 4 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 20 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 7 / 19,649 ( < 1 % ) ; +; -- Dedicated logic registers ; 7 / 18,752 ( < 1 % ) ; +; -- I/O registers ; 0 / 897 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 1,172 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 15 / 315 ( 5 % ) ; +; -- Clock pins ; 1 / 8 ( 13 % ) ; +; ; ; +; Global signals ; 2 ; +; M4Ks ; 0 / 52 ( 0 % ) ; +; Total block memory bits ; 0 / 239,616 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 14 ; +; Highest non-global fan-out ; 14 ; +; Total fan-out ; 99 ; +; Average fan-out ; 2.11 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 20 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; -- Combinational with no register ; 13 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 7 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 13 ; 0 ; +; -- 3 input functions ; 3 ; 0 ; +; -- <=2 input functions ; 4 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 20 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 7 ; 0 ; +; -- Dedicated logic registers ; 7 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 1172 ( < 1 % ) ; 0 / 1172 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 15 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; 0 / 52 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 2 / 20 ( 10 % ) ; 0 / 20 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 99 ; 0 ; +; -- Registered Connections ; 56 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 3 ; 0 ; +; -- Output Ports ; 12 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; clk ; M1 ; 1 ; 0 ; 13 ; 2 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; key ; G5 ; 2 ; 0 ; 22 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; reset ; M2 ; 1 ; 0 ; 13 ; 3 ; 6 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; OUTPUT_A ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_B ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_C ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_D ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_E ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_F ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; OUTPUT_G ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; rco ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[0] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[1] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[2] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[3] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 2 / 41 ( 5 % ) ; 3.3V ; -- ; +; 2 ; 15 / 33 ( 45 % ) ; 3.3V ; -- ; +; 3 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; +; 4 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 5 ; 0 / 39 ( 0 % ) ; 3.3V ; -- ; +; 6 ; 1 / 36 ( 3 % ) ; 3.3V ; -- ; +; 7 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 8 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 306 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A8 ; 304 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A9 ; 298 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A10 ; 293 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A11 ; 287 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 265 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 251 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 249 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 82 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA4 ; 85 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA5 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA6 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA7 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA11 ; 122 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 130 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 144 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 83 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB4 ; 84 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB5 ; 88 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB6 ; 96 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB7 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB12 ; 127 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB13 ; 129 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 305 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B8 ; 303 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B9 ; 297 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B10 ; 292 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B11 ; 286 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B14 ; 278 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 264 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B18 ; 250 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 8 ; 2 ; OUTPUT_A ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; C2 ; 9 ; 2 ; OUTPUT_G ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C7 ; 315 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; 310 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C10 ; 296 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C14 ; 260 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 14 ; 2 ; value[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D2 ; 15 ; 2 ; value[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D4 ; 3 ; 2 ; value[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D5 ; 4 ; 2 ; OUTPUT_F ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D6 ; 5 ; 2 ; OUTPUT_E ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 302 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 289 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 267 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 259 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; 255 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 6 ; 2 ; OUTPUT_C ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; E4 ; 7 ; 2 ; OUTPUT_D ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; 266 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E15 ; 256 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; 13 ; 2 ; value[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; F4 ; 10 ; 2 ; OUTPUT_B ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 276 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F13 ; 269 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 268 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 262 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 2 ; key ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; G6 ; 11 ; 2 ; rco ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 261 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 252 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H2 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; H4 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H6 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 274 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; 263 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H14 ; 257 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H15 ; 253 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J1 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J2 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; 258 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M1 ; 41 ; 1 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M2 ; 42 ; 1 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P6 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 187 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R1 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R2 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R5 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R6 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R7 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R8 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R10 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R11 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; R21 ; 190 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R22 ; 191 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T1 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T2 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T3 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T5 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T6 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T7 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T8 ; 90 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T12 ; 131 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T15 ; 147 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 188 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T22 ; 189 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U1 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U2 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U3 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U4 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U8 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U21 ; 182 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U22 ; 183 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V9 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 180 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 181 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W2 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W7 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W8 ; 100 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W9 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W21 ; 174 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; 175 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y3 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y4 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y5 ; 86 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y6 ; 87 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y7 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y13 ; 133 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y21 ; 178 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 179 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------+--------------+ +; |YL_pushcounter ; 20 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; 13 (0) ; 0 (0) ; 7 (0) ; |YL_pushcounter ; work ; +; |7segment:inst_| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |YL_pushcounter|7segment:inst_ ; work ; +; |dec_count:inst1| ; 9 (9) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 4 (4) ; |YL_pushcounter|dec_count:inst1 ; work ; +; |pulsar:inst| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |YL_pushcounter|pulsar:inst ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++----------+----------+---------------+---------------+-----------------------+-----+ +; rco ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_A ; Output ; -- ; -- ; -- ; -- ; +; value[3] ; Output ; -- ; -- ; -- ; -- ; +; value[2] ; Output ; -- ; -- ; -- ; -- ; +; value[1] ; Output ; -- ; -- ; -- ; -- ; +; value[0] ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_B ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_C ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_D ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_E ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_F ; Output ; -- ; -- ; -- ; -- ; +; OUTPUT_G ; Output ; -- ; -- ; -- ; -- ; +; reset ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; clk ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; key ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; ++----------+----------+---------------+---------------+-----------------------+-----+ + + ++-------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------+-------------------+---------+ +; reset ; ; ; +; clk ; ; ; +; key ; ; ; +; - pulsar:inst|s2~0 ; 1 ; 6 ; +; - pulsar:inst|s1~0 ; 1 ; 6 ; +; - pulsar:inst|s0~0 ; 1 ; 6 ; ++-------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 7 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; reset ; PIN_M2 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ; ++-------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 7 ; Global Clock ; GCLK3 ; -- ; +; reset ; PIN_M2 ; 3 ; Global Clock ; GCLK1 ; -- ; ++-------+----------+---------+----------------------+------------------+---------------------------+ + + ++--------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------+---------+ +; dec_count:inst1|count[1] ; 14 ; +; dec_count:inst1|count[0] ; 13 ; +; dec_count:inst1|count[2] ; 12 ; +; dec_count:inst1|count[3] ; 10 ; +; reset ; 5 ; +; pulsar:inst|s2 ; 5 ; +; key ; 3 ; +; 7segment:inst_|a~12 ; 3 ; +; dec_count:inst1|count[3]~4 ; 2 ; +; pulsar:inst|s0~0 ; 1 ; +; pulsar:inst|s1~0 ; 1 ; +; pulsar:inst|s0 ; 1 ; +; pulsar:inst|s2~0 ; 1 ; +; pulsar:inst|s1 ; 1 ; +; dec_count:inst1|count[1]~7 ; 1 ; +; dec_count:inst1|count[1]~6 ; 1 ; +; dec_count:inst1|count[2]~5 ; 1 ; +; dec_count:inst1|op_1~0 ; 1 ; +; dec_count:inst1|count[2]~3 ; 1 ; +; dec_count:inst1|count[0]~2 ; 1 ; +; dec_count:inst1|count[3]~1 ; 1 ; +; dec_count:inst1|count[3]~0 ; 1 ; +; 7segment:inst_|g~0 ; 1 ; +; 7segment:inst_|f~0 ; 1 ; +; 7segment:inst_|e~0 ; 1 ; +; 7segment:inst_|d~0 ; 1 ; +; 7segment:inst_|c~1 ; 1 ; +; 7segment:inst_|b~3 ; 1 ; +; 7segment:inst_|a~13 ; 1 ; ++----------------------------+---------+ + + ++-----------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-----------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-----------------------+ +; Block interconnects ; 25 / 54,004 ( < 1 % ) ; +; C16 interconnects ; 0 / 2,100 ( 0 % ) ; +; C4 interconnects ; 11 / 36,000 ( < 1 % ) ; +; Direct links ; 11 / 54,004 ( < 1 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Local interconnects ; 12 / 18,752 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,900 ( 0 % ) ; +; R4 interconnects ; 5 / 46,920 ( < 1 % ) ; ++-----------------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 10.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 2) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 1 ; +; 1 Clock ; 1 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 13.50) ; Number of LABs (Total = 2) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 6.00) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 4.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 2 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP2C20F484C7 for design "YL_pushcounter" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP2C15AF484C7 is compatible + Info (176445): Device EP2C35F484C7 is compatible + Info (176445): Device EP2C50F484C7 is compatible +Info (169124): Fitter converted 3 user pins into dedicated programming pins + Info (169125): Pin ~ASDO~ is reserved at location C4 + Info (169125): Pin ~nCSO~ is reserved at location C3 + Info (169125): Pin ~LVDS91p/nCEO~ is reserved at location W20 +Critical Warning (169085): No exact pin location assignment(s) for 15 pins of 15 total pins + Info (169086): Pin rco not assigned to an exact location on the device + Info (169086): Pin OUTPUT_A not assigned to an exact location on the device + Info (169086): Pin value[3] not assigned to an exact location on the device + Info (169086): Pin value[2] not assigned to an exact location on the device + Info (169086): Pin value[1] not assigned to an exact location on the device + Info (169086): Pin value[0] not assigned to an exact location on the device + Info (169086): Pin OUTPUT_B not assigned to an exact location on the device + Info (169086): Pin OUTPUT_C not assigned to an exact location on the device + Info (169086): Pin OUTPUT_D not assigned to an exact location on the device + Info (169086): Pin OUTPUT_E not assigned to an exact location on the device + Info (169086): Pin OUTPUT_F not assigned to an exact location on the device + Info (169086): Pin OUTPUT_G not assigned to an exact location on the device + Info (169086): Pin reset not assigned to an exact location on the device + Info (169086): Pin clk not assigned to an exact location on the device + Info (169086): Pin key not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_pushcounter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node reset (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node dec_count:inst1|count[3]~1 + Info (176357): Destination node dec_count:inst1|count[0]~2 + Info (176357): Destination node dec_count:inst1|count[2]~3 + Info (176357): Destination node dec_count:inst1|count[3]~4 + Info (176357): Destination node dec_count:inst1|count[1]~7 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 13 (unused VREF, 3.3V VCCIO, 1 input, 12 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y14 to location X11_Y27 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.30 seconds. +Info (306004): Started post-fitting delay annotation +Warning (306006): Found 12 output pins without output pin load capacitance assignment + Info (306007): Pin "rco" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_A" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_B" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_C" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_D" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_E" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_F" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "OUTPUT_G" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info (306005): Delay annotation completed successfully +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 4844 megabytes + Info: Processing ended: Mon May 04 11:44:40 2020 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:07 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/output_files/YL_pushcounter.fit.smsg. + + diff --git a/YL_pushcounter/output_files/YL_pushcounter.fit.smsg b/YL_pushcounter/output_files/YL_pushcounter.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/YL_pushcounter/output_files/YL_pushcounter.fit.summary b/YL_pushcounter/output_files/YL_pushcounter.fit.summary new file mode 100644 index 0000000..b1bc6a1 --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon May 04 11:44:39 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_pushcounter +Top-level Entity Name : YL_pushcounter +Family : Cyclone II +Device : EP2C20F484C7 +Timing Models : Final +Total logic elements : 20 / 18,752 ( < 1 % ) + Total combinational functions : 20 / 18,752 ( < 1 % ) + Dedicated logic registers : 7 / 18,752 ( < 1 % ) +Total registers : 7 +Total pins : 15 / 315 ( 5 % ) +Total virtual pins : 0 +Total memory bits : 0 / 239,616 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/YL_pushcounter/output_files/YL_pushcounter.flow.rpt b/YL_pushcounter/output_files/YL_pushcounter.flow.rpt new file mode 100644 index 0000000..16d8957 --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.flow.rpt @@ -0,0 +1,122 @@ +Flow report for YL_pushcounter +Mon May 04 11:44:45 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Mon May 04 11:44:43 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_pushcounter ; +; Top-level Entity Name ; YL_pushcounter ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 20 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 20 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 7 / 18,752 ( < 1 % ) ; +; Total registers ; 7 ; +; Total pins ; 15 / 315 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 05/04/2020 11:44:30 ; +; Main task ; Compilation ; +; Revision Name ; YL_pushcounter ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 345052807169.158856387018248 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4594 MB ; 00:00:02 ; +; Fitter ; 00:00:07 ; 1.0 ; 4844 MB ; 00:00:07 ; +; Assembler ; 00:00:02 ; 1.0 ; 4558 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4546 MB ; 00:00:01 ; +; Total ; 00:00:12 ; -- ; -- ; 00:00:12 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off YL_pushcounter -c YL_pushcounter +quartus_fit --read_settings_files=off --write_settings_files=off YL_pushcounter -c YL_pushcounter +quartus_asm --read_settings_files=off --write_settings_files=off YL_pushcounter -c YL_pushcounter +quartus_sta YL_pushcounter -c YL_pushcounter + + + diff --git a/YL_pushcounter/output_files/YL_pushcounter.jdi b/YL_pushcounter/output_files/YL_pushcounter.jdi new file mode 100644 index 0000000..24e5d88 --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/YL_pushcounter/output_files/YL_pushcounter.map.rpt b/YL_pushcounter/output_files/YL_pushcounter.map.rpt new file mode 100644 index 0000000..7c53177 --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.map.rpt @@ -0,0 +1,296 @@ +Analysis & Synthesis report for YL_pushcounter +Mon May 04 11:44:31 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. State Machine - |YL_pushcounter|pulsar:inst|ss + 9. Registers Removed During Synthesis + 10. General Register Statistics + 11. Elapsed Time Per Partition + 12. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon May 04 11:44:31 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_pushcounter ; +; Top-level Entity Name ; YL_pushcounter ; +; Family ; Cyclone II ; +; Total logic elements ; 20 ; +; Total combinational functions ; 20 ; +; Dedicated logic registers ; 7 ; +; Total registers ; 7 ; +; Total pins ; 15 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; YL_pushcounter ; YL_pushcounter ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+ +; YL_pushcounter.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.tdf ; ; +; YL_pushcounter.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.bdf ; ; +; YL_counter.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_counter.tdf ; ; +; YL_7segment.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_7segment.tdf ; ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+--------------------------+ +; Resource ; Usage ; ++---------------------------------------------+--------------------------+ +; Estimated Total logic elements ; 20 ; +; ; ; +; Total combinational functions ; 20 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 13 ; +; -- 3 input functions ; 3 ; +; -- <=2 input functions ; 4 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 20 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 7 ; +; -- Dedicated logic registers ; 7 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 15 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; dec_count:inst1|count[1] ; +; Maximum fan-out ; 14 ; +; Total fan-out ; 97 ; +; Average fan-out ; 2.31 ; ++---------------------------------------------+--------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+--------------+ +; |YL_pushcounter ; 20 (0) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; |YL_pushcounter ; work ; +; |7segment:inst_| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_pushcounter|7segment:inst_ ; work ; +; |dec_count:inst1| ; 9 (9) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_pushcounter|dec_count:inst1 ; work ; +; |pulsar:inst| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_pushcounter|pulsar:inst ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + +Encoding Type: One-Hot ++------------------------------------------------+ +; State Machine - |YL_pushcounter|pulsar:inst|ss ; ++------+----+----+----+--------------------------+ +; Name ; s3 ; s1 ; s0 ; s2 ; ++------+----+----+----+--------------------------+ +; s0 ; 0 ; 0 ; 0 ; 0 ; +; s1 ; 0 ; 1 ; 1 ; 0 ; +; s2 ; 0 ; 0 ; 1 ; 1 ; +; s3 ; 1 ; 0 ; 1 ; 0 ; ++------+----+----+----+--------------------------+ + + ++------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+--------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+--------------------+ +; pulsar:inst|s3 ; Lost fanout ; +; Total Number of Removed Registers = 1 ; ; ++---------------------------------------+--------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 7 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 3 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 11:44:29 2020 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_pushcounter -c YL_pushcounter +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file yl_pushcounter.tdf + Info (12023): Found entity 1: pulsar +Info (12021): Found 1 design units, including 1 entities, in source file yl_pushcounter.bdf + Info (12023): Found entity 1: YL_pushcounter +Info (12021): Found 1 design units, including 1 entities, in source file yl_counter.tdf + Info (12023): Found entity 1: dec_count +Info (12021): Found 1 design units, including 1 entities, in source file yl_7segment.tdf + Info (12023): Found entity 1: 7segment +Info (12127): Elaborating entity "YL_pushcounter" for the top level hierarchy +Info (12128): Elaborating entity "dec_count" for hierarchy "dec_count:inst1" +Info (12128): Elaborating entity "pulsar" for hierarchy "pulsar:inst" +Info (12128): Elaborating entity "7segment" for hierarchy "7segment:inst_" +Warning (284004): State bit assignments are not unique for state "|YL_pushcounter|pulsar:inst|s0" and state "|YL_pushcounter|pulsar:inst|s1" +Info (17049): 1 registers lost all their fanouts during netlist optimizations. +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 35 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 3 input pins + Info (21059): Implemented 12 output pins + Info (21061): Implemented 20 logic cells +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 4605 megabytes + Info: Processing ended: Mon May 04 11:44:31 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_pushcounter/output_files/YL_pushcounter.map.summary b/YL_pushcounter/output_files/YL_pushcounter.map.summary new file mode 100644 index 0000000..212d9ee --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon May 04 11:44:31 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_pushcounter +Top-level Entity Name : YL_pushcounter +Family : Cyclone II +Total logic elements : 20 + Total combinational functions : 20 + Dedicated logic registers : 7 +Total registers : 7 +Total pins : 15 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/YL_pushcounter/output_files/YL_pushcounter.pin b/YL_pushcounter/output_files/YL_pushcounter.pin new file mode 100644 index 0000000..d987f56 --- /dev/null +++ b/YL_pushcounter/output_files/YL_pushcounter.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "YL_pushcounter" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +GND* : A11 : : : : 3 : +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +GND* : AA3 : : : : 8 : +GND* : AA4 : : : : 8 : +GND* : AA5 : : : : 8 : +GND* : AA6 : : : : 8 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +GND* : AA11 : : : : 8 : +GND* : AA12 : : : : 7 : +GND* : AA13 : : : : 7 : +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +GND* : AB3 : : : : 8 : +GND* : AB4 : : : : 8 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +GND* : AB12 : : : : 7 : +GND* : AB13 : : : : 7 : +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +GND* : B11 : : : : 3 : +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +GND* : B14 : : : : 4 : +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +GND* : B17 : : : : 4 : +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +OUTPUT_A : C1 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_G : C2 : output : 3.3-V LVTTL : : 2 : N +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +GND* : C7 : : : : 3 : +GND : C8 : gnd : : : : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +GND* : C14 : : : : 4 : +GND : C15 : gnd : : : : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +GND* : C21 : : : : 5 : +GND* : C22 : : : : 5 : +value[2] : D1 : output : 3.3-V LVTTL : : 2 : N +value[1] : D2 : output : 3.3-V LVTTL : : 2 : N +GND* : D3 : : : : 2 : +value[0] : D4 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_F : D5 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_E : D6 : output : 3.3-V LVTTL : : 2 : N +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +GND* : D9 : : : : 3 : +GND : D10 : gnd : : : : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +GND* : D14 : : : : 4 : +GND* : D15 : : : : 4 : +GND* : D16 : : : : 4 : +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +GND* : D20 : : : : 5 : +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +OUTPUT_C : E3 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_D : E4 : output : 3.3-V LVTTL : : 2 : N +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +GND* : E14 : : : : 4 : +GND* : E15 : : : : 4 : +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +GND* : F1 : : : : 2 : +GND* : F2 : : : : 2 : +value[3] : F3 : output : 3.3-V LVTTL : : 2 : N +OUTPUT_B : F4 : output : 3.3-V LVTTL : : 2 : N +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +GND* : F12 : : : : 4 : +GND* : F13 : : : : 4 : +GND* : F14 : : : : 4 : +GND* : F15 : : : : 4 : +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +GND* : G3 : : : : 2 : +GND : G4 : gnd : : : : +key : G5 : input : 3.3-V LVTTL : : 2 : N +rco : G6 : output : 3.3-V LVTTL : : 2 : N +GND* : G7 : : : : 3 : +GND* : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +GND* : G15 : : : : 4 : +GND* : G16 : : : : 4 : +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +GND* : H4 : : : : 2 : +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +GND* : H12 : : : : 4 : +GND* : H13 : : : : 4 : +GND* : H14 : : : : 4 : +GND* : H15 : : : : 4 : +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +GND* : J1 : : : : 2 : +GND* : J2 : : : : 2 : +NC : J3 : : : : : +GND* : J4 : : : : 2 : +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +GND* : J14 : : : : 4 : +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +GND+ : L1 : : : : 2 : +GND+ : L2 : : : : 2 : +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +GND* : L8 : : : : 2 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +GND+ : L21 : : : : 5 : +GND+ : L22 : : : : 5 : +clk : M1 : input : 3.3-V LVTTL : : 1 : N +reset : M2 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +GND+ : M22 : : : : 6 : +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +GND* : P5 : : : : 1 : +GND* : P6 : : : : 1 : +VCCIO1 : P7 : power : : 3.3V : 1 : +GND* : P8 : : : : 8 : +GND* : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +GND* : P18 : : : : 6 : +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +GND* : R1 : : : : 1 : +GND* : R2 : : : : 1 : +GND : R3 : gnd : : : : +NC : R4 : : : : : +GND* : R5 : : : : 1 : +GND* : R6 : : : : 1 : +GND* : R7 : : : : 1 : +GND* : R8 : : : : 1 : +GND* : R9 : : : : 8 : +GND* : R10 : : : : 8 : +GND* : R11 : : : : 8 : +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +GND* : T1 : : : : 1 : +GND* : T2 : : : : 1 : +GND* : T3 : : : : 1 : +VCCIO1 : T4 : power : : 3.3V : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 8 : +GND* : T8 : : : : 8 : +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +GND* : T12 : : : : 7 : +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +GND* : T15 : : : : 7 : +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +GND* : U8 : : : : 8 : +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND : V3 : gnd : : : : +GND* : V4 : : : : 1 : +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +GND* : V8 : : : : 8 : +GND* : V9 : : : : 8 : +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +VCCIO8 : W6 : power : : 3.3V : 8 : +GND* : W7 : : : : 8 : +GND* : W8 : : : : 8 : +GND* : W9 : : : : 8 : +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +GND* : Y1 : : : : 1 : +GND* : Y2 : : : : 1 : +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +GND* : Y5 : : : : 8 : +GND* : Y6 : : : : 8 : +GND* : Y7 : : : : 8 : +GND : Y8 : gnd : : : : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power : : 3.3V : 7 : +GND* : Y13 : : : : 7 : +GND* : Y14 : : : : 7 : +GND : Y15 : gnd : : : : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 6 : +GND* : Y19 : : : : 6 : +GND* : Y20 : : : : 6 : +GND* : Y21 : : : : 6 : +GND* : Y22 : : : : 6 : diff --git a/YL_pushcounter/output_files/YL_pushcounter.pof b/YL_pushcounter/output_files/YL_pushcounter.pof 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Legal Notice + 2. Simulator Summary + 3. Simulator Settings + 4. Simulation Waveforms + 5. Coverage Summary + 6. Complete 1/0-Value Coverage + 7. Missing 1-Value Coverage + 8. Missing 0-Value Coverage + 9. Simulator INI Usage + 10. Simulator Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------+ +; Simulator Summary ; ++-----------------------------+--------------+ +; Type ; Value ; ++-----------------------------+--------------+ +; Simulation Start Time ; 0 ps ; +; Simulation End Time ; 1.0 us ; +; Simulation Netlist Size ; 44 nodes ; +; Simulation Coverage ; 77.27 % ; +; Total Number of Transitions ; 364 ; +; Simulation Breakpoints ; 0 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Simulator Settings ; ++--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+---------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+---------------+ +; Simulation mode ; Timing ; Timing ; +; Start time ; 0 ns ; 0 ns ; +; Simulation results format ; VWF ; ; +; Vector input source ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.vwf ; ; +; Add pins automatically to simulation output waveforms ; On ; On ; +; Check outputs ; Off ; Off ; +; Report simulation coverage ; On ; On ; +; Display complete 1/0 value coverage report ; On ; On ; +; Display missing 1-value coverage report ; On ; On ; +; Display missing 0-value coverage report ; On ; On ; +; Detect setup and hold time violations ; Off ; Off ; +; Detect glitches ; Off ; Off ; +; Disable timing delays in Timing Simulation ; Off ; Off ; +; Generate Signal Activity File ; Off ; Off ; +; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ; +; Group bus channels in simulation results ; Off ; Off ; +; Preserve fewer signal transitions to reduce memory requirements ; On ; On ; +; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ; +; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ; +; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ; +; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ; ++--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+---------------+ + + ++----------------------+ +; Simulation Waveforms ; ++----------------------+ +Waveform report data cannot be output to ASCII. +Please use Quartus II 64-Bit to view the waveform report data. + + ++--------------------------------------------------------------------+ +; Coverage Summary ; ++-----------------------------------------------------+--------------+ +; Type ; Value ; ++-----------------------------------------------------+--------------+ +; Total coverage as a percentage ; 77.27 % ; +; Total nodes checked ; 44 ; +; Total output ports checked ; 44 ; +; Total output ports with complete 1/0-value coverage ; 34 ; +; Total output ports with no 1/0-value coverage ; 10 ; +; Total output ports with no 1-value coverage ; 10 ; +; Total output ports with no 0-value coverage ; 10 ; ++-----------------------------------------------------+--------------+ + + +The following table displays output ports that toggle between 1 and 0 during simulation. ++------------------------------------------------------------------------------------------------------------+ +; Complete 1/0-Value Coverage ; ++--------------------------------------------+--------------------------------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++--------------------------------------------+--------------------------------------------+------------------+ +; |YL_pushcounter|dec_count:inst1|count[0] ; |YL_pushcounter|dec_count:inst1|count[0] ; regout ; +; |YL_pushcounter|dec_count:inst1|count[1] ; |YL_pushcounter|dec_count:inst1|count[1] ; regout ; +; |YL_pushcounter|7segment:inst_|a~13 ; |YL_pushcounter|7segment:inst_|a~13 ; combout ; +; |YL_pushcounter|7segment:inst_|c~1 ; |YL_pushcounter|7segment:inst_|c~1 ; combout ; +; |YL_pushcounter|7segment:inst_|d~0 ; |YL_pushcounter|7segment:inst_|d~0 ; combout ; +; |YL_pushcounter|7segment:inst_|e~0 ; |YL_pushcounter|7segment:inst_|e~0 ; combout ; +; |YL_pushcounter|7segment:inst_|f~0 ; |YL_pushcounter|7segment:inst_|f~0 ; combout ; +; |YL_pushcounter|7segment:inst_|g~0 ; |YL_pushcounter|7segment:inst_|g~0 ; combout ; +; |YL_pushcounter|pulsar:inst|s2 ; |YL_pushcounter|pulsar:inst|s2 ; regout ; +; |YL_pushcounter|dec_count:inst1|count[3]~0 ; |YL_pushcounter|dec_count:inst1|count[3]~0 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[3]~1 ; |YL_pushcounter|dec_count:inst1|count[3]~1 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[0]~2 ; |YL_pushcounter|dec_count:inst1|count[0]~2 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[3]~4 ; |YL_pushcounter|dec_count:inst1|count[3]~4 ; combout ; +; |YL_pushcounter|dec_count:inst1|op_1~0 ; |YL_pushcounter|dec_count:inst1|op_1~0 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[1]~6 ; |YL_pushcounter|dec_count:inst1|count[1]~6 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[1]~7 ; |YL_pushcounter|dec_count:inst1|count[1]~7 ; combout ; +; |YL_pushcounter|pulsar:inst|s1 ; |YL_pushcounter|pulsar:inst|s1 ; regout ; +; |YL_pushcounter|pulsar:inst|s2~0 ; |YL_pushcounter|pulsar:inst|s2~0 ; combout ; +; |YL_pushcounter|pulsar:inst|s0 ; |YL_pushcounter|pulsar:inst|s0 ; regout ; +; |YL_pushcounter|pulsar:inst|s1~0 ; |YL_pushcounter|pulsar:inst|s1~0 ; combout ; +; |YL_pushcounter|pulsar:inst|s0~0 ; |YL_pushcounter|pulsar:inst|s0~0 ; combout ; +; |YL_pushcounter|OUTPUT_A ; |YL_pushcounter|OUTPUT_A ; padio ; +; |YL_pushcounter|value[1] ; |YL_pushcounter|value[1] ; padio ; +; |YL_pushcounter|value[0] ; |YL_pushcounter|value[0] ; padio ; +; |YL_pushcounter|OUTPUT_C ; |YL_pushcounter|OUTPUT_C ; padio ; +; |YL_pushcounter|OUTPUT_D ; |YL_pushcounter|OUTPUT_D ; padio ; +; |YL_pushcounter|OUTPUT_E ; |YL_pushcounter|OUTPUT_E ; padio ; +; |YL_pushcounter|OUTPUT_F ; |YL_pushcounter|OUTPUT_F ; padio ; +; |YL_pushcounter|OUTPUT_G ; |YL_pushcounter|OUTPUT_G ; padio ; +; |YL_pushcounter|reset ; |YL_pushcounter|reset~corein ; combout ; +; |YL_pushcounter|clk ; |YL_pushcounter|clk~corein ; combout ; +; |YL_pushcounter|key ; |YL_pushcounter|key~corein ; combout ; +; |YL_pushcounter|clk~clkctrl ; |YL_pushcounter|clk~clkctrl ; outclk ; +; |YL_pushcounter|reset~clkctrl ; |YL_pushcounter|reset~clkctrl ; outclk ; ++--------------------------------------------+--------------------------------------------+------------------+ + + +The following table displays output ports that do not toggle to 1 during simulation. ++------------------------------------------------------------------------------------------------------------+ +; Missing 1-Value Coverage ; ++--------------------------------------------+--------------------------------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++--------------------------------------------+--------------------------------------------+------------------+ +; |YL_pushcounter|dec_count:inst1|count[3] ; |YL_pushcounter|dec_count:inst1|count[3] ; regout ; +; |YL_pushcounter|dec_count:inst1|count[2] ; |YL_pushcounter|dec_count:inst1|count[2] ; regout ; +; |YL_pushcounter|7segment:inst_|a~12 ; |YL_pushcounter|7segment:inst_|a~12 ; combout ; +; |YL_pushcounter|7segment:inst_|b~3 ; |YL_pushcounter|7segment:inst_|b~3 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[2]~3 ; |YL_pushcounter|dec_count:inst1|count[2]~3 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[2]~5 ; |YL_pushcounter|dec_count:inst1|count[2]~5 ; combout ; +; |YL_pushcounter|rco ; |YL_pushcounter|rco ; padio ; +; |YL_pushcounter|value[3] ; |YL_pushcounter|value[3] ; padio ; +; |YL_pushcounter|value[2] ; |YL_pushcounter|value[2] ; padio ; +; |YL_pushcounter|OUTPUT_B ; |YL_pushcounter|OUTPUT_B ; padio ; ++--------------------------------------------+--------------------------------------------+------------------+ + + +The following table displays output ports that do not toggle to 0 during simulation. ++------------------------------------------------------------------------------------------------------------+ +; Missing 0-Value Coverage ; ++--------------------------------------------+--------------------------------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++--------------------------------------------+--------------------------------------------+------------------+ +; |YL_pushcounter|dec_count:inst1|count[3] ; |YL_pushcounter|dec_count:inst1|count[3] ; regout ; +; |YL_pushcounter|dec_count:inst1|count[2] ; |YL_pushcounter|dec_count:inst1|count[2] ; regout ; +; |YL_pushcounter|7segment:inst_|a~12 ; |YL_pushcounter|7segment:inst_|a~12 ; combout ; +; |YL_pushcounter|7segment:inst_|b~3 ; |YL_pushcounter|7segment:inst_|b~3 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[2]~3 ; |YL_pushcounter|dec_count:inst1|count[2]~3 ; combout ; +; |YL_pushcounter|dec_count:inst1|count[2]~5 ; |YL_pushcounter|dec_count:inst1|count[2]~5 ; combout ; +; |YL_pushcounter|rco ; |YL_pushcounter|rco ; padio ; +; |YL_pushcounter|value[3] ; |YL_pushcounter|value[3] ; padio ; +; |YL_pushcounter|value[2] ; |YL_pushcounter|value[2] ; padio ; +; |YL_pushcounter|OUTPUT_B ; |YL_pushcounter|OUTPUT_B ; padio ; ++--------------------------------------------+--------------------------------------------+------------------+ + + ++---------------------+ +; Simulator INI Usage ; ++--------+------------+ +; Option ; Usage ; ++--------+------------+ + + ++--------------------+ +; Simulator Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Simulator + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon May 04 11:56:09 2020 +Info: Command: quartus_sim --simulation_results_format=VWF YL_pushcounter -c YL_pushcounter +Info (324025): Using vector source file "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pushcounter/YL_pushcounter.vwf" +Warning (328028): Can't display state machine states -- register holding state machine bit "|YL_pushcounter|pulsar:inst|s3" was synthesized away +Info (310003): Option to preserve fewer signal transitions to reduce memory requirements is enabled + Info (310004): Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements. +Info (310002): Simulation partitioned into 1 sub-simulations +Info (328053): Simulation coverage is 77.27 % +Info (328052): Number of transitions in simulation is 364 +Info (324045): Vector file YL_pushcounter.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help. +Info: Quartus II 64-Bit Simulator was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4484 megabytes + Info: Processing ended: Mon May 04 11:56:10 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/YL_pushcounter/output_files/YL_pushcounter.sof b/YL_pushcounter/output_files/YL_pushcounter.sof new file mode 100644 index 0000000000000000000000000000000000000000..28d506de0486df2300f340fd9d176e2ee0b83ed5 GIT binary patch literal 476073 zcmeIb(a$W|ktdYj{chj+?78bLj}6ljemLD)j3vbQv&S6RrfAT1*vkcH65yz#a?AlL^a&Y~9DCtiTJeHb+o68pq|u*5H` zA}UXv$gGo@=d1kcW`tc;nUTNvMVzRN6Pa1xJ^e@j)*m#GPtoh9`48#+-~RdcfA+!8 z-*?~nj{E(u{VU&k_XGFspZwkT-u=^ee&+t&cYgN%yFdA{`^xYB&i(Iv#eM7N@BZoA z?yJB1Rd@gUU;fHhzx>tvul%n2qj!GxAHVy-Ui z_=9(T_B(&)?RT56zyGIifA77Y{p9bw^TQ9m_wJAXl z;;--G>t9v|_1WgHf8#g0v@}ioPyaPaawm86O|{7HlYlfoZ32>qZ^kuu^i{O9r3u3c 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z(Txomv&6+>G?1zAwMtoLuLT;#{^8^6fM1(fjBSdp(aI!hi`~W@g%}9~_G((2cX#XG z`E?enViSna>ki-}bQ#FO_R$(Az1YY7t{4eJDCh)We zDbdRnqKlT6?$<+ifoQ5q%Q$D9CAtdv?~~>;wwkCi?8}*l7oy$cU2f-~57zUHSz+VN z(H@>!2i`Z{c|@FDvYuctsT4u6#VW|Fy@|ffmPQX?z)}7&Qkgbv;miz>^A%FYRoBjR z2|ff=bcyo-Sh}0A)64dIe;$M4PrC?gqt!|$PoSFYt0U>BDo>|T0@G0PDPnsxR`4mZ zKI$b>44#pEQrc^WBF836tO>3NRRKmzU>ISF%2R=83A&T0wBMrf0kD`jz>2f60cO0P zHyE3;TWZ&!DYQ5tR@<^?cJy%ioas6-Fo>8 H00960s5c2N literal 0 HcmV?d00001 diff --git a/YL_dec_counter/db/YL_dec_counter.cmp_merge.kpt b/YL_dec_counter/db/YL_dec_counter.cmp_merge.kpt new file mode 100644 index 0000000000000000000000000000000000000000..c3f6705f04e412161dcc88983949928e10687aac GIT binary patch literal 230 zcmVuG0001ZoTZV$N&_(vhVT0nL+JSYXlQ%I9(4cpDe z$!wwE!8Cc zb_0*NgB$BOk)kgEmIIzun4IURA~Ntfq^g8_B=jbAdv-`^6FTvlf$A&qyM#&mn3Mi% g*-td0{iEiC(3kA&`VRhZ)fdV4{;|Gz1Jr_-Oc#4|IRF3v literal 0 HcmV?d00001 diff --git a/YL_dec_counter/db/YL_dec_counter.db_info b/YL_dec_counter/db/YL_dec_counter.db_info new file mode 100644 index 0000000..cc29380 --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Sun May 03 18:36:09 2020 diff --git a/YL_dec_counter/db/YL_dec_counter.eda.qmsg b/YL_dec_counter/db/YL_dec_counter.eda.qmsg new file mode 100644 index 0000000..307ca62 --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588508769279 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588508769281 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 20:26:08 2020 " "Processing started: Sun May 03 20:26:08 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588508769281 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588508769281 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog YL_dec_counter -c YL_dec_counter " "Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog YL_dec_counter -c YL_dec_counter" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588508769281 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "YL_dec_counter.vo C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/simulation/modelsim/ simulation " "Generated file YL_dec_counter.vo in folder \"C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1588508769823 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4525 " "Peak virtual memory: 4525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588508769900 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 20:26:09 2020 " "Processing ended: Sun May 03 20:26:09 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588508769900 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588508769900 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588508769900 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588508769900 ""} diff --git a/YL_dec_counter/db/YL_dec_counter.eds_overflow b/YL_dec_counter/db/YL_dec_counter.eds_overflow new file mode 100644 index 0000000..7d37386 --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.eds_overflow @@ -0,0 +1 @@ +45 \ No newline at end of file diff --git a/YL_dec_counter/db/YL_dec_counter.fit.qmsg b/YL_dec_counter/db/YL_dec_counter.fit.qmsg new file mode 100644 index 0000000..179d64c --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.fit.qmsg @@ -0,0 +1,45 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1588502936622 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "YL_dec_counter EP2C20F484C7 " "Selected device EP2C20F484C7 for design \"YL_dec_counter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1588502936637 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588502936686 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1588502936687 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1588502937767 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1588502937787 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Device EP2C15AF484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588502939171 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Device EP2C35F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588502939171 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Device EP2C50F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1588502939171 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1588502939171 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 37 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588502939173 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 38 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588502939173 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 39 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1588502939173 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1588502939173 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "9 9 " "No exact pin location assignment(s) for 9 pins of 9 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rco " "Pin rco not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { rco } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 216 576 752 232 "rco" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rco } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 9 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "value\[3\] " "Pin value\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { value[3] } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 40 584 760 56 "value" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { value[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 5 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "value\[2\] " "Pin value\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { value[2] } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 40 584 760 56 "value" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { value[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 6 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "value\[1\] " "Pin value\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { value[1] } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 40 584 760 56 "value" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { value[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 7 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "value\[0\] " "Pin value\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { value[0] } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 40 584 760 56 "value" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { value[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 8 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ent " "Pin ent not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ent } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 128 40 208 144 "ent" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ent } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 11 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "enc " "Pin enc not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { enc } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 112 40 208 128 "enc" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { enc } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 10 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clear " "Pin clear not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clear } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 160 40 208 176 "clear" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clear } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 13 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clock " "Pin clock not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clock } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 144 40 208 160 "clock" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 12 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1588502939261 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1588502939261 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_dec_counter.sdc " "Synopsys Design Constraints File file not found: 'YL_dec_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1588502939444 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1588502939445 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1588502939447 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Automatically promoted node clock (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1588502939461 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clock } } } { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 144 40 208 160 "clock" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 0 { 0 ""} 0 12 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1588502939461 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1588502939635 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588502939636 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1588502939637 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588502939638 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1588502939638 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1588502939639 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1588502939639 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1588502939639 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1588502939641 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1588502939641 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1588502939641 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 3.3V 3 5 0 " "Number of I/O pins in group: 8 (unused VREF, 3.3V VCCIO, 3 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1588502939643 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1588502939643 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1588502939643 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 40 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 31 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 39 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 35 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1588502939645 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1588502939645 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1588502939645 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588502939655 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1588502941633 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588502941701 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1588502941712 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1588502942041 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588502942041 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1588502942089 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X11_Y13 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13" { } { { "loc" "" { Generic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13"} 0 0 12 14 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1588502942951 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1588502942951 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588502943192 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1588502943196 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1588502943196 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1588502943204 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588502943208 ""} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "rco 0 " "Pin \"rco\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588502943211 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "value\[3\] 0 " "Pin \"value\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588502943211 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "value\[2\] 0 " "Pin \"value\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588502943211 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "value\[1\] 0 " "Pin \"value\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588502943211 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "value\[0\] 0 " "Pin \"value\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1588502943211 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1588502943211 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588502943309 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1588502943320 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1588502943427 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1588502943677 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1588502943795 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.fit.smsg " "Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1588502943933 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4848 " "Peak virtual memory: 4848 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588502944256 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 18:49:04 2020 " "Processing ended: Sun May 03 18:49:04 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588502944256 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588502944256 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 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"IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II 64-Bit " "Running Quartus II 64-Bit Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588508947564 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 20:29:07 2020 " "Processing started: Sun May 03 20:29:07 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588508947564 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588508947564 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map YL_dec_counter -c YL_dec_counter --generate_functional_sim_netlist " "Command: quartus_map YL_dec_counter -c YL_dec_counter --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588508947565 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588508948200 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec_counter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec_counter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_dec_counter " "Found entity 1: YL_dec_counter" { } { { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588508948269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588508948269 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec_counter.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dec_count " "Found entity 1: dec_count" { } { { "YL_dec_counter.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588508948283 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588508948283 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_dec_counter " "Elaborating entity \"YL_dec_counter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588508948393 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst\"" { } { { "YL_dec_counter.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 88 296 456 200 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588508948401 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4578 " "Peak virtual memory: 4578 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588508948562 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 20:29:08 2020 " "Processing ended: Sun May 03 20:29:08 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588508948562 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588508948562 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588508948562 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588508948562 ""} diff --git a/YL_dec_counter/db/YL_dec_counter.hier_info b/YL_dec_counter/db/YL_dec_counter.hier_info new file mode 100644 index 0000000..dd0fd51 --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.hier_info @@ -0,0 +1,30 @@ +|YL_dec_counter +rco <= dec_count:inst.rco +enc => dec_count:inst.enc +ent => dec_count:inst.ent +clock => dec_count:inst.clk +clear => dec_count:inst.clear +value[0] <= dec_count:inst.value[0] +value[1] <= dec_count:inst.value[1] +value[2] <= dec_count:inst.value[2] +value[3] <= dec_count:inst.value[3] + + +|YL_dec_counter|dec_count:inst +enc => _~2.IN0 +enc => _~14.IN0 +ent => _~2.IN1 +ent => _~14.IN1 +ent => rco~0.IN1 +clk => count[3].CLK +clk => count[2].CLK +clk => count[1].CLK +clk => count[0].CLK +clear => _~1.IN0 +value[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE +value[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE +value[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE +value[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE +rco <= rco~0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git 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"*******************************************************************" 0 0 "Quartus II" 0 -1 1588502930002 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588502930003 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 18:48:49 2020 " "Processing started: Sun May 03 18:48:49 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588502930003 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588502930003 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_dec_counter -c YL_dec_counter " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_dec_counter -c YL_dec_counter" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588502930003 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588502930767 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec_counter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec_counter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_dec_counter " "Found entity 1: YL_dec_counter" { } { { "YL_dec_counter.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588502930880 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588502930880 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec_counter.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dec_count " "Found entity 1: dec_count" { } { { "YL_dec_counter.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588502930887 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588502930887 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "YL_dec_counter " "Elaborating entity \"YL_dec_counter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588502930932 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst\"" { } { { "YL_dec_counter.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf" { { 88 296 456 200 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588502930953 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1588502932260 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588502932260 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1588502933220 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1588502933220 ""} { "Info" "ICUT_CUT_TM_LCELLS" "12 " "Implemented 12 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1588502933220 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1588502933220 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4603 " "Peak virtual memory: 4603 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588502933293 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 18:48:53 2020 " "Processing ended: Sun May 03 18:48:53 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588502933293 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588502933293 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588502933293 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588502933293 ""} diff --git a/YL_dec_counter/db/YL_dec_counter.map.rdb b/YL_dec_counter/db/YL_dec_counter.map.rdb new file mode 100644 index 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in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 1000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clock") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("enc") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("rco") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 860.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 100.0; + } +} + +TRANSITION_LIST("clock") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 20; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("enc") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 240.0; + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 460.0; + } +} + +TRANSITION_LIST("rco") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("value[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 825.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 125.0; + } +} + +TRANSITION_LIST("value[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 175.0; + LEVEL 1 FOR 650.0; + LEVEL 0 FOR 175.0; + } +} + +TRANSITION_LIST("value[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 75.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 550.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 25.0; + } +} + +TRANSITION_LIST("value[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + NODE + { + REPEAT = 2; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + } + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 500.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 25.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clock"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "enc"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rco"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "value"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; + CHILDREN = 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "value[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 5; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_dec_counter/db/YL_dec_counter.simfam b/YL_dec_counter/db/YL_dec_counter.simfam new file mode 100644 index 0000000..37dc84f --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.simfam @@ -0,0 +1,2 @@ +BOF +EOF diff --git a/YL_dec_counter/db/YL_dec_counter.sld_design_entry.sci b/YL_dec_counter/db/YL_dec_counter.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/YL_dec_counter/db/YL_dec_counter.sld_design_entry_dsc.sci b/YL_dec_counter/db/YL_dec_counter.sld_design_entry_dsc.sci new file mode 100644 index 0000000000000000000000000000000000000000..1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a GIT binary patch literal 216 zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX z1g932WhSR81SBSBD;O#SdntscCMme4WR?JR+5rs#fldg;5Cf%eK qN!xihAG0P~rUIMhC;o!3#ozdgdinVZO23tSE-B;r_{BW~VjKWu4?;r# literal 0 HcmV?d00001 diff --git a/YL_dec_counter/db/YL_dec_counter.smart_action.txt b/YL_dec_counter/db/YL_dec_counter.smart_action.txt new file mode 100644 index 0000000..11b531f --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/YL_dec_counter/db/YL_dec_counter.sta.qmsg b/YL_dec_counter/db/YL_dec_counter.sta.qmsg new file mode 100644 index 0000000..6ee9f92 --- /dev/null +++ b/YL_dec_counter/db/YL_dec_counter.sta.qmsg @@ -0,0 +1,30 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588502950991 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588502950992 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 18:49:10 2020 " "Processing started: Sun May 03 18:49:10 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588502950992 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588502950992 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_dec_counter -c YL_dec_counter " "Command: quartus_sta YL_dec_counter -c YL_dec_counter" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588502950993 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588502951253 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588502951630 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588502951692 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588502951693 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_dec_counter.sdc " "Synopsys Design Constraints File file not found: 'YL_dec_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588502951827 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588502951828 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clock clock " "create_clock -period 1.000 -name clock clock" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951829 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951829 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588502951832 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588502951850 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588502951860 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.250 " "Worst-case setup slack is -1.250" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951867 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951867 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.250 -4.462 clock " " -1.250 -4.462 clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951867 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588502951867 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.445 " "Worst-case hold slack is 0.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.445 0.000 clock " " 0.445 0.000 clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951872 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588502951872 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588502951885 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588502951890 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951902 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951902 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -6.519 clock " " -1.631 -6.519 clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951902 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588502951902 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588502951936 ""} +{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588502951938 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.125 " "Worst-case setup slack is 0.125" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.125 0.000 clock " " 0.125 0.000 clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951960 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588502951960 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clock " " 0.215 0.000 clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951965 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588502951965 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588502951970 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588502951983 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588502951983 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951997 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951997 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -5.380 clock " " -1.380 -5.380 clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588502951997 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588502951997 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588502952040 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588502952076 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588502952076 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4558 " "Peak virtual memory: 4558 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588502952172 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 18:49:12 2020 " "Processing ended: Sun May 03 18:49:12 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588502952172 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588502952172 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588502952172 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 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b/YL_dec_counter/output_files/YL_dec_counter.asm.rpt new file mode 100644 index 0000000..76a805f --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.asm.rpt @@ -0,0 +1,130 @@ +Assembler report for YL_dec_counter +Sun May 03 18:49:08 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.sof + 6. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sun May 03 18:49:08 2020 ; +; Revision Name ; YL_dec_counter ; +; Top-level Entity Name ; YL_dec_counter ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.sof ; +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.pof ; ++------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.sof ; ++----------------+---------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------------------------------------------+ +; Device ; EP2C20F484C7 ; +; JTAG usercode ; 0x001B2351 ; +; Checksum ; 0x001B2351 ; ++----------------+---------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.pof ; ++--------------------+-----------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+-----------------------------------------------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1DD9C022 ; +; Compression Ratio ; 3 ; ++--------------------+-----------------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 18:49:06 2020 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_dec_counter -c YL_dec_counter +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4558 megabytes + Info: Processing ended: Sun May 03 18:49:08 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_dec_counter/output_files/YL_dec_counter.done b/YL_dec_counter/output_files/YL_dec_counter.done new file mode 100644 index 0000000..21a1b30 --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.done @@ -0,0 +1 @@ +Sun May 03 18:49:13 2020 diff --git a/YL_dec_counter/output_files/YL_dec_counter.eda.rpt b/YL_dec_counter/output_files/YL_dec_counter.eda.rpt new file mode 100644 index 0000000..fc238ed --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.eda.rpt @@ -0,0 +1,92 @@ +EDA Netlist Writer report for YL_dec_counter +Sun May 03 20:26:09 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Sun May 03 20:26:09 2020 ; +; Revision Name ; YL_dec_counter ; +; Top-level Entity Name ; YL_dec_counter ; +; Family ; Cyclone II ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate netlist for functional simulation only ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++------------------------------------------------------------------------------------------------+ +; Generated Files ; ++------------------------------------------------------------------------------------------------+ +; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/simulation/modelsim/YL_dec_counter.vo ; ++------------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit EDA Netlist Writer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 20:26:08 2020 +Info: Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog YL_dec_counter -c YL_dec_counter +Info (204019): Generated file YL_dec_counter.vo in folder "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4525 megabytes + Info: Processing ended: Sun May 03 20:26:09 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/YL_dec_counter/output_files/YL_dec_counter.fit.rpt b/YL_dec_counter/output_files/YL_dec_counter.fit.rpt new file mode 100644 index 0000000..caaec17 --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.fit.rpt @@ -0,0 +1,1191 @@ +Fitter report for YL_dec_counter +Sun May 03 18:49:03 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. Output Pin Default Load For Reported TCO + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Control Signals + 20. Global & Other Fast Signals + 21. Non-Global High Fan-Out Signals + 22. Other Routing Usage Summary + 23. LAB Logic Elements + 24. LAB-wide Signals + 25. LAB Signals Sourced + 26. LAB Signals Sourced Out + 27. LAB Distinct Inputs + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Sun May 03 18:49:03 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_dec_counter ; +; Top-level Entity Name ; YL_dec_counter ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 12 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 12 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 4 / 18,752 ( < 1 % ) ; +; Total registers ; 4 ; +; Total pins ; 9 / 315 ( 3 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C20F484C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 30 ( 0.00 % ) ; +; -- Achieved ; 0 / 30 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 27 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 12 / 18,752 ( < 1 % ) ; +; -- Combinational with no register ; 8 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 4 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 4 ; +; -- <=2 input functions ; 1 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 12 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 4 / 19,649 ( < 1 % ) ; +; -- Dedicated logic registers ; 4 / 18,752 ( < 1 % ) ; +; -- I/O registers ; 0 / 897 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 1,172 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 9 / 315 ( 3 % ) ; +; -- Clock pins ; 1 / 8 ( 13 % ) ; +; ; ; +; Global signals ; 1 ; +; M4Ks ; 0 / 52 ( 0 % ) ; +; Total block memory bits ; 0 / 239,616 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 6 ; +; Highest non-global fan-out ; 6 ; +; Total fan-out ; 56 ; +; Average fan-out ; 1.93 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 12 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; -- Combinational with no register ; 8 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 4 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 7 ; 0 ; +; -- 3 input functions ; 4 ; 0 ; +; -- <=2 input functions ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 12 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 4 ; 0 ; +; -- Dedicated logic registers ; 4 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 1172 ( < 1 % ) ; 0 / 1172 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 9 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; 0 / 52 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 1 / 20 ( 5 % ) ; 0 / 20 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 56 ; 0 ; +; -- Registered Connections ; 20 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 4 ; 0 ; +; -- Output Ports ; 5 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; clear ; R2 ; 1 ; 0 ; 8 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; clock ; M1 ; 1 ; 0 ; 13 ; 2 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; enc ; R1 ; 1 ; 0 ; 8 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; ent ; T2 ; 1 ; 0 ; 8 ; 3 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; rco ; R8 ; 1 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[0] ; P6 ; 1 ; 0 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[1] ; T1 ; 1 ; 0 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[2] ; R6 ; 1 ; 0 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; value[3] ; R7 ; 1 ; 0 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 9 / 41 ( 22 % ) ; 3.3V ; -- ; +; 2 ; 2 / 33 ( 6 % ) ; 3.3V ; -- ; +; 3 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; +; 4 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 5 ; 0 / 39 ( 0 % ) ; 3.3V ; -- ; +; 6 ; 1 / 36 ( 3 % ) ; 3.3V ; -- ; +; 7 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; +; 8 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 306 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A8 ; 304 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A9 ; 298 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A10 ; 293 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A11 ; 287 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 265 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 251 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 249 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 82 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA4 ; 85 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA5 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA6 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA7 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA11 ; 122 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 130 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 144 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 83 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB4 ; 84 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB5 ; 88 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB6 ; 96 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB7 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB12 ; 127 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB13 ; 129 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 305 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B8 ; 303 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B9 ; 297 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B10 ; 292 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B11 ; 286 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B14 ; 278 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 264 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B18 ; 250 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C7 ; 315 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; 310 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C10 ; 296 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C14 ; 260 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D2 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D5 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D6 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 302 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 289 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 267 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 259 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; 255 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; 266 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E15 ; 256 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F4 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 276 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F13 ; 269 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 268 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 262 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 261 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 252 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H2 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; H4 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H6 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 274 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; 263 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H14 ; 257 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H15 ; 253 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J1 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J2 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; 258 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M1 ; 41 ; 1 ; clock ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M2 ; 42 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P6 ; 56 ; 1 ; value[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 187 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R1 ; 57 ; 1 ; enc ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R2 ; 58 ; 1 ; clear ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R5 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R6 ; 64 ; 1 ; value[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R7 ; 54 ; 1 ; value[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R8 ; 53 ; 1 ; rco ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R10 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R11 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; R21 ; 190 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R22 ; 191 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T1 ; 59 ; 1 ; value[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T2 ; 60 ; 1 ; ent ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T3 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T5 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T6 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T7 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T8 ; 90 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T12 ; 131 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T15 ; 147 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 188 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T22 ; 189 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U1 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U2 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U3 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U4 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U8 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U21 ; 182 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U22 ; 183 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V9 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 180 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 181 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W2 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W7 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W8 ; 100 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W9 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W21 ; 174 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; 175 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y3 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y4 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y5 ; 86 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y6 ; 87 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y7 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y13 ; 133 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y21 ; 178 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 179 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+ +; |YL_dec_counter ; 12 (0) ; 4 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; 8 (0) ; 0 (0) ; 4 (0) ; |YL_dec_counter ; work ; +; |dec_count:inst| ; 12 (12) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 4 (4) ; |YL_dec_counter|dec_count:inst ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++----------+----------+---------------+---------------+-----------------------+-----+ +; rco ; Output ; -- ; -- ; -- ; -- ; +; value[3] ; Output ; -- ; -- ; -- ; -- ; +; value[2] ; Output ; -- ; -- ; -- ; -- ; +; value[1] ; Output ; -- ; -- ; -- ; -- ; +; value[0] ; Output ; -- ; -- ; -- ; -- ; +; ent ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; enc ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; clear ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; clock ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; ++----------+----------+---------------+---------------+-----------------------+-----+ + + ++----------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++----------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++----------------------------------+-------------------+---------+ +; ent ; ; ; +; - dec_count:inst|_~1 ; 1 ; 6 ; +; - dec_count:inst|count[0]~0 ; 1 ; 6 ; +; - dec_count:inst|count[0]~1 ; 1 ; 6 ; +; - dec_count:inst|count[0]~3 ; 1 ; 6 ; +; - dec_count:inst|_~2 ; 1 ; 6 ; +; enc ; ; ; +; - dec_count:inst|count[0]~0 ; 1 ; 6 ; +; - dec_count:inst|count[0]~1 ; 1 ; 6 ; +; - dec_count:inst|count[0]~3 ; 1 ; 6 ; +; - dec_count:inst|_~2 ; 1 ; 6 ; +; clear ; ; ; +; - dec_count:inst|count[0]~0 ; 0 ; 6 ; +; - dec_count:inst|count[0]~1 ; 0 ; 6 ; +; - dec_count:inst|count[0]~3 ; 0 ; 6 ; +; - dec_count:inst|count[2]~5 ; 0 ; 6 ; +; - dec_count:inst|count[1]~6 ; 0 ; 6 ; +; clock ; ; ; ++----------------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+ +; clock ; PIN_M1 ; 4 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; ++-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; clock ; PIN_M1 ; 4 ; Global Clock ; GCLK3 ; -- ; ++-------+----------+---------+----------------------+------------------+---------------------------+ + + ++-------------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------------------------+---------+ +; Name ; Fan-Out ; ++---------------------------+---------+ +; dec_count:inst|count[0] ; 6 ; +; clear ; 5 ; +; ent ; 5 ; +; dec_count:inst|count[1] ; 5 ; +; dec_count:inst|count[2] ; 5 ; +; enc ; 4 ; +; dec_count:inst|_~0 ; 4 ; +; dec_count:inst|count[3] ; 4 ; +; dec_count:inst|_~2 ; 2 ; +; dec_count:inst|count[0]~1 ; 2 ; +; dec_count:inst|count[1]~6 ; 1 ; +; dec_count:inst|count[2]~5 ; 1 ; +; dec_count:inst|op_1~1 ; 1 ; +; dec_count:inst|count[0]~4 ; 1 ; +; dec_count:inst|count[0]~3 ; 1 ; +; dec_count:inst|count[3]~2 ; 1 ; +; dec_count:inst|count[0]~0 ; 1 ; +; dec_count:inst|op_1~0 ; 1 ; +; dec_count:inst|_~1 ; 1 ; ++---------------------------+---------+ + + ++-----------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-----------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-----------------------+ +; Block interconnects ; 10 / 54,004 ( < 1 % ) ; +; C16 interconnects ; 0 / 2,100 ( 0 % ) ; +; C4 interconnects ; 4 / 36,000 ( < 1 % ) ; +; Direct links ; 3 / 54,004 ( < 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; Local interconnects ; 11 / 18,752 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,900 ( 0 % ) ; +; R4 interconnects ; 0 / 46,920 ( 0 % ) ; ++-----------------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 12.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 1) ; ++------------------------------------+-----------------------------+ +; 1 Clock ; 1 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 1) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 4.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP2C20F484C7 for design "YL_dec_counter" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP2C15AF484C7 is compatible + Info (176445): Device EP2C35F484C7 is compatible + Info (176445): Device EP2C50F484C7 is compatible +Info (169124): Fitter converted 3 user pins into dedicated programming pins + Info (169125): Pin ~ASDO~ is reserved at location C4 + Info (169125): Pin ~nCSO~ is reserved at location C3 + Info (169125): Pin ~LVDS91p/nCEO~ is reserved at location W20 +Critical Warning (169085): No exact pin location assignment(s) for 9 pins of 9 total pins + Info (169086): Pin rco not assigned to an exact location on the device + Info (169086): Pin value[3] not assigned to an exact location on the device + Info (169086): Pin value[2] not assigned to an exact location on the device + Info (169086): Pin value[1] not assigned to an exact location on the device + Info (169086): Pin value[0] not assigned to an exact location on the device + Info (169086): Pin ent not assigned to an exact location on the device + Info (169086): Pin enc not assigned to an exact location on the device + Info (169086): Pin clear not assigned to an exact location on the device + Info (169086): Pin clock not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_dec_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clock (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 8 (unused VREF, 3.3V VCCIO, 3 input, 5 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.25 seconds. +Info (306004): Started post-fitting delay annotation +Warning (306006): Found 5 output pins without output pin load capacitance assignment + Info (306007): Pin "rco" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "value[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info (306005): Delay annotation completed successfully +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 4848 megabytes + Info: Processing ended: Sun May 03 18:49:04 2020 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:06 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/output_files/YL_dec_counter.fit.smsg. + + diff --git a/YL_dec_counter/output_files/YL_dec_counter.fit.smsg b/YL_dec_counter/output_files/YL_dec_counter.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/YL_dec_counter/output_files/YL_dec_counter.fit.summary b/YL_dec_counter/output_files/YL_dec_counter.fit.summary new file mode 100644 index 0000000..10fa997 --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Sun May 03 18:49:03 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_dec_counter +Top-level Entity Name : YL_dec_counter +Family : Cyclone II +Device : EP2C20F484C7 +Timing Models : Final +Total logic elements : 12 / 18,752 ( < 1 % ) + Total combinational functions : 12 / 18,752 ( < 1 % ) + Dedicated logic registers : 4 / 18,752 ( < 1 % ) +Total registers : 4 +Total pins : 9 / 315 ( 3 % ) +Total virtual pins : 0 +Total memory bits : 0 / 239,616 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/YL_dec_counter/output_files/YL_dec_counter.flow.rpt b/YL_dec_counter/output_files/YL_dec_counter.flow.rpt new file mode 100644 index 0000000..e40e323 --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.flow.rpt @@ -0,0 +1,128 @@ +Flow report for YL_dec_counter +Sun May 03 20:26:09 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Sun May 03 20:26:09 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_dec_counter ; +; Top-level Entity Name ; YL_dec_counter ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 12 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 12 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 4 / 18,752 ( < 1 % ) ; +; Total registers ; 4 ; +; Total pins ; 9 / 315 ( 3 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 05/03/2020 18:48:50 ; +; Main task ; Compilation ; +; Revision Name ; YL_dec_counter ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 345052807169.158850293011320 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4592 MB ; 00:00:02 ; +; Fitter ; 00:00:09 ; 1.0 ; 4848 MB ; 00:00:06 ; +; Assembler ; 00:00:02 ; 1.0 ; 4558 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4558 MB ; 00:00:02 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4525 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4525 MB ; 00:00:01 ; +; Total ; 00:00:17 ; -- ; -- ; 00:00:14 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off YL_dec_counter -c YL_dec_counter +quartus_fit --read_settings_files=off --write_settings_files=off YL_dec_counter -c YL_dec_counter +quartus_asm --read_settings_files=off --write_settings_files=off YL_dec_counter -c YL_dec_counter +quartus_sta YL_dec_counter -c YL_dec_counter +quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog YL_dec_counter -c YL_dec_counter --vector_source=C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_DecCounter.vwf --testbench_file=./simulation/qsim/YL_dec_counter.vt +quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog YL_dec_counter -c YL_dec_counter + + + diff --git a/YL_dec_counter/output_files/YL_dec_counter.jdi b/YL_dec_counter/output_files/YL_dec_counter.jdi new file mode 100644 index 0000000..f2051fc --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/YL_dec_counter/output_files/YL_dec_counter.map.rpt b/YL_dec_counter/output_files/YL_dec_counter.map.rpt new file mode 100644 index 0000000..92c2b3b --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.map.rpt @@ -0,0 +1,259 @@ +Analysis & Synthesis report for YL_dec_counter +Sun May 03 18:48:53 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sun May 03 18:48:53 2020 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; YL_dec_counter ; +; Top-level Entity Name ; YL_dec_counter ; +; Family ; Cyclone II ; +; Total logic elements ; 12 ; +; Total combinational functions ; 12 ; +; Dedicated logic registers ; 4 ; +; Total registers ; 4 ; +; Total pins ; 9 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; YL_dec_counter ; YL_dec_counter ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+ +; YL_dec_counter.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf ; ; +; YL_dec_counter.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.tdf ; ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------------------+ +; Estimated Total logic elements ; 12 ; +; ; ; +; Total combinational functions ; 12 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 4 ; +; -- <=2 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 12 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 4 ; +; -- Dedicated logic registers ; 4 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 9 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; dec_count:inst|count[0] ; +; Maximum fan-out ; 6 ; +; Total fan-out ; 55 ; +; Average fan-out ; 2.20 ; ++---------------------------------------------+-------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+ +; |YL_dec_counter ; 12 (0) ; 4 (0) ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; |YL_dec_counter ; work ; +; |dec_count:inst| ; 12 (12) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |YL_dec_counter|dec_count:inst ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 4 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 18:48:49 2020 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_dec_counter -c YL_dec_counter +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file yl_dec_counter.bdf + Info (12023): Found entity 1: YL_dec_counter +Info (12021): Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf + Info (12023): Found entity 1: dec_count +Info (12127): Elaborating entity "YL_dec_counter" for the top level hierarchy +Info (12128): Elaborating entity "dec_count" for hierarchy "dec_count:inst" +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 4 input pins + Info (21059): Implemented 5 output pins + Info (21061): Implemented 12 logic cells +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4603 megabytes + Info: Processing ended: Sun May 03 18:48:53 2020 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_dec_counter/output_files/YL_dec_counter.map.summary b/YL_dec_counter/output_files/YL_dec_counter.map.summary new file mode 100644 index 0000000..42fc092 --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Sun May 03 18:48:53 2020 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : YL_dec_counter +Top-level Entity Name : YL_dec_counter +Family : Cyclone II +Total logic elements : 12 + Total combinational functions : 12 + Dedicated logic registers : 4 +Total registers : 4 +Total pins : 9 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/YL_dec_counter/output_files/YL_dec_counter.pin b/YL_dec_counter/output_files/YL_dec_counter.pin new file mode 100644 index 0000000..62d8975 --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "YL_dec_counter" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +GND* : A11 : : : : 3 : +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +GND* : AA3 : : : : 8 : +GND* : AA4 : : : : 8 : +GND* : AA5 : : : : 8 : +GND* : AA6 : : : : 8 : +GND* : AA7 : : : : 8 : +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +GND* : AA11 : : : : 8 : +GND* : AA12 : : : : 7 : +GND* : AA13 : : : : 7 : +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +GND* : AA16 : : : : 7 : +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +GND* : AB3 : : : : 8 : +GND* : AB4 : : : : 8 : +GND* : AB5 : : : : 8 : +GND* : AB6 : : : : 8 : +GND* : AB7 : : : : 8 : +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +GND* : AB12 : : : : 7 : +GND* : AB13 : : : : 7 : +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +GND* : B11 : : : : 3 : +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +GND* : B14 : : : : 4 : +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +GND* : B17 : : : : 4 : +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 2 : +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +GND* : C7 : : : : 3 : +GND : C8 : gnd : : : : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +GND* : C14 : : : : 4 : +GND : C15 : gnd : : : : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +GND* : C21 : : : : 5 : +GND* : C22 : : : : 5 : +GND* : D1 : : : : 2 : +GND* : D2 : : : : 2 : +GND* : D3 : : : : 2 : +GND* : D4 : : : : 2 : +GND* : D5 : : : : 2 : +GND* : D6 : : : : 2 : +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +GND* : D9 : : : : 3 : +GND : D10 : gnd : : : : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +GND* : D14 : : : : 4 : +GND* : D15 : : : : 4 : +GND* : D16 : : : : 4 : +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +GND* : D20 : : : : 5 : +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +GND* : E14 : : : : 4 : +GND* : E15 : : : : 4 : +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +GND* : F1 : : : : 2 : +GND* : F2 : : : : 2 : +GND* : F3 : : : : 2 : +GND* : F4 : : : : 2 : +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +GND* : F12 : : : : 4 : +GND* : F13 : : : : 4 : +GND* : F14 : : : : 4 : +GND* : F15 : : : : 4 : +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +GND* : G3 : : : : 2 : +GND : G4 : gnd : : : : +GND* : G5 : : : : 2 : +GND* : G6 : : : : 2 : +GND* : G7 : : : : 3 : +GND* : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +GND* : G15 : : : : 4 : +GND* : G16 : : : : 4 : +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +GND* : H4 : : : : 2 : +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +GND* : H12 : : : : 4 : +GND* : H13 : : : : 4 : +GND* : H14 : : : : 4 : +GND* : H15 : : : : 4 : +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +GND* : J1 : : : : 2 : +GND* : J2 : : : : 2 : +NC : J3 : : : : : +GND* : J4 : : : : 2 : +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +GND* : J14 : : : : 4 : +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +GND+ : L1 : : : : 2 : +GND+ : L2 : : : : 2 : +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +GND* : L8 : : : : 2 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +GND+ : L21 : : : : 5 : +GND+ : L22 : : : : 5 : +clock : M1 : input : 3.3-V LVTTL : : 1 : N +GND+ : M2 : : : : 1 : +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +GND+ : M22 : : : : 6 : +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +GND* : P5 : : : : 1 : +value[0] : P6 : output : 3.3-V LVTTL : : 1 : N +VCCIO1 : P7 : power : : 3.3V : 1 : +GND* : P8 : : : : 8 : +GND* : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +GND* : P18 : : : : 6 : +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +enc : R1 : input : 3.3-V LVTTL : : 1 : N +clear : R2 : input : 3.3-V LVTTL : : 1 : N +GND : R3 : gnd : : : : +NC : R4 : : : : : +GND* : R5 : : : : 1 : +value[2] : R6 : output : 3.3-V LVTTL : : 1 : N +value[3] : R7 : output : 3.3-V LVTTL : : 1 : N +rco : R8 : output : 3.3-V LVTTL : : 1 : N +GND* : R9 : : : : 8 : +GND* : R10 : : : : 8 : +GND* : R11 : : : : 8 : +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +value[1] : T1 : output : 3.3-V LVTTL : : 1 : N +ent : T2 : input : 3.3-V LVTTL : : 1 : N +GND* : T3 : : : : 1 : +VCCIO1 : T4 : power : : 3.3V : 1 : +GND* : T5 : : : : 1 : +GND* : T6 : : : : 1 : +GND* : T7 : : : : 8 : +GND* : T8 : : : : 8 : +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +GND* : T12 : : : : 7 : +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +GND* : T15 : : : : 7 : +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +GND* : U1 : : : : 1 : +GND* : U2 : : : : 1 : +GND* : U3 : : : : 1 : +GND* : U4 : : : : 1 : +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +GND* : U8 : : : : 8 : +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : V1 : : : : 1 : +GND* : V2 : : : : 1 : +GND : V3 : gnd : : : : +GND* : V4 : : : : 1 : +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +GND* : V8 : : : : 8 : +GND* : V9 : : : : 8 : +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +GND* : W1 : : : : 1 : +GND* : W2 : : : : 1 : +GND* : W3 : : : : 1 : +GND* : W4 : : : : 1 : +GND* : W5 : : : : 1 : +VCCIO8 : W6 : power : : 3.3V : 8 : +GND* : W7 : : : : 8 : +GND* : W8 : : : : 8 : +GND* : W9 : : : : 8 : +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +GND* : Y1 : : : : 1 : +GND* : Y2 : : : : 1 : +GND* : Y3 : : : : 1 : +GND* : Y4 : : : : 1 : +GND* : Y5 : : : : 8 : +GND* : Y6 : : : : 8 : +GND* : Y7 : : : : 8 : +GND : Y8 : gnd : : : : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power : : 3.3V : 7 : +GND* : Y13 : : : : 7 : +GND* : Y14 : : : : 7 : +GND : Y15 : gnd : : : : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 6 : +GND* : Y19 : : : : 6 : +GND* : Y20 : : : : 6 : +GND* : Y21 : : : : 6 : +GND* : Y22 : : : : 6 : diff --git a/YL_dec_counter/output_files/YL_dec_counter.pof b/YL_dec_counter/output_files/YL_dec_counter.pof new file mode 100644 index 0000000000000000000000000000000000000000..16b9fd81b561c94b4564ff189b37cd857cc77a4c GIT binary patch literal 2097373 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z$NC!EK}e3h9B*I#>$pD+RyrAEyvIp6-j<9NZyb{R_P-AFW9t6B-=HrVyXUDmg8k{i Xd)eoClB1KV9Nb}U+s|MB$?g9S4STU- literal 0 HcmV?d00001 diff --git a/YL_dec_counter/output_files/YL_dec_counter.sta.rpt b/YL_dec_counter/output_files/YL_dec_counter.sta.rpt new file mode 100644 index 0000000..83478cb --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.sta.rpt @@ -0,0 +1,677 @@ +TimeQuest Timing Analyzer report for YL_dec_counter +Sun May 03 18:49:12 2020 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow Model Fmax Summary + 6. Slow Model Setup Summary + 7. Slow Model Hold Summary + 8. Slow Model Recovery Summary + 9. Slow Model Removal Summary + 10. Slow Model Minimum Pulse Width Summary + 11. Slow Model Setup: 'clock' + 12. Slow Model Hold: 'clock' + 13. Slow Model Minimum Pulse Width: 'clock' + 14. Setup Times + 15. Hold Times + 16. Clock to Output Times + 17. Minimum Clock to Output Times + 18. Propagation Delay + 19. Minimum Propagation Delay + 20. Fast Model Setup Summary + 21. Fast Model Hold Summary + 22. Fast Model Recovery Summary + 23. Fast Model Removal Summary + 24. Fast Model Minimum Pulse Width Summary + 25. Fast Model Setup: 'clock' + 26. Fast Model Hold: 'clock' + 27. Fast Model Minimum Pulse Width: 'clock' + 28. Setup Times + 29. Hold Times + 30. Clock to Output Times + 31. Minimum Clock to Output Times + 32. Propagation Delay + 33. Minimum Propagation Delay + 34. Multicorner Timing Analysis Summary + 35. Setup Times + 36. Hold Times + 37. Clock to Output Times + 38. Minimum Clock to Output Times + 39. Progagation Delay + 40. Minimum Progagation Delay + 41. Setup Transfers + 42. Hold Transfers + 43. Report TCCS + 44. Report RSKM + 45. Unconstrained Paths + 46. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; YL_dec_counter ; +; Device Family ; Cyclone II ; +; Device Name ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; clock ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clock } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Slow Model Fmax Summary ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; 444.44 MHz ; 380.08 MHz ; clock ; limit due to minimum period restriction (max I/O toggle rate) ; ++------------+-----------------+------------+---------------------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++--------------------------------+ +; Slow Model Setup Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; clock ; -1.250 ; -4.462 ; ++-------+--------+---------------+ + + ++-------------------------------+ +; Slow Model Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; clock ; 0.445 ; 0.000 ; ++-------+-------+---------------+ + + +------------------------------- +; Slow Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Slow Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Slow Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clock ; -1.631 ; -6.519 ; ++-------+--------+-----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Slow Model Setup: 'clock' ; ++--------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; -1.250 ; dec_count:inst|count[3] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 2.288 ; +; -1.228 ; dec_count:inst|count[3] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 2.266 ; +; -1.227 ; dec_count:inst|count[3] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 2.265 ; +; -1.132 ; dec_count:inst|count[1] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 2.170 ; +; -1.110 ; dec_count:inst|count[1] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 2.148 ; +; -1.109 ; dec_count:inst|count[1] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 2.147 ; +; -1.053 ; dec_count:inst|count[2] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 2.091 ; +; -1.031 ; dec_count:inst|count[2] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 2.069 ; +; -1.030 ; dec_count:inst|count[2] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 2.068 ; +; -0.899 ; dec_count:inst|count[0] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 1.937 ; +; -0.877 ; dec_count:inst|count[0] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 1.915 ; +; -0.876 ; dec_count:inst|count[0] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 1.914 ; +; -0.757 ; dec_count:inst|count[3] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 1.795 ; +; -0.639 ; dec_count:inst|count[1] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 1.677 ; +; -0.560 ; dec_count:inst|count[2] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 1.598 ; +; -0.406 ; dec_count:inst|count[0] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 1.444 ; ++--------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Slow Model Hold: 'clock' ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; 0.445 ; dec_count:inst|count[0] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 0.731 ; +; 0.445 ; dec_count:inst|count[1] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 0.731 ; +; 0.445 ; dec_count:inst|count[2] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 0.731 ; +; 0.445 ; dec_count:inst|count[3] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 0.731 ; +; 1.195 ; dec_count:inst|count[0] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 1.481 ; +; 1.312 ; dec_count:inst|count[2] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 1.598 ; +; 1.391 ; dec_count:inst|count[1] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 1.677 ; +; 1.470 ; dec_count:inst|count[0] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 1.756 ; +; 1.477 ; dec_count:inst|count[0] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 1.763 ; +; 1.509 ; dec_count:inst|count[3] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 1.795 ; +; 1.633 ; dec_count:inst|count[2] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 1.919 ; +; 1.783 ; dec_count:inst|count[2] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 2.069 ; +; 1.802 ; dec_count:inst|count[1] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 2.088 ; +; 1.807 ; dec_count:inst|count[1] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 2.093 ; +; 1.979 ; dec_count:inst|count[3] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 2.265 ; +; 1.980 ; dec_count:inst|count[3] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 2.266 ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Slow Model Minimum Pulse Width: 'clock' ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------+ +; -1.631 ; 1.000 ; 2.631 ; Port Rate ; clock ; Rise ; clock ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[0] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[0] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[1] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[1] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[2] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[2] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[3] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[3] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; clock|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; clock|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; clock~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; clock~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; clock~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; clock~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[3]|clk ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; clear ; clock ; 4.263 ; 4.263 ; Rise ; clock ; +; enc ; clock ; 4.158 ; 4.158 ; Rise ; clock ; +; ent ; clock ; 4.017 ; 4.017 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; clear ; clock ; -3.130 ; -3.130 ; Rise ; clock ; +; enc ; clock ; -3.496 ; -3.496 ; Rise ; clock ; +; ent ; clock ; -3.702 ; -3.702 ; Rise ; clock ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; rco ; clock ; 8.596 ; 8.596 ; Rise ; clock ; +; value[*] ; clock ; 6.897 ; 6.897 ; Rise ; clock ; +; value[0] ; clock ; 6.879 ; 6.879 ; Rise ; clock ; +; value[1] ; clock ; 6.553 ; 6.553 ; Rise ; clock ; +; value[2] ; clock ; 6.871 ; 6.871 ; Rise ; clock ; +; value[3] ; clock ; 6.897 ; 6.897 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; rco ; clock ; 8.245 ; 8.245 ; Rise ; clock ; +; value[*] ; clock ; 6.553 ; 6.553 ; Rise ; clock ; +; value[0] ; clock ; 6.879 ; 6.879 ; Rise ; clock ; +; value[1] ; clock ; 6.553 ; 6.553 ; Rise ; clock ; +; value[2] ; clock ; 6.871 ; 6.871 ; Rise ; clock ; +; value[3] ; clock ; 6.897 ; 6.897 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++----------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; ent ; rco ; 9.626 ; ; ; 9.626 ; ++------------+-------------+-------+----+----+-------+ + + ++----------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; ent ; rco ; 9.626 ; ; ; 9.626 ; ++------------+-------------+-------+----+----+-------+ + + ++-------------------------------+ +; Fast Model Setup Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; clock ; 0.125 ; 0.000 ; ++-------+-------+---------------+ + + ++-------------------------------+ +; Fast Model Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; clock ; 0.215 ; 0.000 ; ++-------+-------+---------------+ + + +------------------------------- +; Fast Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Fast Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Fast Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clock ; -1.380 ; -5.380 ; ++-------+--------+-----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Fast Model Setup: 'clock' ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; 0.125 ; dec_count:inst|count[3] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 0.907 ; +; 0.138 ; dec_count:inst|count[3] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 0.894 ; +; 0.139 ; dec_count:inst|count[3] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 0.893 ; +; 0.151 ; dec_count:inst|count[1] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 0.881 ; +; 0.164 ; dec_count:inst|count[1] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 0.868 ; +; 0.165 ; dec_count:inst|count[1] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 0.867 ; +; 0.209 ; dec_count:inst|count[2] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 0.823 ; +; 0.222 ; dec_count:inst|count[2] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 0.810 ; +; 0.223 ; dec_count:inst|count[2] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 0.809 ; +; 0.263 ; dec_count:inst|count[0] ; dec_count:inst|count[3] ; clock ; clock ; 1.000 ; 0.000 ; 0.769 ; +; 0.276 ; dec_count:inst|count[0] ; dec_count:inst|count[1] ; clock ; clock ; 1.000 ; 0.000 ; 0.756 ; +; 0.277 ; dec_count:inst|count[0] ; dec_count:inst|count[2] ; clock ; clock ; 1.000 ; 0.000 ; 0.755 ; +; 0.304 ; dec_count:inst|count[3] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 0.728 ; +; 0.330 ; dec_count:inst|count[1] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 0.702 ; +; 0.388 ; dec_count:inst|count[2] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 0.644 ; +; 0.442 ; dec_count:inst|count[0] ; dec_count:inst|count[0] ; clock ; clock ; 1.000 ; 0.000 ; 0.590 ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Fast Model Hold: 'clock' ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ +; 0.215 ; dec_count:inst|count[0] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 0.367 ; +; 0.215 ; dec_count:inst|count[1] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 0.367 ; +; 0.215 ; dec_count:inst|count[2] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 0.367 ; +; 0.215 ; dec_count:inst|count[3] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 0.367 ; +; 0.441 ; dec_count:inst|count[0] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 0.593 ; +; 0.492 ; dec_count:inst|count[2] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 0.644 ; +; 0.547 ; dec_count:inst|count[0] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 0.699 ; +; 0.547 ; dec_count:inst|count[0] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 0.699 ; +; 0.550 ; dec_count:inst|count[1] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 0.702 ; +; 0.576 ; dec_count:inst|count[3] ; dec_count:inst|count[0] ; clock ; clock ; 0.000 ; 0.000 ; 0.728 ; +; 0.603 ; dec_count:inst|count[2] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 0.755 ; +; 0.657 ; dec_count:inst|count[1] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 0.809 ; +; 0.658 ; dec_count:inst|count[1] ; dec_count:inst|count[3] ; clock ; clock ; 0.000 ; 0.000 ; 0.810 ; +; 0.658 ; dec_count:inst|count[2] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 0.810 ; +; 0.741 ; dec_count:inst|count[3] ; dec_count:inst|count[2] ; clock ; clock ; 0.000 ; 0.000 ; 0.893 ; +; 0.742 ; dec_count:inst|count[3] ; dec_count:inst|count[1] ; clock ; clock ; 0.000 ; 0.000 ; 0.894 ; ++-------+-------------------------+-------------------------+--------------+-------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Fast Model Minimum Pulse Width: 'clock' ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------+ +; -1.380 ; 1.000 ; 2.380 ; Port Rate ; clock ; Rise ; clock ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[0] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[0] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[1] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[1] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[2] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[2] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clock ; Rise ; dec_count:inst|count[3] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clock ; Rise ; dec_count:inst|count[3] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; clock|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; clock|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; clock~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; clock~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; clock~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; clock~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clock ; Rise ; inst|count[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clock ; Rise ; inst|count[3]|clk ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; clear ; clock ; 1.919 ; 1.919 ; Rise ; clock ; +; enc ; clock ; 1.846 ; 1.846 ; Rise ; clock ; +; ent ; clock ; 1.794 ; 1.794 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; clear ; clock ; -1.482 ; -1.482 ; Rise ; clock ; +; enc ; clock ; -1.601 ; -1.601 ; Rise ; clock ; +; ent ; clock ; -1.646 ; -1.646 ; Rise ; clock ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; rco ; clock ; 4.360 ; 4.360 ; Rise ; clock ; +; value[*] ; clock ; 3.721 ; 3.721 ; Rise ; clock ; +; value[0] ; clock ; 3.700 ; 3.700 ; Rise ; clock ; +; value[1] ; clock ; 3.592 ; 3.592 ; Rise ; clock ; +; value[2] ; clock ; 3.697 ; 3.697 ; Rise ; clock ; +; value[3] ; clock ; 3.721 ; 3.721 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; rco ; clock ; 4.222 ; 4.222 ; Rise ; clock ; +; value[*] ; clock ; 3.592 ; 3.592 ; Rise ; clock ; +; value[0] ; clock ; 3.700 ; 3.700 ; Rise ; clock ; +; value[1] ; clock ; 3.592 ; 3.592 ; Rise ; clock ; +; value[2] ; clock ; 3.697 ; 3.697 ; Rise ; clock ; +; value[3] ; clock ; 3.721 ; 3.721 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++----------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; ent ; rco ; 5.003 ; ; ; 5.003 ; ++------------+-------------+-------+----+----+-------+ + + ++----------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; ent ; rco ; 5.003 ; ; ; 5.003 ; ++------------+-------------+-------+----+----+-------+ + + ++------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+--------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+--------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -1.250 ; 0.215 ; N/A ; N/A ; -1.631 ; +; clock ; -1.250 ; 0.215 ; N/A ; N/A ; -1.631 ; +; Design-wide TNS ; -4.462 ; 0.0 ; 0.0 ; 0.0 ; -6.519 ; +; clock ; -4.462 ; 0.000 ; N/A ; N/A ; -6.519 ; ++------------------+--------+-------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; clear ; clock ; 4.263 ; 4.263 ; Rise ; clock ; +; enc ; clock ; 4.158 ; 4.158 ; Rise ; clock ; +; ent ; clock ; 4.017 ; 4.017 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; clear ; clock ; -1.482 ; -1.482 ; Rise ; clock ; +; enc ; clock ; -1.601 ; -1.601 ; Rise ; clock ; +; ent ; clock ; -1.646 ; -1.646 ; Rise ; clock ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; rco ; clock ; 8.596 ; 8.596 ; Rise ; clock ; +; value[*] ; clock ; 6.897 ; 6.897 ; Rise ; clock ; +; value[0] ; clock ; 6.879 ; 6.879 ; Rise ; clock ; +; value[1] ; clock ; 6.553 ; 6.553 ; Rise ; clock ; +; value[2] ; clock ; 6.871 ; 6.871 ; Rise ; clock ; +; value[3] ; clock ; 6.897 ; 6.897 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; rco ; clock ; 4.222 ; 4.222 ; Rise ; clock ; +; value[*] ; clock ; 3.592 ; 3.592 ; Rise ; clock ; +; value[0] ; clock ; 3.700 ; 3.700 ; Rise ; clock ; +; value[1] ; clock ; 3.592 ; 3.592 ; Rise ; clock ; +; value[2] ; clock ; 3.697 ; 3.697 ; Rise ; clock ; +; value[3] ; clock ; 3.721 ; 3.721 ; Rise ; clock ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++----------------------------------------------------+ +; Progagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; ent ; rco ; 9.626 ; ; ; 9.626 ; ++------------+-------------+-------+----+----+-------+ + + ++----------------------------------------------------+ +; Minimum Progagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; ent ; rco ; 5.003 ; ; ; 5.003 ; ++------------+-------------+-------+----+----+-------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clock ; clock ; 28 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clock ; clock ; 28 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 3 ; 3 ; +; Unconstrained Input Port Paths ; 13 ; 13 ; +; Unconstrained Output Ports ; 5 ; 5 ; +; Unconstrained Output Port Paths ; 9 ; 9 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Sun May 03 18:49:10 2020 +Info: Command: quartus_sta YL_dec_counter -c YL_dec_counter +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_dec_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name clock clock +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow Model +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -1.250 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.250 -4.462 clock +Info (332146): Worst-case hold slack is 0.445 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.445 0.000 clock +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.631 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.631 -6.519 clock +Info (332001): The selected device family is not supported by the report_metastability command. +Info: Analyzing Fast Model +Info (332146): Worst-case setup slack is 0.125 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.125 0.000 clock +Info (332146): Worst-case hold slack is 0.215 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.215 0.000 clock +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case minimum pulse width slack is -1.380 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.380 -5.380 clock +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 4558 megabytes + Info: Processing ended: Sun May 03 18:49:12 2020 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/YL_dec_counter/output_files/YL_dec_counter.sta.summary b/YL_dec_counter/output_files/YL_dec_counter.sta.summary new file mode 100644 index 0000000..ff00f2a --- /dev/null +++ b/YL_dec_counter/output_files/YL_dec_counter.sta.summary @@ -0,0 +1,29 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow Model Setup 'clock' +Slack : -1.250 +TNS : -4.462 + +Type : Slow Model Hold 'clock' +Slack : 0.445 +TNS : 0.000 + +Type : Slow Model Minimum Pulse Width 'clock' +Slack : -1.631 +TNS : -6.519 + +Type : Fast Model Setup 'clock' +Slack : 0.125 +TNS : 0.000 + +Type : Fast Model Hold 'clock' +Slack : 0.215 +TNS : 0.000 + +Type : Fast Model Minimum Pulse Width 'clock' +Slack : -1.380 +TNS : -5.380 + +------------------------------------------------------------ diff --git a/YL_dec_counter/simulation/modelsim/YL_dec_counter.sft b/YL_dec_counter/simulation/modelsim/YL_dec_counter.sft new file mode 100644 index 0000000..06a2ca4 --- /dev/null +++ b/YL_dec_counter/simulation/modelsim/YL_dec_counter.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/YL_dec_counter/simulation/modelsim/YL_dec_counter.vo b/YL_dec_counter/simulation/modelsim/YL_dec_counter.vo new file mode 100644 index 0000000..81dab14 --- /dev/null +++ b/YL_dec_counter/simulation/modelsim/YL_dec_counter.vo @@ -0,0 +1,681 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/03/2020 20:26:09" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_dec_counter ( + rco, + enc, + ent, + clock, + clear, + value); +output rco; +input enc; +input ent; +input clock; +input clear; +output [3:0] value; + +// Design Ports Information +// rco => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[3] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[2] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[1] => Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[0] => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// ent => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// enc => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clear => Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clock => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \inst|count[0]~1_combout ; +wire \clear~combout ; +wire \enc~combout ; +wire \ent~combout ; +wire \inst|count[0]~3_combout ; +wire \inst|count[0]~4_combout ; +wire \inst|_~2_combout ; +wire \inst|count[1]~6_combout ; +wire \inst|op_1~1_combout ; +wire \inst|count[2]~5_combout ; +wire \inst|_~0_combout ; +wire \inst|_~1_combout ; +wire \clock~combout ; +wire \clock~clkctrl_outclk ; +wire \inst|op_1~0_combout ; +wire \inst|count[0]~0_combout ; +wire \inst|count[3]~2_combout ; +wire [3:0] \inst|count ; + + +// Location: LCCOMB_X1_Y8_N24 +cycloneii_lcell_comb \inst|count[0]~1 ( +// Equation(s): +// \inst|count[0]~1_combout = (!\clear~combout & ((!\ent~combout ) # (!\enc~combout ))) + + .dataa(\clear~combout ), + .datab(vcc), + .datac(\enc~combout ), + .datad(\ent~combout ), + .cin(gnd), + .combout(\inst|count[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~1 .lut_mask = 16'h0555; +defparam \inst|count[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clear~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clear~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clear)); +// synopsys translate_off +defparam \clear~I .input_async_reset = "none"; +defparam \clear~I .input_power_up = "low"; +defparam \clear~I .input_register_mode = "none"; +defparam \clear~I .input_sync_reset = "none"; +defparam \clear~I .oe_async_reset = "none"; +defparam \clear~I .oe_power_up = "low"; +defparam \clear~I .oe_register_mode = "none"; +defparam \clear~I .oe_sync_reset = "none"; +defparam \clear~I .operation_mode = "input"; +defparam \clear~I .output_async_reset = "none"; +defparam \clear~I .output_power_up = "low"; +defparam \clear~I .output_register_mode = "none"; +defparam \clear~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \enc~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\enc~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(enc)); +// synopsys translate_off +defparam \enc~I .input_async_reset = "none"; +defparam \enc~I .input_power_up = "low"; +defparam \enc~I .input_register_mode = "none"; +defparam \enc~I .input_sync_reset = "none"; +defparam \enc~I .oe_async_reset = "none"; +defparam \enc~I .oe_power_up = "low"; +defparam \enc~I .oe_register_mode = "none"; +defparam \enc~I .oe_sync_reset = "none"; +defparam \enc~I .operation_mode = "input"; +defparam \enc~I .output_async_reset = "none"; +defparam \enc~I .output_power_up = "low"; +defparam \enc~I .output_register_mode = "none"; +defparam \enc~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \ent~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\ent~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(ent)); +// synopsys translate_off +defparam \ent~I .input_async_reset = "none"; +defparam \ent~I .input_power_up = "low"; +defparam \ent~I .input_register_mode = "none"; +defparam \ent~I .input_sync_reset = "none"; +defparam \ent~I .oe_async_reset = "none"; +defparam \ent~I .oe_power_up = "low"; +defparam \ent~I .oe_register_mode = "none"; +defparam \ent~I .oe_sync_reset = "none"; +defparam \ent~I .operation_mode = "input"; +defparam \ent~I .output_async_reset = "none"; +defparam \ent~I .output_power_up = "low"; +defparam \ent~I .output_register_mode = "none"; +defparam \ent~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N14 +cycloneii_lcell_comb \inst|count[0]~3 ( +// Equation(s): +// \inst|count[0]~3_combout = (!\clear~combout & (\enc~combout & \ent~combout )) + + .dataa(\clear~combout ), + .datab(vcc), + .datac(\enc~combout ), + .datad(\ent~combout ), + .cin(gnd), + .combout(\inst|count[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~3 .lut_mask = 16'h5000; +defparam \inst|count[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N10 +cycloneii_lcell_comb \inst|count[0]~4 ( +// Equation(s): +// \inst|count[0]~4_combout = (\inst|count [0] & (\inst|count[0]~1_combout )) # (!\inst|count [0] & (((\inst|count[0]~3_combout & !\inst|_~0_combout )))) + + .dataa(\inst|count[0]~1_combout ), + .datab(\inst|count[0]~3_combout ), + .datac(\inst|count [0]), + .datad(\inst|_~0_combout ), + .cin(gnd), + .combout(\inst|count[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~4 .lut_mask = 16'hA0AC; +defparam \inst|count[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N11 +cycloneii_lcell_ff \inst|count[0] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[0]~4_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [0])); + +// Location: LCCOMB_X1_Y8_N30 +cycloneii_lcell_comb \inst|_~2 ( +// Equation(s): +// \inst|_~2_combout = (\ent~combout & (\enc~combout & !\inst|_~0_combout )) + + .dataa(vcc), + .datab(\ent~combout ), + .datac(\enc~combout ), + .datad(\inst|_~0_combout ), + .cin(gnd), + .combout(\inst|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst|_~2 .lut_mask = 16'h00C0; +defparam \inst|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N2 +cycloneii_lcell_comb \inst|count[1]~6 ( +// Equation(s): +// \inst|count[1]~6_combout = (!\clear~combout & (\inst|count [1] $ (((\inst|count [0] & \inst|_~2_combout ))))) + + .dataa(\clear~combout ), + .datab(\inst|count [0]), + .datac(\inst|count [1]), + .datad(\inst|_~2_combout ), + .cin(gnd), + .combout(\inst|count[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[1]~6 .lut_mask = 16'h1450; +defparam \inst|count[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N3 +cycloneii_lcell_ff \inst|count[1] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[1]~6_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [1])); + +// Location: LCCOMB_X1_Y8_N8 +cycloneii_lcell_comb \inst|op_1~1 ( +// Equation(s): +// \inst|op_1~1_combout = \inst|count [2] $ (((\inst|count [1] & \inst|count [0]))) + + .dataa(vcc), + .datab(\inst|count [1]), + .datac(\inst|count [2]), + .datad(\inst|count [0]), + .cin(gnd), + .combout(\inst|op_1~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|op_1~1 .lut_mask = 16'h3CF0; +defparam \inst|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N20 +cycloneii_lcell_comb \inst|count[2]~5 ( +// Equation(s): +// \inst|count[2]~5_combout = (!\clear~combout & ((\inst|_~2_combout & (\inst|op_1~1_combout )) # (!\inst|_~2_combout & ((\inst|count [2]))))) + + .dataa(\clear~combout ), + .datab(\inst|op_1~1_combout ), + .datac(\inst|count [2]), + .datad(\inst|_~2_combout ), + .cin(gnd), + .combout(\inst|count[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[2]~5 .lut_mask = 16'h4450; +defparam \inst|count[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N21 +cycloneii_lcell_ff \inst|count[2] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[2]~5_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [2])); + +// Location: LCCOMB_X1_Y8_N12 +cycloneii_lcell_comb \inst|_~0 ( +// Equation(s): +// \inst|_~0_combout = (\inst|count [3] & (!\inst|count [1] & (!\inst|count [2] & \inst|count [0]))) + + .dataa(\inst|count [3]), + .datab(\inst|count [1]), + .datac(\inst|count [2]), + .datad(\inst|count [0]), + .cin(gnd), + .combout(\inst|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|_~0 .lut_mask = 16'h0200; +defparam \inst|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N18 +cycloneii_lcell_comb \inst|_~1 ( +// Equation(s): +// \inst|_~1_combout = (\inst|_~0_combout & \ent~combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\inst|_~0_combout ), + .datad(\ent~combout ), + .cin(gnd), + .combout(\inst|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|_~1 .lut_mask = 16'hF000; +defparam \inst|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clock~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clock~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clock)); +// synopsys translate_off +defparam \clock~I .input_async_reset = "none"; +defparam \clock~I .input_power_up = "low"; +defparam \clock~I .input_register_mode = "none"; +defparam \clock~I .input_sync_reset = "none"; +defparam \clock~I .oe_async_reset = "none"; +defparam \clock~I .oe_power_up = "low"; +defparam \clock~I .oe_register_mode = "none"; +defparam \clock~I .oe_sync_reset = "none"; +defparam \clock~I .operation_mode = "input"; +defparam \clock~I .output_async_reset = "none"; +defparam \clock~I .output_power_up = "low"; +defparam \clock~I .output_register_mode = "none"; +defparam \clock~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clock~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clock~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clock~clkctrl_outclk )); +// synopsys translate_off +defparam \clock~clkctrl .clock_type = "global clock"; +defparam \clock~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N4 +cycloneii_lcell_comb \inst|op_1~0 ( +// Equation(s): +// \inst|op_1~0_combout = \inst|count [3] $ (((\inst|count [1] & (\inst|count [2] & \inst|count [0])))) + + .dataa(\inst|count [3]), + .datab(\inst|count [1]), + .datac(\inst|count [2]), + .datad(\inst|count [0]), + .cin(gnd), + .combout(\inst|op_1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|op_1~0 .lut_mask = 16'h6AAA; +defparam \inst|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N6 +cycloneii_lcell_comb \inst|count[0]~0 ( +// Equation(s): +// \inst|count[0]~0_combout = (!\clear~combout & (\ent~combout & (\enc~combout & !\inst|_~0_combout ))) + + .dataa(\clear~combout ), + .datab(\ent~combout ), + .datac(\enc~combout ), + .datad(\inst|_~0_combout ), + .cin(gnd), + .combout(\inst|count[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~0 .lut_mask = 16'h0040; +defparam \inst|count[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N16 +cycloneii_lcell_comb \inst|count[3]~2 ( +// Equation(s): +// \inst|count[3]~2_combout = (\inst|count[0]~1_combout & ((\inst|count [3]) # ((\inst|op_1~0_combout & \inst|count[0]~0_combout )))) # (!\inst|count[0]~1_combout & (\inst|op_1~0_combout & ((\inst|count[0]~0_combout )))) + + .dataa(\inst|count[0]~1_combout ), + .datab(\inst|op_1~0_combout ), + .datac(\inst|count [3]), + .datad(\inst|count[0]~0_combout ), + .cin(gnd), + .combout(\inst|count[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[3]~2 .lut_mask = 16'hECA0; +defparam \inst|count[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N17 +cycloneii_lcell_ff \inst|count[3] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[3]~2_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [3])); + +// Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \rco~I ( + .datain(\inst|_~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(rco)); +// synopsys translate_off +defparam \rco~I .input_async_reset = "none"; +defparam \rco~I .input_power_up = "low"; +defparam \rco~I .input_register_mode = "none"; +defparam \rco~I .input_sync_reset = "none"; +defparam \rco~I .oe_async_reset = "none"; +defparam \rco~I .oe_power_up = "low"; +defparam \rco~I .oe_register_mode = "none"; +defparam \rco~I .oe_sync_reset = "none"; +defparam \rco~I .operation_mode = "output"; +defparam \rco~I .output_async_reset = "none"; +defparam \rco~I .output_power_up = "low"; +defparam \rco~I .output_register_mode = "none"; +defparam \rco~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[3]~I ( + .datain(\inst|count [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[3])); +// synopsys translate_off +defparam \value[3]~I .input_async_reset = "none"; +defparam \value[3]~I .input_power_up = "low"; +defparam \value[3]~I .input_register_mode = "none"; +defparam \value[3]~I .input_sync_reset = "none"; +defparam \value[3]~I .oe_async_reset = "none"; +defparam \value[3]~I .oe_power_up = "low"; +defparam \value[3]~I .oe_register_mode = "none"; +defparam \value[3]~I .oe_sync_reset = "none"; +defparam \value[3]~I .operation_mode = "output"; +defparam \value[3]~I .output_async_reset = "none"; +defparam \value[3]~I .output_power_up = "low"; +defparam \value[3]~I .output_register_mode = "none"; +defparam \value[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[2]~I ( + .datain(\inst|count [2]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[2])); +// synopsys translate_off +defparam \value[2]~I .input_async_reset = "none"; +defparam \value[2]~I .input_power_up = "low"; +defparam \value[2]~I .input_register_mode = "none"; +defparam \value[2]~I .input_sync_reset = "none"; +defparam \value[2]~I .oe_async_reset = "none"; +defparam \value[2]~I .oe_power_up = "low"; +defparam \value[2]~I .oe_register_mode = "none"; +defparam \value[2]~I .oe_sync_reset = "none"; +defparam \value[2]~I .operation_mode = "output"; +defparam \value[2]~I .output_async_reset = "none"; +defparam \value[2]~I .output_power_up = "low"; +defparam \value[2]~I .output_register_mode = "none"; +defparam \value[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[1]~I ( + .datain(\inst|count [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[1])); +// synopsys translate_off +defparam \value[1]~I .input_async_reset = "none"; +defparam \value[1]~I .input_power_up = "low"; +defparam \value[1]~I .input_register_mode = "none"; +defparam \value[1]~I .input_sync_reset = "none"; +defparam \value[1]~I .oe_async_reset = "none"; +defparam \value[1]~I .oe_power_up = "low"; +defparam \value[1]~I .oe_register_mode = "none"; +defparam \value[1]~I .oe_sync_reset = "none"; +defparam \value[1]~I .operation_mode = "output"; +defparam \value[1]~I .output_async_reset = "none"; +defparam \value[1]~I .output_power_up = "low"; +defparam \value[1]~I .output_register_mode = "none"; +defparam \value[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[0]~I ( + .datain(\inst|count [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[0])); +// synopsys translate_off +defparam \value[0]~I .input_async_reset = "none"; +defparam \value[0]~I .input_power_up = "low"; +defparam \value[0]~I .input_register_mode = "none"; +defparam \value[0]~I .input_sync_reset = "none"; +defparam \value[0]~I .oe_async_reset = "none"; +defparam \value[0]~I .oe_power_up = "low"; +defparam \value[0]~I .oe_register_mode = "none"; +defparam \value[0]~I .oe_sync_reset = "none"; +defparam \value[0]~I .operation_mode = "output"; +defparam \value[0]~I .output_async_reset = "none"; +defparam \value[0]~I .output_power_up = "low"; +defparam \value[0]~I .output_register_mode = "none"; +defparam \value[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/YL_dec_counter/simulation/modelsim/YL_dec_counter_modelsim.xrf b/YL_dec_counter/simulation/modelsim/YL_dec_counter_modelsim.xrf new file mode 100644 index 0000000..7ba72fc --- /dev/null +++ b/YL_dec_counter/simulation/modelsim/YL_dec_counter_modelsim.xrf @@ -0,0 +1,32 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.bdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_dec_counter.tdf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/YL_DecCounter.vwf +source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_dec_counter/db/YL_dec_counter.cbx.xml +design_name = YL_dec_counter +instance = comp, \inst|count[0]~1 , inst|count[0]~1, YL_dec_counter, 1 +instance = comp, \clear~I , clear, YL_dec_counter, 1 +instance = comp, \enc~I , enc, YL_dec_counter, 1 +instance = comp, \ent~I , ent, YL_dec_counter, 1 +instance = comp, \inst|count[0]~3 , inst|count[0]~3, YL_dec_counter, 1 +instance = comp, \inst|count[0]~4 , inst|count[0]~4, YL_dec_counter, 1 +instance = comp, \inst|count[0] , inst|count[0], YL_dec_counter, 1 +instance = comp, \inst|_~2 , inst|_~2, YL_dec_counter, 1 +instance = comp, \inst|count[1]~6 , inst|count[1]~6, YL_dec_counter, 1 +instance = comp, \inst|count[1] , inst|count[1], YL_dec_counter, 1 +instance = comp, \inst|op_1~1 , inst|op_1~1, YL_dec_counter, 1 +instance = comp, \inst|count[2]~5 , inst|count[2]~5, YL_dec_counter, 1 +instance = comp, \inst|count[2] , inst|count[2], YL_dec_counter, 1 +instance = comp, \inst|_~0 , inst|_~0, YL_dec_counter, 1 +instance = comp, \inst|_~1 , inst|_~1, YL_dec_counter, 1 +instance = comp, \clock~I , clock, YL_dec_counter, 1 +instance = comp, \clock~clkctrl , clock~clkctrl, YL_dec_counter, 1 +instance = comp, \inst|op_1~0 , inst|op_1~0, YL_dec_counter, 1 +instance = comp, \inst|count[0]~0 , inst|count[0]~0, YL_dec_counter, 1 +instance = comp, \inst|count[3]~2 , inst|count[3]~2, YL_dec_counter, 1 +instance = comp, \inst|count[3] , inst|count[3], YL_dec_counter, 1 +instance = comp, \rco~I , rco, YL_dec_counter, 1 +instance = comp, \value[3]~I , value[3], YL_dec_counter, 1 +instance = comp, \value[2]~I , value[2], YL_dec_counter, 1 +instance = comp, \value[1]~I , value[1], YL_dec_counter, 1 +instance = comp, \value[0]~I , value[0], YL_dec_counter, 1 diff --git a/YL_dec_counter/simulation/qsim/YL_dec_counter.do b/YL_dec_counter/simulation/qsim/YL_dec_counter.do new file mode 100644 index 0000000..9244f00 --- /dev/null +++ b/YL_dec_counter/simulation/qsim/YL_dec_counter.do @@ -0,0 +1,10 @@ +onerror {quit -f} +vlib work +vlog -work work YL_dec_counter.vo +vlog -work work YL_dec_counter.vt +vsim -novopt -c -t 1ps -L cycloneii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.YL_dec_counter_vlg_vec_tst +vcd file -direction YL_dec_counter.msim.vcd +vcd add -internal YL_dec_counter_vlg_vec_tst/* +vcd add -internal YL_dec_counter_vlg_vec_tst/i1/* +add wave /* +run -all diff --git a/YL_dec_counter/simulation/qsim/YL_dec_counter.sim.vwf b/YL_dec_counter/simulation/qsim/YL_dec_counter.sim.vwf new file mode 100644 index 0000000..6f96b9c --- /dev/null +++ b/YL_dec_counter/simulation/qsim/YL_dec_counter.sim.vwf @@ -0,0 +1,348 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 1000.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clear") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clock") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("enc") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ent") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("rco") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("value[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +SIGNAL("value[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "value"; +} + +TRANSITION_LIST("clear") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 860.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 100.0; + } +} + +TRANSITION_LIST("clock") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 20; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("enc") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 240.0; + } +} + +TRANSITION_LIST("ent") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 460.0; + } +} + +TRANSITION_LIST("rco") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("value[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 825.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 125.0; + } +} + +TRANSITION_LIST("value[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 175.0; + LEVEL 1 FOR 650.0; + LEVEL 0 FOR 175.0; + } +} + +TRANSITION_LIST("value[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 75.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 550.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 25.0; + } +} + +TRANSITION_LIST("value[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + NODE + { + REPEAT = 2; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + } + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 500.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 25.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clear"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clock"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "enc"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ent"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rco"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "value"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; + CHILDREN = 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "value[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "value[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 5; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_dec_counter/simulation/qsim/YL_dec_counter.vo b/YL_dec_counter/simulation/qsim/YL_dec_counter.vo new file mode 100644 index 0000000..81dab14 --- /dev/null +++ b/YL_dec_counter/simulation/qsim/YL_dec_counter.vo @@ -0,0 +1,681 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +// DATE "05/03/2020 20:26:09" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module YL_dec_counter ( + rco, + enc, + ent, + clock, + clear, + value); +output rco; +input enc; +input ent; +input clock; +input clear; +output [3:0] value; + +// Design Ports Information +// rco => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[3] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[2] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[1] => Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// value[0] => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// ent => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// enc => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clear => Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clock => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \inst|count[0]~1_combout ; +wire \clear~combout ; +wire \enc~combout ; +wire \ent~combout ; +wire \inst|count[0]~3_combout ; +wire \inst|count[0]~4_combout ; +wire \inst|_~2_combout ; +wire \inst|count[1]~6_combout ; +wire \inst|op_1~1_combout ; +wire \inst|count[2]~5_combout ; +wire \inst|_~0_combout ; +wire \inst|_~1_combout ; +wire \clock~combout ; +wire \clock~clkctrl_outclk ; +wire \inst|op_1~0_combout ; +wire \inst|count[0]~0_combout ; +wire \inst|count[3]~2_combout ; +wire [3:0] \inst|count ; + + +// Location: LCCOMB_X1_Y8_N24 +cycloneii_lcell_comb \inst|count[0]~1 ( +// Equation(s): +// \inst|count[0]~1_combout = (!\clear~combout & ((!\ent~combout ) # (!\enc~combout ))) + + .dataa(\clear~combout ), + .datab(vcc), + .datac(\enc~combout ), + .datad(\ent~combout ), + .cin(gnd), + .combout(\inst|count[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~1 .lut_mask = 16'h0555; +defparam \inst|count[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clear~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clear~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clear)); +// synopsys translate_off +defparam \clear~I .input_async_reset = "none"; +defparam \clear~I .input_power_up = "low"; +defparam \clear~I .input_register_mode = "none"; +defparam \clear~I .input_sync_reset = "none"; +defparam \clear~I .oe_async_reset = "none"; +defparam \clear~I .oe_power_up = "low"; +defparam \clear~I .oe_register_mode = "none"; +defparam \clear~I .oe_sync_reset = "none"; +defparam \clear~I .operation_mode = "input"; +defparam \clear~I .output_async_reset = "none"; +defparam \clear~I .output_power_up = "low"; +defparam \clear~I .output_register_mode = "none"; +defparam \clear~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \enc~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\enc~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(enc)); +// synopsys translate_off +defparam \enc~I .input_async_reset = "none"; +defparam \enc~I .input_power_up = "low"; +defparam \enc~I .input_register_mode = "none"; +defparam \enc~I .input_sync_reset = "none"; +defparam \enc~I .oe_async_reset = "none"; +defparam \enc~I .oe_power_up = "low"; +defparam \enc~I .oe_register_mode = "none"; +defparam \enc~I .oe_sync_reset = "none"; +defparam \enc~I .operation_mode = "input"; +defparam \enc~I .output_async_reset = "none"; +defparam \enc~I .output_power_up = "low"; +defparam \enc~I .output_register_mode = "none"; +defparam \enc~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \ent~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\ent~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(ent)); +// synopsys translate_off +defparam \ent~I .input_async_reset = "none"; +defparam \ent~I .input_power_up = "low"; +defparam \ent~I .input_register_mode = "none"; +defparam \ent~I .input_sync_reset = "none"; +defparam \ent~I .oe_async_reset = "none"; +defparam \ent~I .oe_power_up = "low"; +defparam \ent~I .oe_register_mode = "none"; +defparam \ent~I .oe_sync_reset = "none"; +defparam \ent~I .operation_mode = "input"; +defparam \ent~I .output_async_reset = "none"; +defparam \ent~I .output_power_up = "low"; +defparam \ent~I .output_register_mode = "none"; +defparam \ent~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N14 +cycloneii_lcell_comb \inst|count[0]~3 ( +// Equation(s): +// \inst|count[0]~3_combout = (!\clear~combout & (\enc~combout & \ent~combout )) + + .dataa(\clear~combout ), + .datab(vcc), + .datac(\enc~combout ), + .datad(\ent~combout ), + .cin(gnd), + .combout(\inst|count[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~3 .lut_mask = 16'h5000; +defparam \inst|count[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N10 +cycloneii_lcell_comb \inst|count[0]~4 ( +// Equation(s): +// \inst|count[0]~4_combout = (\inst|count [0] & (\inst|count[0]~1_combout )) # (!\inst|count [0] & (((\inst|count[0]~3_combout & !\inst|_~0_combout )))) + + .dataa(\inst|count[0]~1_combout ), + .datab(\inst|count[0]~3_combout ), + .datac(\inst|count [0]), + .datad(\inst|_~0_combout ), + .cin(gnd), + .combout(\inst|count[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~4 .lut_mask = 16'hA0AC; +defparam \inst|count[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N11 +cycloneii_lcell_ff \inst|count[0] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[0]~4_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [0])); + +// Location: LCCOMB_X1_Y8_N30 +cycloneii_lcell_comb \inst|_~2 ( +// Equation(s): +// \inst|_~2_combout = (\ent~combout & (\enc~combout & !\inst|_~0_combout )) + + .dataa(vcc), + .datab(\ent~combout ), + .datac(\enc~combout ), + .datad(\inst|_~0_combout ), + .cin(gnd), + .combout(\inst|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst|_~2 .lut_mask = 16'h00C0; +defparam \inst|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N2 +cycloneii_lcell_comb \inst|count[1]~6 ( +// Equation(s): +// \inst|count[1]~6_combout = (!\clear~combout & (\inst|count [1] $ (((\inst|count [0] & \inst|_~2_combout ))))) + + .dataa(\clear~combout ), + .datab(\inst|count [0]), + .datac(\inst|count [1]), + .datad(\inst|_~2_combout ), + .cin(gnd), + .combout(\inst|count[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[1]~6 .lut_mask = 16'h1450; +defparam \inst|count[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N3 +cycloneii_lcell_ff \inst|count[1] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[1]~6_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [1])); + +// Location: LCCOMB_X1_Y8_N8 +cycloneii_lcell_comb \inst|op_1~1 ( +// Equation(s): +// \inst|op_1~1_combout = \inst|count [2] $ (((\inst|count [1] & \inst|count [0]))) + + .dataa(vcc), + .datab(\inst|count [1]), + .datac(\inst|count [2]), + .datad(\inst|count [0]), + .cin(gnd), + .combout(\inst|op_1~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|op_1~1 .lut_mask = 16'h3CF0; +defparam \inst|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N20 +cycloneii_lcell_comb \inst|count[2]~5 ( +// Equation(s): +// \inst|count[2]~5_combout = (!\clear~combout & ((\inst|_~2_combout & (\inst|op_1~1_combout )) # (!\inst|_~2_combout & ((\inst|count [2]))))) + + .dataa(\clear~combout ), + .datab(\inst|op_1~1_combout ), + .datac(\inst|count [2]), + .datad(\inst|_~2_combout ), + .cin(gnd), + .combout(\inst|count[2]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[2]~5 .lut_mask = 16'h4450; +defparam \inst|count[2]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N21 +cycloneii_lcell_ff \inst|count[2] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[2]~5_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [2])); + +// Location: LCCOMB_X1_Y8_N12 +cycloneii_lcell_comb \inst|_~0 ( +// Equation(s): +// \inst|_~0_combout = (\inst|count [3] & (!\inst|count [1] & (!\inst|count [2] & \inst|count [0]))) + + .dataa(\inst|count [3]), + .datab(\inst|count [1]), + .datac(\inst|count [2]), + .datad(\inst|count [0]), + .cin(gnd), + .combout(\inst|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|_~0 .lut_mask = 16'h0200; +defparam \inst|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N18 +cycloneii_lcell_comb \inst|_~1 ( +// Equation(s): +// \inst|_~1_combout = (\inst|_~0_combout & \ent~combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\inst|_~0_combout ), + .datad(\ent~combout ), + .cin(gnd), + .combout(\inst|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|_~1 .lut_mask = 16'hF000; +defparam \inst|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clock~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clock~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clock)); +// synopsys translate_off +defparam \clock~I .input_async_reset = "none"; +defparam \clock~I .input_power_up = "low"; +defparam \clock~I .input_register_mode = "none"; +defparam \clock~I .input_sync_reset = "none"; +defparam \clock~I .oe_async_reset = "none"; +defparam \clock~I .oe_power_up = "low"; +defparam \clock~I .oe_register_mode = "none"; +defparam \clock~I .oe_sync_reset = "none"; +defparam \clock~I .operation_mode = "input"; +defparam \clock~I .output_async_reset = "none"; +defparam \clock~I .output_power_up = "low"; +defparam \clock~I .output_register_mode = "none"; +defparam \clock~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clock~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clock~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clock~clkctrl_outclk )); +// synopsys translate_off +defparam \clock~clkctrl .clock_type = "global clock"; +defparam \clock~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N4 +cycloneii_lcell_comb \inst|op_1~0 ( +// Equation(s): +// \inst|op_1~0_combout = \inst|count [3] $ (((\inst|count [1] & (\inst|count [2] & \inst|count [0])))) + + .dataa(\inst|count [3]), + .datab(\inst|count [1]), + .datac(\inst|count [2]), + .datad(\inst|count [0]), + .cin(gnd), + .combout(\inst|op_1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|op_1~0 .lut_mask = 16'h6AAA; +defparam \inst|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N6 +cycloneii_lcell_comb \inst|count[0]~0 ( +// Equation(s): +// \inst|count[0]~0_combout = (!\clear~combout & (\ent~combout & (\enc~combout & !\inst|_~0_combout ))) + + .dataa(\clear~combout ), + .datab(\ent~combout ), + .datac(\enc~combout ), + .datad(\inst|_~0_combout ), + .cin(gnd), + .combout(\inst|count[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[0]~0 .lut_mask = 16'h0040; +defparam \inst|count[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N16 +cycloneii_lcell_comb \inst|count[3]~2 ( +// Equation(s): +// \inst|count[3]~2_combout = (\inst|count[0]~1_combout & ((\inst|count [3]) # ((\inst|op_1~0_combout & \inst|count[0]~0_combout )))) # (!\inst|count[0]~1_combout & (\inst|op_1~0_combout & ((\inst|count[0]~0_combout )))) + + .dataa(\inst|count[0]~1_combout ), + .datab(\inst|op_1~0_combout ), + .datac(\inst|count [3]), + .datad(\inst|count[0]~0_combout ), + .cin(gnd), + .combout(\inst|count[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst|count[3]~2 .lut_mask = 16'hECA0; +defparam \inst|count[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y8_N17 +cycloneii_lcell_ff \inst|count[3] ( + .clk(\clock~clkctrl_outclk ), + .datain(\inst|count[3]~2_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|count [3])); + +// Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \rco~I ( + .datain(\inst|_~1_combout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(rco)); +// synopsys translate_off +defparam \rco~I .input_async_reset = "none"; +defparam \rco~I .input_power_up = "low"; +defparam \rco~I .input_register_mode = "none"; +defparam \rco~I .input_sync_reset = "none"; +defparam \rco~I .oe_async_reset = "none"; +defparam \rco~I .oe_power_up = "low"; +defparam \rco~I .oe_register_mode = "none"; +defparam \rco~I .oe_sync_reset = "none"; +defparam \rco~I .operation_mode = "output"; +defparam \rco~I .output_async_reset = "none"; +defparam \rco~I .output_power_up = "low"; +defparam \rco~I .output_register_mode = "none"; +defparam \rco~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[3]~I ( + .datain(\inst|count [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[3])); +// synopsys translate_off +defparam \value[3]~I .input_async_reset = "none"; +defparam \value[3]~I .input_power_up = "low"; +defparam \value[3]~I .input_register_mode = "none"; +defparam \value[3]~I .input_sync_reset = "none"; +defparam \value[3]~I .oe_async_reset = "none"; +defparam \value[3]~I .oe_power_up = "low"; +defparam \value[3]~I .oe_register_mode = "none"; +defparam \value[3]~I .oe_sync_reset = "none"; +defparam \value[3]~I .operation_mode = "output"; +defparam \value[3]~I .output_async_reset = "none"; +defparam \value[3]~I .output_power_up = "low"; +defparam \value[3]~I .output_register_mode = "none"; +defparam \value[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[2]~I ( + .datain(\inst|count [2]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[2])); +// synopsys translate_off +defparam \value[2]~I .input_async_reset = "none"; +defparam \value[2]~I .input_power_up = "low"; +defparam \value[2]~I .input_register_mode = "none"; +defparam \value[2]~I .input_sync_reset = "none"; +defparam \value[2]~I .oe_async_reset = "none"; +defparam \value[2]~I .oe_power_up = "low"; +defparam \value[2]~I .oe_register_mode = "none"; +defparam \value[2]~I .oe_sync_reset = "none"; +defparam \value[2]~I .operation_mode = "output"; +defparam \value[2]~I .output_async_reset = "none"; +defparam \value[2]~I .output_power_up = "low"; +defparam \value[2]~I .output_register_mode = "none"; +defparam \value[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[1]~I ( + .datain(\inst|count [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[1])); +// synopsys translate_off +defparam \value[1]~I .input_async_reset = "none"; +defparam \value[1]~I .input_power_up = "low"; +defparam \value[1]~I .input_register_mode = "none"; +defparam \value[1]~I .input_sync_reset = "none"; +defparam \value[1]~I .oe_async_reset = "none"; +defparam \value[1]~I .oe_power_up = "low"; +defparam \value[1]~I .oe_register_mode = "none"; +defparam \value[1]~I .oe_sync_reset = "none"; +defparam \value[1]~I .operation_mode = "output"; +defparam \value[1]~I .output_async_reset = "none"; +defparam \value[1]~I .output_power_up = "low"; +defparam \value[1]~I .output_register_mode = "none"; +defparam \value[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \value[0]~I ( + .datain(\inst|count [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(value[0])); +// synopsys translate_off +defparam \value[0]~I .input_async_reset = "none"; +defparam \value[0]~I .input_power_up = "low"; +defparam \value[0]~I .input_register_mode = "none"; +defparam \value[0]~I .input_sync_reset = "none"; +defparam \value[0]~I .oe_async_reset = "none"; +defparam \value[0]~I .oe_power_up = "low"; +defparam \value[0]~I .oe_register_mode = "none"; +defparam \value[0]~I .oe_sync_reset = "none"; +defparam \value[0]~I .operation_mode = "output"; +defparam \value[0]~I .output_async_reset = "none"; +defparam \value[0]~I .output_power_up = "low"; +defparam \value[0]~I .output_register_mode = "none"; +defparam \value[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/YL_dec_counter/simulation/qsim/YL_dec_counter.vt b/YL_dec_counter/simulation/qsim/YL_dec_counter.vt new file mode 100644 index 0000000..1406301 --- /dev/null +++ b/YL_dec_counter/simulation/qsim/YL_dec_counter.vt @@ -0,0 +1,306 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "05/03/2020 20:26:08" + +// Verilog Self-Checking Test Bench (with test vectors) for design : YL_dec_counter +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module YL_dec_counter_vlg_sample_tst( + clear, + clock, + enc, + ent, + sampler_tx +); +input clear; +input clock; +input enc; +input ent; +output sampler_tx; + +reg sample; +time current_time; +always @(clear or clock or enc or ent) + +begin + if ($realtime > 0) + begin + if ($realtime == 0 || $realtime != current_time) + begin + if (sample === 1'bx) + sample = 0; + else + sample = ~sample; + end + current_time = $realtime; + end +end + +assign sampler_tx = sample; +endmodule + +module YL_dec_counter_vlg_check_tst ( + rco, + value, + sampler_rx +); +input rco; +input [3:0] value; +input sampler_rx; + +reg rco_expected; +reg [3:0] value_expected; + +reg rco_prev; +reg [3:0] value_prev; + +reg rco_expected_prev; +reg [3:0] value_expected_prev; + +reg last_rco_exp; +reg [3:0] last_value_exp; + +reg trigger; + +integer i; +integer nummismatches; + +reg [1:2] on_first_change ; + + +initial +begin +trigger = 0; +i = 0; +nummismatches = 0; +on_first_change = 2'b1; +end + +// update real /o prevs + +always @(trigger) +begin + rco_prev = rco; + value_prev = value; +end + +// update expected /o prevs + +always @(trigger) +begin + rco_expected_prev = rco_expected; + value_expected_prev = value_expected; +end + + + +// expected rco +initial +begin + rco_expected = 1'bX; +end +// expected value[ 3 ] +initial +begin + value_expected[3] = 1'bX; +end +// expected value[ 2 ] +initial +begin + value_expected[2] = 1'bX; +end +// expected value[ 1 ] +initial +begin + value_expected[1] = 1'bX; +end +// expected value[ 0 ] +initial +begin + value_expected[0] = 1'bX; +end +// generate trigger +always @(rco_expected or rco or value_expected or value) +begin + trigger <= ~trigger; +end + +always @(posedge sampler_rx or negedge sampler_rx) +begin +`ifdef debug_tbench + $display("Scanning pattern %d @time = %t",i,$realtime ); + i = i + 1; + $display("| expected rco = %b | expected value = %b | ",rco_expected_prev,value_expected_prev); + $display("| real rco = %b | real value = %b | ",rco_prev,value_prev); +`endif + if ( + ( rco_expected_prev !== 1'bx ) && ( rco_prev !== rco_expected_prev ) + && ((rco_expected_prev !== last_rco_exp) || + on_first_change[1]) + ) + begin + $display ("ERROR! Vector Mismatch for output port rco :: @time = %t", $realtime); + $display (" Expected value = %b", rco_expected_prev); + $display (" Real value = %b", rco_prev); + nummismatches = nummismatches + 1; + on_first_change[1] = 1'b0; + last_rco_exp = rco_expected_prev; + end + if ( + ( value_expected_prev[0] !== 1'bx ) && ( value_prev[0] !== value_expected_prev[0] ) + && ((value_expected_prev[0] !== last_value_exp[0]) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port value[0] :: @time = %t", $realtime); + $display (" Expected value = %b", value_expected_prev); + $display (" Real value = %b", value_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_value_exp[0] = value_expected_prev[0]; + end + if ( + ( value_expected_prev[1] !== 1'bx ) && ( value_prev[1] !== value_expected_prev[1] ) + && ((value_expected_prev[1] !== last_value_exp[1]) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port value[1] :: @time = %t", $realtime); + $display (" Expected value = %b", value_expected_prev); + $display (" Real value = %b", value_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_value_exp[1] = value_expected_prev[1]; + end + if ( + ( value_expected_prev[2] !== 1'bx ) && ( value_prev[2] !== value_expected_prev[2] ) + && ((value_expected_prev[2] !== last_value_exp[2]) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port value[2] :: @time = %t", $realtime); + $display (" Expected value = %b", value_expected_prev); + $display (" Real value = %b", value_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_value_exp[2] = value_expected_prev[2]; + end + if ( + ( value_expected_prev[3] !== 1'bx ) && ( value_prev[3] !== value_expected_prev[3] ) + && ((value_expected_prev[3] !== last_value_exp[3]) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port value[3] :: @time = %t", $realtime); + $display (" Expected value = %b", value_expected_prev); + $display (" Real value = %b", value_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_value_exp[3] = value_expected_prev[3]; + end + + trigger <= ~trigger; +end +initial + +begin +$timeformat(-12,3," ps",6); +#1000000; +if (nummismatches > 0) + $display ("%d mismatched vectors : Simulation failed !",nummismatches); +else + $display ("Simulation passed !"); +$finish; +end +endmodule + +module YL_dec_counter_vlg_vec_tst(); +// constants +// general purpose registers +reg clear; +reg clock; +reg enc; +reg ent; +// wires +wire rco; +wire [3:0] value; + +wire sampler; + +// assign statements (if any) +YL_dec_counter i1 ( +// port map - connection between master ports and signals/registers + .clear(clear), + .clock(clock), + .enc(enc), + .ent(ent), + .rco(rco), + .value(value) +); + +// clear +initial +begin + clear = 1'b1; + clear = #320000 1'b0; + clear = #280000 1'b1; +end + +// clock +always +begin + clock = 1'b0; + clock = #25000 1'b1; + #25000; +end + +// enc +initial +begin + enc = 1'b1; + enc = #400000 1'b0; + enc = #360000 1'b1; +end + +// ent +initial +begin + ent = 1'b0; +end + +YL_dec_counter_vlg_sample_tst tb_sample ( + .clear(clear), + .clock(clock), + .enc(enc), + .ent(ent), + .sampler_tx(sampler) +); + +YL_dec_counter_vlg_check_tst tb_out( + .rco(rco), + .value(value), + .sampler_rx(sampler) +); +endmodule + diff --git a/YL_pulsar/YL_pulsar.bdf b/YL_pulsar/YL_pulsar.bdf new file mode 100644 index 0000000..5b3dd8d --- /dev/null +++ b/YL_pulsar/YL_pulsar.bdf @@ -0,0 +1,162 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 168 120 336 136) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 168 136 336 152) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "reset" (rect 5 0 30 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 80 184 248 200) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "key" (rect 5 0 24 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 464 120 640 136) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "output" (rect 90 0 120 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 336 96 464 208) + (text "pulsar" (rect 5 0 34 12)(font "Arial" )) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 14 12)(font "Arial" )) + (text "clk" (rect 21 27 35 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "reset" (rect 0 0 24 12)(font "Arial" )) + (text "reset" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "key" (rect 0 0 18 12)(font "Arial" )) + (text "key" (rect 21 59 39 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 128 32) + (output) + (text "o" (rect 0 0 5 12)(font "Arial" )) + (text "o" (rect 103 27 108 39)(font "Arial" )) + (line (pt 128 32)(pt 112 32)) + ) + (drawing + (rectangle (rect 16 16 112 96)) + ) +) +(symbol + (rect 256 176 304 208) + (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6))) + (text "inst99" (rect 3 21 32 33)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(connector + (pt 328 160) + (pt 328 192) +) +(connector + (pt 336 160) + (pt 328 160) +) +(connector + (pt 248 192) + (pt 256 192) +) +(connector + (pt 304 192) + (pt 328 192) +) diff --git a/YL_pulsar/YL_pulsar.qpf b/YL_pulsar/YL_pulsar.qpf new file mode 100644 index 0000000..56ece46 --- /dev/null +++ b/YL_pulsar/YL_pulsar.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 09:42:20 May 04, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "09:42:20 May 04, 2020" + +# Revisions + +PROJECT_REVISION = "YL_pulsar" diff --git a/YL_pulsar/YL_pulsar.qsf b/YL_pulsar/YL_pulsar.qsf new file mode 100644 index 0000000..62b9865 --- /dev/null +++ b/YL_pulsar/YL_pulsar.qsf @@ -0,0 +1,66 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 09:42:20 May 04, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# YL_pulsar_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY YL_pulsar +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:42:20 MAY 04, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name AHDL_FILE YL_pulsar.tdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name BDF_FILE YL_pulsar.bdf +set_global_assignment -name VECTOR_WAVEFORM_FILE YL_pulsar.vwf +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation +set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_pulsar/YL_pulsar.vwf" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_R21 -to key \ No newline at end of file diff --git a/YL_pulsar/YL_pulsar.qws b/YL_pulsar/YL_pulsar.qws new file mode 100644 index 0000000000000000000000000000000000000000..af74d614b1a5963882eb2bc69ccf5ae3281984ec GIT binary patch literal 3046 zcmeH}&uddb5XZmo)kD3AClM40B2t7jO`6iCUW&Dz3W6w75K4Z$Xi02Jl3GP-!J{|5 zdGqSO(0{>;SG@@S8&>P*yLk~!Lxn;O6!$UvW@cx1XJ@}N?=4KI-!7`DvO4N&Rata#UvtZd`kDQjY z3@xglJWoz5$gAwM$!LfD+Cz1dthlB6$i3)tn$devNxe8lJeKvGIL;EeA~CH(bIQW! z;R=CEkV_b8;84!-2qoG={_zx$LgG^t;Z~}gyU=Bv~4>$cseJr_16eXD-DaM z9TFt3GPulS^y%Y=u#ohb;S1cwX-@MN{wp+(%r^0B_+B$UXYg$rlobhU5uda0B{Wqy zSAiO2d>VN&Wv_3f8ZSCIAm~;PX@kx!XwweV<=|f()h}} zNI^3w<1WphndR#8lrMiuU6is=g=ZLOJUR%P8EpOW9eptizY)HOKVgevYzO56%*g0cN-DTs{4iOL^%I0|^%ejC literal 0 HcmV?d00001 diff --git a/YL_pulsar/YL_pulsar.tdf b/YL_pulsar/YL_pulsar.tdf new file mode 100644 index 0000000..6292f61 --- /dev/null +++ b/YL_pulsar/YL_pulsar.tdf @@ -0,0 +1,35 @@ +SUBDESIGN pulsar +( + clk, reset, key : input; + o : output; +) +VARIABLE + ss: MACHINE OF BITS (o) WITH STATES ( + s0 = 0, + s1 = 0, + s2 = 1, + s3 = 0 + ); +BEGIN + ss.clk = clk; + ss.reset = reset; + + TABLE + % current current next % + ss, key => ss; + s0, 0 => s0; + s0, 1 => s1; + s1, 0 => s0; + s1, 1 => s2; + s2, 0 => s0; + s2, 1 => s3; + s3, 0 => s0; + s3, 1 => s3; + END TABLE; + +END; + + + + + \ No newline at end of file diff --git a/YL_pulsar/YL_pulsar.tdf.bak b/YL_pulsar/YL_pulsar.tdf.bak new file mode 100644 index 0000000..e69de29 diff --git a/YL_pulsar/YL_pulsar.vwf b/YL_pulsar/YL_pulsar.vwf new file mode 100644 index 0000000..f8e6fb4 --- /dev/null +++ b/YL_pulsar/YL_pulsar.vwf @@ -0,0 +1,191 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 2.5; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("key") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("output") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 8; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + NODE + { + REPEAT = 40; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("key") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 27.5; + LEVEL 1 FOR 62.5; + LEVEL 0 FOR 27.5; + LEVEL 1 FOR 42.5; + LEVEL 0 FOR 37.5; + LEVEL 1 FOR 152.5; + } +} + +TRANSITION_LIST("output") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 520.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 460.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "key"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "output"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_pulsar/YL_pulsar.vwf.temp b/YL_pulsar/YL_pulsar.vwf.temp new file mode 100644 index 0000000..7ff19f2 --- /dev/null +++ b/YL_pulsar/YL_pulsar.vwf.temp @@ -0,0 +1,224 @@ +/* Simulator = Quartus II Simulator */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("key") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("output") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("reset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("key") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 2.757; + LEVEL 1 FOR 3.1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 6.9; + LEVEL 1 FOR 3.1; + } + LEVEL 0 FOR 4.296; + LEVEL 1 FOR 3.1; + LEVEL 0 FOR 6.747; + LEVEL 1 FOR 1.089; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 6.7; + LEVEL 1 FOR 3.3; + } + LEVEL 0 FOR 6.7; + LEVEL 1 FOR 3.489; + LEVEL 0 FOR 6.5; + LEVEL 1 FOR 3.5; + LEVEL 0 FOR 6.5; + LEVEL 1 FOR 6.997; + LEVEL 0 FOR 13.0; + LEVEL 1 FOR 2.225; + LEVEL 0 FOR 1.49; + LEVEL 1 FOR 1.633; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 1.7; + LEVEL 1 FOR 1.633; + } + LEVEL 0 FOR 0.211; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 1.157; + LEVEL 1 FOR 3.799; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 2.867; + LEVEL 1 FOR 3.799; + } + LEVEL 0 FOR 4.533; + LEVEL 1 FOR 9.8; + LEVEL 0 FOR 17.005; + LEVEL 1 FOR 9.0; + LEVEL 0 FOR 2.116; + LEVEL 1 FOR 3.666; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 3.0; + LEVEL 1 FOR 3.666; + } + LEVEL 0 FOR 4.244; + LEVEL 1 FOR 2.466; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 4.2; + LEVEL 1 FOR 2.466; + } + LEVEL 0 FOR 2.218; + LEVEL 1 FOR 640.0; + } +} + +TRANSITION_LIST("output") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("reset") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "key"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "reset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "output"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/YL_pulsar/db/YL_pulsar.(0).cnf.cdb b/YL_pulsar/db/YL_pulsar.(0).cnf.cdb new file mode 100644 index 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