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ELEC211_FPGA/YL_adder/YL_adder.bdf

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(pt 744 176)
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(pt 800 176)
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(pt 632 184)
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(pt 632 200)
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(pt 192 168)
(pt 376 168)
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(pt 312 184)
)
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(pt 312 184)
(pt 312 200)
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(pt 312 200)
(pt 376 200)
)
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(pt 264 200)
(pt 192 200)
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(pt 264 200)
(pt 264 232)
)
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(pt 264 232)
(pt 376 232)
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(pt 232 216)
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(pt 232 216)
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(pt 320 344)
(pt 328 344)
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(pt 328 184)
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(pt 328 184)
(pt 376 184)
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(pt 344 360)
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(pt 320 376)
(pt 360 376)
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(pt 592 440)
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(pt 592 336)
(pt 592 440)
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(pt 512 336)
(pt 512 96)
)
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)
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(pt 376 136)
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(pt 416 312)
(pt 416 368)
)
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(pt 416 312)
(pt 280 312)
)
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(pt 280 312)
(pt 280 264)
)
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(pt 376 264)
(pt 280 264)
)
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(pt 280 264)
(pt 232 264)
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