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95 lines
4.7 KiB
95 lines
4.7 KiB
# -------------------------------------------------------------------------- # |
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# |
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# Copyright (C) 1991-2013 Altera Corporation |
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# Your use of Altera Corporation's design tools, logic functions |
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# and other software and tools, and its AMPP partner logic |
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# functions, and any output files from any of the foregoing |
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# (including device programming or simulation files), and any |
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# associated documentation or information are expressly subject |
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# to the terms and conditions of the Altera Program License |
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# Subscription Agreement, Altera MegaCore Function License |
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# Agreement, or other applicable license agreement, including, |
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# without limitation, that your use is for the sole purpose of |
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# programming logic devices manufactured by Altera and sold by |
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# Altera or its authorized distributors. Please refer to the |
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# applicable agreement for further details. |
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# |
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# -------------------------------------------------------------------------- # |
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# |
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# Quartus II 64-Bit |
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition |
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# Date created = 12:07:53 May 04, 2020 |
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# |
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# -------------------------------------------------------------------------- # |
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# |
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# Notes: |
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# |
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# 1) The default values for assignments are stored in the file: |
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# YL_adder_assignment_defaults.qdf |
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# If this file doesn't exist, see file: |
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# assignment_defaults.qdf |
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# |
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# 2) Altera recommends that you do not modify this file. This |
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# file is updated automatically by the Quartus II software |
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# and any changes you make may be lost or overwritten. |
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# |
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# -------------------------------------------------------------------------- # |
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set_global_assignment -name FAMILY "Cyclone II" |
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set_global_assignment -name DEVICE EP2C20F484C7 |
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set_global_assignment -name TOP_LEVEL_ENTITY YL_adder |
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" |
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:07:53 MAY 04, 2020" |
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" |
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files |
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 |
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 |
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA |
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 |
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 |
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 |
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set_global_assignment -name BDF_FILE YL_adder.bdf |
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set_global_assignment -name AHDL_FILE YL_7segment.tdf |
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
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set_global_assignment -name AHDL_FILE ../Exp28_Decoder/YL_7segment_sign.tdf |
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set_global_assignment -name AHDL_FILE YL_7segment_sign.tdf |
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set_global_assignment -name AHDL_FILE YL_sign_to_unsign.tdf |
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set_global_assignment -name AHDL_FILE operator.tdf |
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set_global_assignment -name AHDL_FILE overflow.tdf |
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set_global_assignment -name VECTOR_WAVEFORM_FILE YL_adde.vwf |
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set_global_assignment -name SIMULATION_MODE FUNCTIONAL |
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" |
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation |
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation |
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set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF |
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" |
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set_location_assignment PIN_L1 -to clk |
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set_location_assignment PIN_L2 -to reset |
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set_location_assignment PIN_M1 -to isAdd |
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set_location_assignment PIN_L22 -to INPUT_A4 |
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set_location_assignment PIN_L21 -to INPUT_A3 |
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set_location_assignment PIN_M22 -to INPUT_A2 |
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set_location_assignment PIN_V12 -to INPUT_A1 |
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set_location_assignment PIN_W12 -to INPUT_B4 |
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set_location_assignment PIN_U12 -to INPUT_B3 |
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set_location_assignment PIN_U11 -to INPUT_B2 |
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set_location_assignment PIN_M2 -to INPUT_B1 |
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set_location_assignment PIN_D1 -to OUTPUT_G2 |
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set_location_assignment PIN_E2 -to OUTPUT_G |
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set_location_assignment PIN_D2 -to OUTPUT_F2 |
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set_location_assignment PIN_F1 -to OUTPUT_F |
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set_location_assignment PIN_G3 -to OUTPUT_E2 |
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set_location_assignment PIN_F2 -to OUTPUT_E |
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set_location_assignment PIN_H4 -to OUTPUT_D2 |
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set_location_assignment PIN_H1 -to OUTPUT_D |
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set_location_assignment PIN_H5 -to OUTPUT_C2 |
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set_location_assignment PIN_H2 -to OUTPUT_C |
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set_location_assignment PIN_H6 -to OUTPUT_B2 |
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set_location_assignment PIN_J1 -to OUTPUT_B |
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set_location_assignment PIN_E1 -to OUTPUT_A2 |
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set_location_assignment PIN_J2 -to OUTPUT_A |
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set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/ushio/OneDrive/study/uol/ELEC211/YL_adder/YL_adde.vwf" |