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% 0 1 2 3 4 5 6 7 8 9 A b C d E F % |
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% % |
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SUBDESIGN sign |
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( |
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sign : INPUT; |
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a, b, c, d, e, f, g : OUTPUT; |
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) |
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BEGIN |
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DEFAULTS |
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a = VCC; |
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b = VCC; |
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c = VCC; |
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d = VCC; |
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e = VCC; |
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f = VCC; |
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g = VCC; |
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END DEFAULTS; |
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IF sign THEN |
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g = GND; |
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ELSE |
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g = VCC; |
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END iF; |
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END;
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