You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
179 lines
12 KiB
179 lines
12 KiB
Simulator report for YL_dec7748 |
|
Sun May 03 17:01:03 2020 |
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition |
|
|
|
|
|
--------------------- |
|
; Table of Contents ; |
|
--------------------- |
|
1. Legal Notice |
|
2. Simulator Summary |
|
3. Simulator Settings |
|
4. Simulation Waveforms |
|
5. Coverage Summary |
|
6. Complete 1/0-Value Coverage |
|
7. Missing 1-Value Coverage |
|
8. Missing 0-Value Coverage |
|
9. Simulator INI Usage |
|
10. Simulator Messages |
|
|
|
|
|
|
|
---------------- |
|
; Legal Notice ; |
|
---------------- |
|
Copyright (C) 1991-2013 Altera Corporation |
|
Your use of Altera Corporation's design tools, logic functions |
|
and other software and tools, and its AMPP partner logic |
|
functions, and any output files from any of the foregoing |
|
(including device programming or simulation files), and any |
|
associated documentation or information are expressly subject |
|
to the terms and conditions of the Altera Program License |
|
Subscription Agreement, Altera MegaCore Function License |
|
Agreement, or other applicable license agreement, including, |
|
without limitation, that your use is for the sole purpose of |
|
programming logic devices manufactured by Altera and sold by |
|
Altera or its authorized distributors. Please refer to the |
|
applicable agreement for further details. |
|
|
|
|
|
|
|
+--------------------------------------------+ |
|
; Simulator Summary ; |
|
+-----------------------------+--------------+ |
|
; Type ; Value ; |
|
+-----------------------------+--------------+ |
|
; Simulation Start Time ; 0 ps ; |
|
; Simulation End Time ; 1.0 us ; |
|
; Simulation Netlist Size ; 18 nodes ; |
|
; Simulation Coverage ; 100.00 % ; |
|
; Total Number of Transitions ; 224 ; |
|
; Simulation Breakpoints ; 0 ; |
|
; Family ; Cyclone II ; |
|
; Device ; EP2C20F484C7 ; |
|
+-----------------------------+--------------+ |
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
; Simulator Settings ; |
|
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+ |
|
; Option ; Setting ; Default Value ; |
|
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+ |
|
; Simulation mode ; Timing ; Timing ; |
|
; Start time ; 0 ns ; 0 ns ; |
|
; Simulation results format ; VWF ; ; |
|
; Vector input source ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf ; ; |
|
; Add pins automatically to simulation output waveforms ; On ; On ; |
|
; Check outputs ; Off ; Off ; |
|
; Report simulation coverage ; On ; On ; |
|
; Display complete 1/0 value coverage report ; On ; On ; |
|
; Display missing 1-value coverage report ; On ; On ; |
|
; Display missing 0-value coverage report ; On ; On ; |
|
; Detect setup and hold time violations ; Off ; Off ; |
|
; Detect glitches ; Off ; Off ; |
|
; Disable timing delays in Timing Simulation ; Off ; Off ; |
|
; Generate Signal Activity File ; Off ; Off ; |
|
; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ; |
|
; Group bus channels in simulation results ; Off ; Off ; |
|
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ; |
|
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ; |
|
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ; |
|
; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ; |
|
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ; |
|
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+ |
|
|
|
|
|
+----------------------+ |
|
; Simulation Waveforms ; |
|
+----------------------+ |
|
Waveform report data cannot be output to ASCII. |
|
Please use Quartus II 64-Bit to view the waveform report data. |
|
|
|
|
|
+--------------------------------------------------------------------+ |
|
; Coverage Summary ; |
|
+-----------------------------------------------------+--------------+ |
|
; Type ; Value ; |
|
+-----------------------------------------------------+--------------+ |
|
; Total coverage as a percentage ; 100.00 % ; |
|
; Total nodes checked ; 18 ; |
|
; Total output ports checked ; 18 ; |
|
; Total output ports with complete 1/0-value coverage ; 18 ; |
|
; Total output ports with no 1/0-value coverage ; 0 ; |
|
; Total output ports with no 1-value coverage ; 0 ; |
|
; Total output ports with no 0-value coverage ; 0 ; |
|
+-----------------------------------------------------+--------------+ |
|
|
|
|
|
The following table displays output ports that toggle between 1 and 0 during simulation. |
|
+----------------------------------------------------------------------------+ |
|
; Complete 1/0-Value Coverage ; |
|
+----------------------------+----------------------------+------------------+ |
|
; Node Name ; Output Port Name ; Output Port Type ; |
|
+----------------------------+----------------------------+------------------+ |
|
; |YL_dec7748|7448:inst|69~0 ; |YL_dec7748|7448:inst|69~0 ; combout ; |
|
; |YL_dec7748|7448:inst|68~0 ; |YL_dec7748|7448:inst|68~0 ; combout ; |
|
; |YL_dec7748|7448:inst|70 ; |YL_dec7748|7448:inst|70 ; combout ; |
|
; |YL_dec7748|7448:inst|67~0 ; |YL_dec7748|7448:inst|67~0 ; combout ; |
|
; |YL_dec7748|7448:inst|71 ; |YL_dec7748|7448:inst|71 ; combout ; |
|
; |YL_dec7748|7448:inst|66~0 ; |YL_dec7748|7448:inst|66~0 ; combout ; |
|
; |YL_dec7748|7448:inst|72 ; |YL_dec7748|7448:inst|72 ; combout ; |
|
; |YL_dec7748|OUTPUT_A ; |YL_dec7748|OUTPUT_A ; padio ; |
|
; |YL_dec7748|OUTPUT_B ; |YL_dec7748|OUTPUT_B ; padio ; |
|
; |YL_dec7748|OUTPUT_C ; |YL_dec7748|OUTPUT_C ; padio ; |
|
; |YL_dec7748|OUTPUT_D ; |YL_dec7748|OUTPUT_D ; padio ; |
|
; |YL_dec7748|OUTPUT_E ; |YL_dec7748|OUTPUT_E ; padio ; |
|
; |YL_dec7748|OUTPUT_F ; |YL_dec7748|OUTPUT_F ; padio ; |
|
; |YL_dec7748|OUTPUT_G ; |YL_dec7748|OUTPUT_G ; padio ; |
|
; |YL_dec7748|INPUT_B ; |YL_dec7748|INPUT_B~corein ; combout ; |
|
; |YL_dec7748|INPUT_D ; |YL_dec7748|INPUT_D~corein ; combout ; |
|
; |YL_dec7748|INPUT_C ; |YL_dec7748|INPUT_C~corein ; combout ; |
|
; |YL_dec7748|INPUT_A ; |YL_dec7748|INPUT_A~corein ; combout ; |
|
+----------------------------+----------------------------+------------------+ |
|
|
|
|
|
The following table displays output ports that do not toggle to 1 during simulation. |
|
+-------------------------------------------------+ |
|
; Missing 1-Value Coverage ; |
|
+-----------+------------------+------------------+ |
|
; Node Name ; Output Port Name ; Output Port Type ; |
|
+-----------+------------------+------------------+ |
|
|
|
|
|
The following table displays output ports that do not toggle to 0 during simulation. |
|
+-------------------------------------------------+ |
|
; Missing 0-Value Coverage ; |
|
+-----------+------------------+------------------+ |
|
; Node Name ; Output Port Name ; Output Port Type ; |
|
+-----------+------------------+------------------+ |
|
|
|
|
|
+---------------------+ |
|
; Simulator INI Usage ; |
|
+--------+------------+ |
|
; Option ; Usage ; |
|
+--------+------------+ |
|
|
|
|
|
+--------------------+ |
|
; Simulator Messages ; |
|
+--------------------+ |
|
Info: ******************************************************************* |
|
Info: Running Quartus II 64-Bit Simulator |
|
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition |
|
Info: Processing started: Sun May 03 17:01:02 2020 |
|
Info: Command: quartus_sim --simulation_results_format=VWF YL_dec7748 -c YL_dec7748 |
|
Info (324025): Using vector source file "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf" |
|
Info (310003): Option to preserve fewer signal transitions to reduce memory requirements is enabled |
|
Info (310004): Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements. |
|
Info (310002): Simulation partitioned into 1 sub-simulations |
|
Info (328053): Simulation coverage is 100.00 % |
|
Info (328052): Number of transitions in simulation is 224 |
|
Info (324045): Vector file YL_dec7748.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help. |
|
Info: Quartus II 64-Bit Simulator was successful. 0 errors, 0 warnings |
|
Info: Peak virtual memory: 4484 megabytes |
|
Info: Processing ended: Sun May 03 17:01:03 2020 |
|
Info: Elapsed time: 00:00:01 |
|
Info: Total CPU time (on all processors): 00:00:01 |
|
|
|
|
|
|