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444 lines
20 KiB
444 lines
20 KiB
TimeQuest Timing Analyzer report for YL_dec7748 |
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Sun May 03 17:00:29 2020 |
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Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition |
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--------------------- |
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; Table of Contents ; |
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--------------------- |
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1. Legal Notice |
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2. TimeQuest Timing Analyzer Summary |
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3. Parallel Compilation |
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4. Clocks |
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5. Slow Model Fmax Summary |
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6. Slow Model Setup Summary |
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7. Slow Model Hold Summary |
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8. Slow Model Recovery Summary |
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9. Slow Model Removal Summary |
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10. Slow Model Minimum Pulse Width Summary |
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11. Propagation Delay |
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12. Minimum Propagation Delay |
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13. Fast Model Setup Summary |
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14. Fast Model Hold Summary |
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15. Fast Model Recovery Summary |
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16. Fast Model Removal Summary |
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17. Fast Model Minimum Pulse Width Summary |
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18. Propagation Delay |
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19. Minimum Propagation Delay |
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20. Multicorner Timing Analysis Summary |
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21. Progagation Delay |
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22. Minimum Progagation Delay |
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23. Clock Transfers |
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24. Report TCCS |
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25. Report RSKM |
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26. Unconstrained Paths |
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27. TimeQuest Timing Analyzer Messages |
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---------------- |
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; Legal Notice ; |
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---------------- |
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Copyright (C) 1991-2013 Altera Corporation |
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Your use of Altera Corporation's design tools, logic functions |
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and other software and tools, and its AMPP partner logic |
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functions, and any output files from any of the foregoing |
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(including device programming or simulation files), and any |
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associated documentation or information are expressly subject |
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to the terms and conditions of the Altera Program License |
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Subscription Agreement, Altera MegaCore Function License |
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Agreement, or other applicable license agreement, including, |
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without limitation, that your use is for the sole purpose of |
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programming logic devices manufactured by Altera and sold by |
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Altera or its authorized distributors. Please refer to the |
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applicable agreement for further details. |
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+----------------------------------------------------------------------------------------+ |
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; TimeQuest Timing Analyzer Summary ; |
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+--------------------+-------------------------------------------------------------------+ |
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; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; |
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; Revision Name ; YL_dec7748 ; |
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; Device Family ; Cyclone II ; |
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; Device Name ; EP2C20F484C7 ; |
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; Timing Models ; Final ; |
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; Delay Model ; Combined ; |
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; Rise/Fall Delays ; Unavailable ; |
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+--------------------+-------------------------------------------------------------------+ |
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Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. |
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+-------------------------------------+ |
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; Parallel Compilation ; |
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+----------------------------+--------+ |
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; Processors ; Number ; |
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+----------------------------+--------+ |
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; Number detected on machine ; 4 ; |
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; Maximum allowed ; 1 ; |
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+----------------------------+--------+ |
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---------- |
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; Clocks ; |
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---------- |
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No clocks to report. |
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--------------------------- |
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; Slow Model Fmax Summary ; |
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--------------------------- |
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No paths to report. |
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---------------------------- |
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; Slow Model Setup Summary ; |
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---------------------------- |
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No paths to report. |
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--------------------------- |
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; Slow Model Hold Summary ; |
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--------------------------- |
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No paths to report. |
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------------------------------- |
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; Slow Model Recovery Summary ; |
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------------------------------- |
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No paths to report. |
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------------------------------ |
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; Slow Model Removal Summary ; |
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------------------------------ |
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No paths to report. |
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------------------------------------------ |
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; Slow Model Minimum Pulse Width Summary ; |
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------------------------------------------ |
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No paths to report. |
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+--------------------------------------------------------------+ |
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; Propagation Delay ; |
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+------------+-------------+--------+--------+--------+--------+ |
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; Input Port ; Output Port ; RR ; RF ; FR ; FF ; |
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+------------+-------------+--------+--------+--------+--------+ |
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; INPUT_A ; OUTPUT_A ; 13.260 ; 13.260 ; 13.260 ; 13.260 ; |
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; INPUT_A ; OUTPUT_B ; 11.167 ; 11.167 ; 11.167 ; 11.167 ; |
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; INPUT_A ; OUTPUT_C ; 11.414 ; ; ; 11.414 ; |
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; INPUT_A ; OUTPUT_D ; 11.576 ; 11.576 ; 11.576 ; 11.576 ; |
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; INPUT_A ; OUTPUT_E ; ; 11.915 ; 11.915 ; ; |
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; INPUT_A ; OUTPUT_F ; ; 11.165 ; 11.165 ; ; |
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; INPUT_A ; OUTPUT_G ; ; 11.134 ; 11.134 ; ; |
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; INPUT_B ; OUTPUT_A ; 13.063 ; 13.063 ; 13.063 ; 13.063 ; |
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; INPUT_B ; OUTPUT_B ; 10.961 ; 10.961 ; 10.961 ; 10.961 ; |
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; INPUT_B ; OUTPUT_C ; ; 11.208 ; 11.208 ; ; |
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; INPUT_B ; OUTPUT_D ; 11.341 ; 11.341 ; 11.341 ; 11.341 ; |
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; INPUT_B ; OUTPUT_E ; 11.754 ; ; ; 11.754 ; |
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; INPUT_B ; OUTPUT_F ; ; 10.967 ; 10.967 ; ; |
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; INPUT_B ; OUTPUT_G ; 10.907 ; 10.907 ; 10.907 ; 10.907 ; |
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; INPUT_C ; OUTPUT_A ; 13.132 ; 13.132 ; 13.132 ; 13.132 ; |
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; INPUT_C ; OUTPUT_B ; ; 11.046 ; 11.046 ; ; |
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; INPUT_C ; OUTPUT_C ; 11.293 ; 11.293 ; 11.293 ; 11.293 ; |
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; INPUT_C ; OUTPUT_D ; 11.455 ; 11.455 ; 11.455 ; 11.455 ; |
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; INPUT_C ; OUTPUT_E ; ; 11.838 ; 11.838 ; ; |
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; INPUT_C ; OUTPUT_F ; 11.037 ; ; ; 11.037 ; |
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; INPUT_C ; OUTPUT_G ; 11.006 ; 11.006 ; 11.006 ; 11.006 ; |
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; INPUT_D ; OUTPUT_A ; 12.550 ; 12.550 ; 12.550 ; 12.550 ; |
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; INPUT_D ; OUTPUT_B ; ; 10.467 ; 10.467 ; ; |
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; INPUT_D ; OUTPUT_C ; ; 10.711 ; 10.711 ; ; |
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; INPUT_D ; OUTPUT_F ; 10.455 ; ; ; 10.455 ; |
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; INPUT_D ; OUTPUT_G ; 10.396 ; ; ; 10.396 ; |
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+------------+-------------+--------+--------+--------+--------+ |
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+--------------------------------------------------------------+ |
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; Minimum Propagation Delay ; |
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+------------+-------------+--------+--------+--------+--------+ |
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; Input Port ; Output Port ; RR ; RF ; FR ; FF ; |
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+------------+-------------+--------+--------+--------+--------+ |
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; INPUT_A ; OUTPUT_A ; 13.260 ; 13.260 ; 13.260 ; 13.260 ; |
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; INPUT_A ; OUTPUT_B ; 11.167 ; 11.167 ; 11.167 ; 11.167 ; |
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; INPUT_A ; OUTPUT_C ; 11.414 ; ; ; 11.414 ; |
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; INPUT_A ; OUTPUT_D ; 11.576 ; 11.576 ; 11.576 ; 11.576 ; |
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; INPUT_A ; OUTPUT_E ; ; 11.915 ; 11.915 ; ; |
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; INPUT_A ; OUTPUT_F ; ; 11.165 ; 11.165 ; ; |
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; INPUT_A ; OUTPUT_G ; ; 11.134 ; 11.134 ; ; |
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; INPUT_B ; OUTPUT_A ; 13.063 ; 13.063 ; 13.063 ; 13.063 ; |
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; INPUT_B ; OUTPUT_B ; 10.961 ; 10.961 ; 10.961 ; 10.961 ; |
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; INPUT_B ; OUTPUT_C ; ; 11.208 ; 11.208 ; ; |
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; INPUT_B ; OUTPUT_D ; 11.341 ; 11.341 ; 11.341 ; 11.341 ; |
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; INPUT_B ; OUTPUT_E ; 11.754 ; ; ; 11.754 ; |
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; INPUT_B ; OUTPUT_F ; ; 10.967 ; 10.967 ; ; |
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; INPUT_B ; OUTPUT_G ; 10.907 ; 10.907 ; 10.907 ; 10.907 ; |
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; INPUT_C ; OUTPUT_A ; 13.132 ; 13.132 ; 13.132 ; 13.132 ; |
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; INPUT_C ; OUTPUT_B ; ; 11.046 ; 11.046 ; ; |
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; INPUT_C ; OUTPUT_C ; 11.293 ; 11.293 ; 11.293 ; 11.293 ; |
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; INPUT_C ; OUTPUT_D ; 11.455 ; 11.455 ; 11.455 ; 11.455 ; |
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; INPUT_C ; OUTPUT_E ; ; 11.838 ; 11.838 ; ; |
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; INPUT_C ; OUTPUT_F ; 11.037 ; ; ; 11.037 ; |
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; INPUT_C ; OUTPUT_G ; 11.006 ; 11.006 ; 11.006 ; 11.006 ; |
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; INPUT_D ; OUTPUT_A ; 12.550 ; 12.550 ; 12.550 ; 12.550 ; |
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; INPUT_D ; OUTPUT_B ; ; 10.467 ; 10.467 ; ; |
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; INPUT_D ; OUTPUT_C ; ; 10.711 ; 10.711 ; ; |
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; INPUT_D ; OUTPUT_F ; 10.455 ; ; ; 10.455 ; |
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; INPUT_D ; OUTPUT_G ; 10.396 ; ; ; 10.396 ; |
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+------------+-------------+--------+--------+--------+--------+ |
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---------------------------- |
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; Fast Model Setup Summary ; |
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---------------------------- |
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No paths to report. |
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--------------------------- |
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; Fast Model Hold Summary ; |
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--------------------------- |
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No paths to report. |
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------------------------------- |
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; Fast Model Recovery Summary ; |
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------------------------------- |
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No paths to report. |
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------------------------------ |
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; Fast Model Removal Summary ; |
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------------------------------ |
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No paths to report. |
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------------------------------------------ |
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; Fast Model Minimum Pulse Width Summary ; |
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------------------------------------------ |
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No paths to report. |
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+----------------------------------------------------------+ |
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; Propagation Delay ; |
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+------------+-------------+-------+-------+-------+-------+ |
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; Input Port ; Output Port ; RR ; RF ; FR ; FF ; |
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+------------+-------------+-------+-------+-------+-------+ |
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; INPUT_A ; OUTPUT_A ; 6.571 ; 6.571 ; 6.571 ; 6.571 ; |
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; INPUT_A ; OUTPUT_B ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; |
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; INPUT_A ; OUTPUT_C ; 5.804 ; ; ; 5.804 ; |
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; INPUT_A ; OUTPUT_D ; 5.915 ; 5.915 ; 5.915 ; 5.915 ; |
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; INPUT_A ; OUTPUT_E ; ; 5.997 ; 5.997 ; ; |
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; INPUT_A ; OUTPUT_F ; ; 5.727 ; 5.727 ; ; |
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; INPUT_A ; OUTPUT_G ; ; 5.695 ; 5.695 ; ; |
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; INPUT_B ; OUTPUT_A ; 6.383 ; 6.383 ; 6.383 ; 6.383 ; |
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; INPUT_B ; OUTPUT_B ; 5.531 ; 5.531 ; 5.531 ; 5.531 ; |
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; INPUT_B ; OUTPUT_C ; ; 5.611 ; 5.611 ; ; |
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; INPUT_B ; OUTPUT_D ; 5.720 ; 5.720 ; 5.720 ; 5.720 ; |
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; INPUT_B ; OUTPUT_E ; 5.802 ; ; ; 5.802 ; |
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; INPUT_B ; OUTPUT_F ; ; 5.541 ; 5.541 ; ; |
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; INPUT_B ; OUTPUT_G ; 5.510 ; 5.510 ; 5.510 ; 5.510 ; |
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; INPUT_C ; OUTPUT_A ; 6.508 ; 6.508 ; 6.508 ; 6.508 ; |
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; INPUT_C ; OUTPUT_B ; ; 5.669 ; 5.669 ; ; |
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; INPUT_C ; OUTPUT_C ; 5.747 ; 5.747 ; 5.747 ; 5.747 ; |
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; INPUT_C ; OUTPUT_D ; 5.857 ; 5.857 ; 5.857 ; 5.857 ; |
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; INPUT_C ; OUTPUT_E ; ; 5.940 ; 5.940 ; ; |
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; INPUT_C ; OUTPUT_F ; 5.661 ; ; ; 5.661 ; |
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; INPUT_C ; OUTPUT_G ; 5.629 ; 5.629 ; 5.629 ; 5.629 ; |
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; INPUT_D ; OUTPUT_A ; 6.185 ; 6.185 ; 6.185 ; 6.185 ; |
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; INPUT_D ; OUTPUT_B ; ; 5.349 ; 5.349 ; ; |
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; INPUT_D ; OUTPUT_C ; ; 5.434 ; 5.434 ; ; |
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; INPUT_D ; OUTPUT_F ; 5.338 ; ; ; 5.338 ; |
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; INPUT_D ; OUTPUT_G ; 5.310 ; ; ; 5.310 ; |
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+------------+-------------+-------+-------+-------+-------+ |
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+----------------------------------------------------------+ |
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; Minimum Propagation Delay ; |
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+------------+-------------+-------+-------+-------+-------+ |
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; Input Port ; Output Port ; RR ; RF ; FR ; FF ; |
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+------------+-------------+-------+-------+-------+-------+ |
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; INPUT_A ; OUTPUT_A ; 6.571 ; 6.571 ; 6.571 ; 6.571 ; |
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; INPUT_A ; OUTPUT_B ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; |
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; INPUT_A ; OUTPUT_C ; 5.804 ; ; ; 5.804 ; |
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; INPUT_A ; OUTPUT_D ; 5.915 ; 5.915 ; 5.915 ; 5.915 ; |
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; INPUT_A ; OUTPUT_E ; ; 5.997 ; 5.997 ; ; |
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; INPUT_A ; OUTPUT_F ; ; 5.727 ; 5.727 ; ; |
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; INPUT_A ; OUTPUT_G ; ; 5.695 ; 5.695 ; ; |
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; INPUT_B ; OUTPUT_A ; 6.383 ; 6.383 ; 6.383 ; 6.383 ; |
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; INPUT_B ; OUTPUT_B ; 5.531 ; 5.531 ; 5.531 ; 5.531 ; |
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; INPUT_B ; OUTPUT_C ; ; 5.611 ; 5.611 ; ; |
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; INPUT_B ; OUTPUT_D ; 5.720 ; 5.720 ; 5.720 ; 5.720 ; |
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; INPUT_B ; OUTPUT_E ; 5.802 ; ; ; 5.802 ; |
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; INPUT_B ; OUTPUT_F ; ; 5.541 ; 5.541 ; ; |
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; INPUT_B ; OUTPUT_G ; 5.510 ; 5.510 ; 5.510 ; 5.510 ; |
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; INPUT_C ; OUTPUT_A ; 6.508 ; 6.508 ; 6.508 ; 6.508 ; |
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; INPUT_C ; OUTPUT_B ; ; 5.669 ; 5.669 ; ; |
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; INPUT_C ; OUTPUT_C ; 5.747 ; 5.747 ; 5.747 ; 5.747 ; |
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; INPUT_C ; OUTPUT_D ; 5.857 ; 5.857 ; 5.857 ; 5.857 ; |
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; INPUT_C ; OUTPUT_E ; ; 5.940 ; 5.940 ; ; |
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; INPUT_C ; OUTPUT_F ; 5.661 ; ; ; 5.661 ; |
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; INPUT_C ; OUTPUT_G ; 5.629 ; 5.629 ; 5.629 ; 5.629 ; |
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; INPUT_D ; OUTPUT_A ; 6.185 ; 6.185 ; 6.185 ; 6.185 ; |
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; INPUT_D ; OUTPUT_B ; ; 5.349 ; 5.349 ; ; |
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; INPUT_D ; OUTPUT_C ; ; 5.434 ; 5.434 ; ; |
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; INPUT_D ; OUTPUT_F ; 5.338 ; ; ; 5.338 ; |
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; INPUT_D ; OUTPUT_G ; 5.310 ; ; ; 5.310 ; |
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+------------+-------------+-------+-------+-------+-------+ |
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+----------------------------------------------------------------------------+ |
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; Multicorner Timing Analysis Summary ; |
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+------------------+-------+------+----------+---------+---------------------+ |
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; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; |
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+------------------+-------+------+----------+---------+---------------------+ |
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; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; |
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; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; |
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+------------------+-------+------+----------+---------+---------------------+ |
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+--------------------------------------------------------------+ |
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; Progagation Delay ; |
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+------------+-------------+--------+--------+--------+--------+ |
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; Input Port ; Output Port ; RR ; RF ; FR ; FF ; |
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+------------+-------------+--------+--------+--------+--------+ |
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; INPUT_A ; OUTPUT_A ; 13.260 ; 13.260 ; 13.260 ; 13.260 ; |
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; INPUT_A ; OUTPUT_B ; 11.167 ; 11.167 ; 11.167 ; 11.167 ; |
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; INPUT_A ; OUTPUT_C ; 11.414 ; ; ; 11.414 ; |
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; INPUT_A ; OUTPUT_D ; 11.576 ; 11.576 ; 11.576 ; 11.576 ; |
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; INPUT_A ; OUTPUT_E ; ; 11.915 ; 11.915 ; ; |
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; INPUT_A ; OUTPUT_F ; ; 11.165 ; 11.165 ; ; |
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; INPUT_A ; OUTPUT_G ; ; 11.134 ; 11.134 ; ; |
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; INPUT_B ; OUTPUT_A ; 13.063 ; 13.063 ; 13.063 ; 13.063 ; |
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; INPUT_B ; OUTPUT_B ; 10.961 ; 10.961 ; 10.961 ; 10.961 ; |
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; INPUT_B ; OUTPUT_C ; ; 11.208 ; 11.208 ; ; |
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; INPUT_B ; OUTPUT_D ; 11.341 ; 11.341 ; 11.341 ; 11.341 ; |
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; INPUT_B ; OUTPUT_E ; 11.754 ; ; ; 11.754 ; |
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; INPUT_B ; OUTPUT_F ; ; 10.967 ; 10.967 ; ; |
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; INPUT_B ; OUTPUT_G ; 10.907 ; 10.907 ; 10.907 ; 10.907 ; |
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; INPUT_C ; OUTPUT_A ; 13.132 ; 13.132 ; 13.132 ; 13.132 ; |
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; INPUT_C ; OUTPUT_B ; ; 11.046 ; 11.046 ; ; |
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; INPUT_C ; OUTPUT_C ; 11.293 ; 11.293 ; 11.293 ; 11.293 ; |
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; INPUT_C ; OUTPUT_D ; 11.455 ; 11.455 ; 11.455 ; 11.455 ; |
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; INPUT_C ; OUTPUT_E ; ; 11.838 ; 11.838 ; ; |
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; INPUT_C ; OUTPUT_F ; 11.037 ; ; ; 11.037 ; |
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; INPUT_C ; OUTPUT_G ; 11.006 ; 11.006 ; 11.006 ; 11.006 ; |
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; INPUT_D ; OUTPUT_A ; 12.550 ; 12.550 ; 12.550 ; 12.550 ; |
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; INPUT_D ; OUTPUT_B ; ; 10.467 ; 10.467 ; ; |
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; INPUT_D ; OUTPUT_C ; ; 10.711 ; 10.711 ; ; |
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; INPUT_D ; OUTPUT_F ; 10.455 ; ; ; 10.455 ; |
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; INPUT_D ; OUTPUT_G ; 10.396 ; ; ; 10.396 ; |
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+------------+-------------+--------+--------+--------+--------+ |
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+----------------------------------------------------------+ |
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; Minimum Progagation Delay ; |
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+------------+-------------+-------+-------+-------+-------+ |
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; Input Port ; Output Port ; RR ; RF ; FR ; FF ; |
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+------------+-------------+-------+-------+-------+-------+ |
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; INPUT_A ; OUTPUT_A ; 6.571 ; 6.571 ; 6.571 ; 6.571 ; |
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; INPUT_A ; OUTPUT_B ; 5.726 ; 5.726 ; 5.726 ; 5.726 ; |
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; INPUT_A ; OUTPUT_C ; 5.804 ; ; ; 5.804 ; |
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; INPUT_A ; OUTPUT_D ; 5.915 ; 5.915 ; 5.915 ; 5.915 ; |
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; INPUT_A ; OUTPUT_E ; ; 5.997 ; 5.997 ; ; |
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; INPUT_A ; OUTPUT_F ; ; 5.727 ; 5.727 ; ; |
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; INPUT_A ; OUTPUT_G ; ; 5.695 ; 5.695 ; ; |
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; INPUT_B ; OUTPUT_A ; 6.383 ; 6.383 ; 6.383 ; 6.383 ; |
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; INPUT_B ; OUTPUT_B ; 5.531 ; 5.531 ; 5.531 ; 5.531 ; |
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; INPUT_B ; OUTPUT_C ; ; 5.611 ; 5.611 ; ; |
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; INPUT_B ; OUTPUT_D ; 5.720 ; 5.720 ; 5.720 ; 5.720 ; |
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; INPUT_B ; OUTPUT_E ; 5.802 ; ; ; 5.802 ; |
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; INPUT_B ; OUTPUT_F ; ; 5.541 ; 5.541 ; ; |
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; INPUT_B ; OUTPUT_G ; 5.510 ; 5.510 ; 5.510 ; 5.510 ; |
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; INPUT_C ; OUTPUT_A ; 6.508 ; 6.508 ; 6.508 ; 6.508 ; |
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; INPUT_C ; OUTPUT_B ; ; 5.669 ; 5.669 ; ; |
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; INPUT_C ; OUTPUT_C ; 5.747 ; 5.747 ; 5.747 ; 5.747 ; |
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; INPUT_C ; OUTPUT_D ; 5.857 ; 5.857 ; 5.857 ; 5.857 ; |
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; INPUT_C ; OUTPUT_E ; ; 5.940 ; 5.940 ; ; |
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; INPUT_C ; OUTPUT_F ; 5.661 ; ; ; 5.661 ; |
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; INPUT_C ; OUTPUT_G ; 5.629 ; 5.629 ; 5.629 ; 5.629 ; |
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; INPUT_D ; OUTPUT_A ; 6.185 ; 6.185 ; 6.185 ; 6.185 ; |
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; INPUT_D ; OUTPUT_B ; ; 5.349 ; 5.349 ; ; |
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; INPUT_D ; OUTPUT_C ; ; 5.434 ; 5.434 ; ; |
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; INPUT_D ; OUTPUT_F ; 5.338 ; ; ; 5.338 ; |
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; INPUT_D ; OUTPUT_G ; 5.310 ; ; ; 5.310 ; |
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+------------+-------------+-------+-------+-------+-------+ |
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------------------- |
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; Clock Transfers ; |
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------------------- |
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Nothing to report. |
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--------------- |
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; Report TCCS ; |
|
--------------- |
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No dedicated SERDES Transmitter circuitry present in device or used in design |
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--------------- |
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; Report RSKM ; |
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--------------- |
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No dedicated SERDES Receiver circuitry present in device or used in design |
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+------------------------------------------------+ |
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; Unconstrained Paths ; |
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+---------------------------------+-------+------+ |
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; Property ; Setup ; Hold ; |
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+---------------------------------+-------+------+ |
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; Illegal Clocks ; 0 ; 0 ; |
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; Unconstrained Clocks ; 0 ; 0 ; |
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; Unconstrained Input Ports ; 4 ; 4 ; |
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; Unconstrained Input Port Paths ; 26 ; 26 ; |
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; Unconstrained Output Ports ; 7 ; 7 ; |
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; Unconstrained Output Port Paths ; 26 ; 26 ; |
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+---------------------------------+-------+------+ |
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+------------------------------------+ |
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; TimeQuest Timing Analyzer Messages ; |
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+------------------------------------+ |
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Info: ******************************************************************* |
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Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer |
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Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition |
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Info: Processing started: Sun May 03 17:00:28 2020 |
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Info: Command: quartus_sta YL_dec7748 -c YL_dec7748 |
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Info: qsta_default_script.tcl version: #1 |
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Warning (20028): Parallel compilation is not licensed and has been disabled |
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Info (21077): Low junction temperature is 0 degrees C |
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Info (21077): High junction temperature is 85 degrees C |
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Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_dec7748.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. |
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Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" |
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Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. |
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Warning (332068): No clocks defined in design. |
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Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON |
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Info (332159): No clocks to report |
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Info: Analyzing Slow Model |
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Info (332140): No fmax paths to report |
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Info (332140): No Setup paths to report |
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Info (332140): No Hold paths to report |
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Info (332140): No Recovery paths to report |
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Info (332140): No Removal paths to report |
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Info (332140): No Minimum Pulse Width paths to report |
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Info (332001): The selected device family is not supported by the report_metastability command. |
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Info: Analyzing Fast Model |
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Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" |
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Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. |
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Warning (332068): No clocks defined in design. |
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Info (332140): No Setup paths to report |
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Info (332140): No Hold paths to report |
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Info (332140): No Recovery paths to report |
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Info (332140): No Removal paths to report |
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Info (332140): No Minimum Pulse Width paths to report |
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Info (332001): The selected device family is not supported by the report_metastability command. |
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Info (332102): Design is not fully constrained for setup requirements |
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Info (332102): Design is not fully constrained for hold requirements |
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Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings |
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Info: Peak virtual memory: 4541 megabytes |
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Info: Processing ended: Sun May 03 17:00:29 2020 |
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Info: Elapsed time: 00:00:01 |
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Info: Total CPU time (on all processors): 00:00:01 |
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