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366 lines
12 KiB
366 lines
12 KiB
#ifndef _ASM_X86_HYPERV_H |
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#define _ASM_X86_HYPERV_H |
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#include <linux/types.h> |
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/* |
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* The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent |
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* is set by CPUID(HvCpuIdFunctionVersionAndFeatures). |
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*/ |
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#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 |
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#define HYPERV_CPUID_INTERFACE 0x40000001 |
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#define HYPERV_CPUID_VERSION 0x40000002 |
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#define HYPERV_CPUID_FEATURES 0x40000003 |
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#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 |
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#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 |
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#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 |
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#define HYPERV_CPUID_MIN 0x40000005 |
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#define HYPERV_CPUID_MAX 0x4000ffff |
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/* |
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* Feature identification. EAX indicates which features are available |
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* to the partition based upon the current partition privileges. |
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*/ |
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/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ |
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#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) |
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/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ |
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#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) |
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/* Partition reference TSC MSR is available */ |
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#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) |
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/* A partition's reference time stamp counter (TSC) page */ |
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021 |
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/* |
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* There is a single feature flag that signifies the presence of the MSR |
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* that can be used to retrieve both the local APIC Timer frequency as |
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* well as the TSC frequency. |
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*/ |
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/* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */ |
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#define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11) |
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/* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */ |
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#define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11) |
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/* |
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* Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM |
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* and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available |
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*/ |
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#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) |
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/* |
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* Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through |
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* HV_X64_MSR_STIMER3_COUNT) available |
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*/ |
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#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) |
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/* |
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* APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) |
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* are available |
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*/ |
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#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) |
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/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ |
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#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) |
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/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ |
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#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) |
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/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ |
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#define HV_X64_MSR_RESET_AVAILABLE (1 << 7) |
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/* |
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* Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, |
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* HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, |
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* HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available |
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*/ |
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#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) |
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/* |
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* Feature identification: EBX indicates which flags were specified at |
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* partition creation. The format is the same as the partition creation |
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* flag structure defined in section Partition Creation Flags. |
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*/ |
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#define HV_X64_CREATE_PARTITIONS (1 << 0) |
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#define HV_X64_ACCESS_PARTITION_ID (1 << 1) |
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#define HV_X64_ACCESS_MEMORY_POOL (1 << 2) |
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#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) |
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#define HV_X64_POST_MESSAGES (1 << 4) |
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#define HV_X64_SIGNAL_EVENTS (1 << 5) |
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#define HV_X64_CREATE_PORT (1 << 6) |
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#define HV_X64_CONNECT_PORT (1 << 7) |
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#define HV_X64_ACCESS_STATS (1 << 8) |
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#define HV_X64_DEBUGGING (1 << 11) |
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#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) |
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#define HV_X64_CONFIGURE_PROFILER (1 << 13) |
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/* |
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* Feature identification. EDX indicates which miscellaneous features |
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* are available to the partition. |
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*/ |
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/* The MWAIT instruction is available (per section MONITOR / MWAIT) */ |
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#define HV_X64_MWAIT_AVAILABLE (1 << 0) |
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/* Guest debugging support is available */ |
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#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) |
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/* Performance Monitor support is available*/ |
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#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) |
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/* Support for physical CPU dynamic partitioning events is available*/ |
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#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) |
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/* |
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* Support for passing hypercall input parameter block via XMM |
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* registers is available |
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*/ |
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#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) |
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/* Support for a virtual guest idle state is available */ |
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#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) |
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/* Guest crash data handler available */ |
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#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) |
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/* |
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* Implementation recommendations. Indicates which behaviors the hypervisor |
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* recommends the OS implement for optimal performance. |
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*/ |
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/* |
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* Recommend using hypercall for address space switches rather |
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* than MOV to CR3 instruction |
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*/ |
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#define HV_X64_MWAIT_RECOMMENDED (1 << 0) |
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/* Recommend using hypercall for local TLB flushes rather |
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* than INVLPG or MOV to CR3 instructions */ |
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#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) |
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/* |
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* Recommend using hypercall for remote TLB flushes rather |
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* than inter-processor interrupts |
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*/ |
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#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) |
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/* |
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* Recommend using MSRs for accessing APIC registers |
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* EOI, ICR and TPR rather than their memory-mapped counterparts |
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*/ |
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#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) |
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/* Recommend using the hypervisor-provided MSR to initiate a system RESET */ |
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#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) |
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/* |
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* Recommend using relaxed timing for this partition. If used, |
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* the VM should disable any watchdog timeouts that rely on the |
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* timely delivery of external interrupts |
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*/ |
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#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) |
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/* MSR used to identify the guest OS. */ |
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#define HV_X64_MSR_GUEST_OS_ID 0x40000000 |
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/* MSR used to setup pages used to communicate with the hypervisor. */ |
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#define HV_X64_MSR_HYPERCALL 0x40000001 |
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/* MSR used to provide vcpu index */ |
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#define HV_X64_MSR_VP_INDEX 0x40000002 |
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/* MSR used to reset the guest OS. */ |
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#define HV_X64_MSR_RESET 0x40000003 |
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/* MSR used to provide vcpu runtime in 100ns units */ |
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#define HV_X64_MSR_VP_RUNTIME 0x40000010 |
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/* MSR used to read the per-partition time reference counter */ |
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#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 |
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/* MSR used to retrieve the TSC frequency */ |
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#define HV_X64_MSR_TSC_FREQUENCY 0x40000022 |
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/* MSR used to retrieve the local APIC timer frequency */ |
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#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 |
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/* Define the virtual APIC registers */ |
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#define HV_X64_MSR_EOI 0x40000070 |
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#define HV_X64_MSR_ICR 0x40000071 |
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#define HV_X64_MSR_TPR 0x40000072 |
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#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 |
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/* Define synthetic interrupt controller model specific registers. */ |
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#define HV_X64_MSR_SCONTROL 0x40000080 |
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#define HV_X64_MSR_SVERSION 0x40000081 |
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#define HV_X64_MSR_SIEFP 0x40000082 |
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#define HV_X64_MSR_SIMP 0x40000083 |
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#define HV_X64_MSR_EOM 0x40000084 |
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#define HV_X64_MSR_SINT0 0x40000090 |
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#define HV_X64_MSR_SINT1 0x40000091 |
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#define HV_X64_MSR_SINT2 0x40000092 |
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#define HV_X64_MSR_SINT3 0x40000093 |
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#define HV_X64_MSR_SINT4 0x40000094 |
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#define HV_X64_MSR_SINT5 0x40000095 |
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#define HV_X64_MSR_SINT6 0x40000096 |
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#define HV_X64_MSR_SINT7 0x40000097 |
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#define HV_X64_MSR_SINT8 0x40000098 |
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#define HV_X64_MSR_SINT9 0x40000099 |
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#define HV_X64_MSR_SINT10 0x4000009A |
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#define HV_X64_MSR_SINT11 0x4000009B |
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#define HV_X64_MSR_SINT12 0x4000009C |
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#define HV_X64_MSR_SINT13 0x4000009D |
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#define HV_X64_MSR_SINT14 0x4000009E |
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#define HV_X64_MSR_SINT15 0x4000009F |
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/* |
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* Synthetic Timer MSRs. Four timers per vcpu. |
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*/ |
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#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 |
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#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 |
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#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 |
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#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 |
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#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 |
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#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 |
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#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 |
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#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 |
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/* Hyper-V guest crash notification MSR's */ |
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#define HV_X64_MSR_CRASH_P0 0x40000100 |
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#define HV_X64_MSR_CRASH_P1 0x40000101 |
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#define HV_X64_MSR_CRASH_P2 0x40000102 |
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#define HV_X64_MSR_CRASH_P3 0x40000103 |
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#define HV_X64_MSR_CRASH_P4 0x40000104 |
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#define HV_X64_MSR_CRASH_CTL 0x40000105 |
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#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) |
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#define HV_X64_MSR_CRASH_PARAMS \ |
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(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) |
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#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 |
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#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 |
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#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ |
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(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) |
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/* Declare the various hypercall operations. */ |
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#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 |
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#define HVCALL_POST_MESSAGE 0x005c |
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#define HVCALL_SIGNAL_EVENT 0x005d |
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#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001 |
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#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12 |
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#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \ |
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(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) |
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#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 |
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#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 |
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#define HV_PROCESSOR_POWER_STATE_C0 0 |
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#define HV_PROCESSOR_POWER_STATE_C1 1 |
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#define HV_PROCESSOR_POWER_STATE_C2 2 |
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#define HV_PROCESSOR_POWER_STATE_C3 3 |
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/* hypercall status code */ |
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#define HV_STATUS_SUCCESS 0 |
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#define HV_STATUS_INVALID_HYPERCALL_CODE 2 |
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#define HV_STATUS_INVALID_HYPERCALL_INPUT 3 |
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#define HV_STATUS_INVALID_ALIGNMENT 4 |
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#define HV_STATUS_INSUFFICIENT_MEMORY 11 |
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#define HV_STATUS_INVALID_CONNECTION_ID 18 |
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#define HV_STATUS_INSUFFICIENT_BUFFERS 19 |
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typedef struct _HV_REFERENCE_TSC_PAGE { |
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__u32 tsc_sequence; |
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__u32 res1; |
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__u64 tsc_scale; |
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__s64 tsc_offset; |
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} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; |
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/* Define the number of synthetic interrupt sources. */ |
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#define HV_SYNIC_SINT_COUNT (16) |
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/* Define the expected SynIC version. */ |
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#define HV_SYNIC_VERSION_1 (0x1) |
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#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) |
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#define HV_SYNIC_SIMP_ENABLE (1ULL << 0) |
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#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) |
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#define HV_SYNIC_SINT_MASKED (1ULL << 16) |
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#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) |
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#define HV_SYNIC_SINT_VECTOR_MASK (0xFF) |
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#define HV_SYNIC_STIMER_COUNT (4) |
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/* Define synthetic interrupt controller message constants. */ |
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#define HV_MESSAGE_SIZE (256) |
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#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) |
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#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) |
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/* Define hypervisor message types. */ |
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enum hv_message_type { |
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HVMSG_NONE = 0x00000000, |
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/* Memory access messages. */ |
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HVMSG_UNMAPPED_GPA = 0x80000000, |
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HVMSG_GPA_INTERCEPT = 0x80000001, |
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/* Timer notification messages. */ |
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HVMSG_TIMER_EXPIRED = 0x80000010, |
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/* Error messages. */ |
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HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, |
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HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, |
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HVMSG_UNSUPPORTED_FEATURE = 0x80000022, |
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/* Trace buffer complete messages. */ |
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HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, |
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/* Platform-specific processor intercept messages. */ |
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HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, |
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HVMSG_X64_MSR_INTERCEPT = 0x80010001, |
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HVMSG_X64_CPUID_INTERCEPT = 0x80010002, |
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HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, |
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HVMSG_X64_APIC_EOI = 0x80010004, |
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HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 |
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}; |
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/* Define synthetic interrupt controller message flags. */ |
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union hv_message_flags { |
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__u8 asu8; |
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struct { |
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__u8 msg_pending:1; |
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__u8 reserved:7; |
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}; |
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}; |
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/* Define port identifier type. */ |
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union hv_port_id { |
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__u32 asu32; |
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struct { |
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__u32 id:24; |
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__u32 reserved:8; |
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} u; |
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}; |
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/* Define synthetic interrupt controller message header. */ |
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struct hv_message_header { |
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__u32 message_type; |
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__u8 payload_size; |
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union hv_message_flags message_flags; |
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__u8 reserved[2]; |
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union { |
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__u64 sender; |
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union hv_port_id port; |
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}; |
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}; |
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/* Define synthetic interrupt controller message format. */ |
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struct hv_message { |
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struct hv_message_header header; |
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union { |
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__u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; |
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} u; |
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}; |
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/* Define the synthetic interrupt message page layout. */ |
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struct hv_message_page { |
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struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; |
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}; |
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/* Define timer message payload structure. */ |
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struct hv_timer_message_payload { |
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__u32 timer_index; |
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__u32 reserved; |
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__u64 expiration_time; /* When the timer expired */ |
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__u64 delivery_time; /* When the message was delivered */ |
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}; |
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#define HV_STIMER_ENABLE (1ULL << 0) |
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#define HV_STIMER_PERIODIC (1ULL << 1) |
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#define HV_STIMER_LAZY (1ULL << 2) |
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#define HV_STIMER_AUTOENABLE (1ULL << 3) |
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#define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F) |
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#endif
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