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ELEC211_FPGA
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final

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master
IoTcat 3 years ago
parent 8962599cde
commit ffd7bc357c
55 changed files with 399 additions and 484 deletions
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  1. BIN
      Exp28_Decoder/.pplq.rdb
  2. BIN
      Exp28_Decoder/YL_7SegmentDecoder.qws
  3. 12
      Exp28_Decoder/YL_7SegmentDecoder_nativelink_simulation.rpt
  4. 5
      Exp28_Decoder/db/YL_7SegmentDecoder.analyze_file.qmsg
  5. 12
      Exp28_Decoder/db/YL_7SegmentDecoder.asm.qmsg
  6. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.asm.rdb
  7. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.cmp.bpm
  8. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.cmp.cdb
  9. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.cmp.hdb
  10. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.cmp.rdb
  11. 2
      Exp28_Decoder/db/YL_7SegmentDecoder.db_info
  12. 10
      Exp28_Decoder/db/YL_7SegmentDecoder.eda.qmsg
  13. 94
      Exp28_Decoder/db/YL_7SegmentDecoder.fit.qmsg
  14. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.cdb
  15. 302
      Exp28_Decoder/db/YL_7SegmentDecoder.hier_info
  16. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.map.bpm
  17. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.map.cdb
  18. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.map.hdb
  19. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.map.kpt
  20. 36
      Exp28_Decoder/db/YL_7SegmentDecoder.map.qmsg
  21. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.map.rdb
  22. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.map_bb.cdb
  23. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.map_bb.hdb
  24. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.pre_map.hdb
  25. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.rtlv.hdb
  26. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.sgdiff.cdb
  27. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.sgdiff.hdb
  28. 2
      Exp28_Decoder/db/YL_7SegmentDecoder.smart_action.txt
  29. 60
      Exp28_Decoder/db/YL_7SegmentDecoder.sta.qmsg
  30. BIN
      Exp28_Decoder/db/YL_7SegmentDecoder.sta_cmp.7_slow.tdb
  31. 7
      Exp28_Decoder/db/YL_7SegmentDecoder.tmw_info
  32. 119
      Exp28_Decoder/db/prev_cmp_YL_7SegmentDecoder.qmsg
  33. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.cmp.cdb
  34. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.cmp.hdb
  35. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.map.cdb
  36. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.map.dpi
  37. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.map.hbdb.cdb
  38. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.map.hbdb.hdb
  39. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.map.hdb
  40. BIN
      Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.map.kpt
  41. 66
      Exp28_Decoder/output_files/YL_7SegmentDecoder.asm.rpt
  42. 2
      Exp28_Decoder/output_files/YL_7SegmentDecoder.done
  43. 30
      Exp28_Decoder/output_files/YL_7SegmentDecoder.eda.rpt
  44. 28
      Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.rpt
  45. 2
      Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.summary
  46. 26
      Exp28_Decoder/output_files/YL_7SegmentDecoder.flow.rpt
  47. 28
      Exp28_Decoder/output_files/YL_7SegmentDecoder.map.rpt
  48. 2
      Exp28_Decoder/output_files/YL_7SegmentDecoder.map.summary
  49. BIN
      Exp28_Decoder/output_files/YL_7SegmentDecoder.sof
  50. 8
      Exp28_Decoder/output_files/YL_7SegmentDecoder.sta.rpt
  51. 2
      Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder.vo
  52. 2
      Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_fast.vo
  53. 22
      Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_modelsim.xrf
  54. 2
      Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v.sdo
  55. 2
      Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v_fast.sdo

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Exp28_Decoder/.pplq.rdb
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Exp28_Decoder/YL_7SegmentDecoder.qws
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12
Exp28_Decoder/YL_7SegmentDecoder_nativelink_simulation.rpt
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@ -0,0 +1,12 @@
Info: Start Nativelink Simulation process
Error: NativeLink did not detect any HDL files in the project
Error: NativeLink simulation flow was NOT successful
================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode: NONE
Nativelink TCL script failed with errorInfo: NativeLink did not detect any HDL files in the project
(procedure "run_eda_simulation_tool" line 1)
invoked from within
"run_eda_simulation_tool eda_opts_hash"

5
Exp28_Decoder/db/YL_7SegmentDecoder.analyze_file.qmsg
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@ -0,0 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1605753220500 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus II 64-Bit " "Running Quartus II 64-Bit Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1605753220501 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 19 10:33:40 2020 " "Processing started: Thu Nov 19 10:33:40 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1605753220501 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1605753220501 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder --analyze_file=C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder --analyze_file=C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1605753220501 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1605753222269 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4583 " "Peak virtual memory: 4583 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1605753222391 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 19 10:33:42 2020 " "Processing ended: Thu Nov 19 10:33:42 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1605753222391 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1605753222391 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1605753222391 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1605753222391 ""}

12
Exp28_Decoder/db/YL_7SegmentDecoder.asm.qmsg
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@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588514806555 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588514806556 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 22:06:46 2020 " "Processing started: Sun May 03 22:06:46 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588514806556 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1588514806556 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1588514806556 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1588514807749 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1588514807795 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4552 " "Peak virtual memory: 4552 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514808374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:06:48 2020 " "Processing ended: Sun May 03 22:06:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514808374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514808374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514808374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1588514808374 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1605758736296 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1605758736297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 19 12:05:36 2020 " "Processing started: Thu Nov 19 12:05:36 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1605758736297 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1605758736297 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1605758736297 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1605758737433 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1605758737497 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4552 " "Peak virtual memory: 4552 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1605758738491 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 19 12:05:38 2020 " "Processing ended: Thu Nov 19 12:05:38 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1605758738491 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1605758738491 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1605758738491 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1605758738491 ""}

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Exp28_Decoder/db/YL_7SegmentDecoder.asm.rdb
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Exp28_Decoder/db/YL_7SegmentDecoder.cmp.bpm
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Exp28_Decoder/db/YL_7SegmentDecoder.cmp.cdb
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Exp28_Decoder/db/YL_7SegmentDecoder.cmp.hdb
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Exp28_Decoder/db/YL_7SegmentDecoder.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Sun May 03 20:37:39 2020
Creation_Time = Thu Nov 19 15:42:12 2020

10
Exp28_Decoder/db/YL_7SegmentDecoder.eda.qmsg
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@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588514812218 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 22:06:51 2020 " "Processing started: Sun May 03 22:06:51 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588514812219 ""}
{ "Info" "IWSC_DONE_HDL_DUAL_SDO_GENERATION" "YL_7SegmentDecoder.vo\", \"YL_7SegmentDecoder_fast.vo YL_7SegmentDecoder_v.sdo YL_7SegmentDecoder_v_fast.sdo C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/ simulation " "Generated files \"YL_7SegmentDecoder.vo\", \"YL_7SegmentDecoder_fast.vo\", \"YL_7SegmentDecoder_v.sdo\" and \"YL_7SegmentDecoder_v_fast.sdo\" in directory \"C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204026 "Generated files \"%1!s!\", \"%2!s!\" and \"%3!s!\" in directory \"%4!s!\" for EDA %5!s! tool" 0 0 "Quartus II" 0 -1 1588514812743 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4529 " "Peak virtual memory: 4529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514812789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:06:52 2020 " "Processing ended: Sun May 03 22:06:52 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588514812789 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1605758742535 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1605758742537 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 19 12:05:42 2020 " "Processing started: Thu Nov 19 12:05:42 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1605758742537 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1605758742537 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1605758742537 ""}
{ "Info" "IWSC_DONE_HDL_DUAL_SDO_GENERATION" "YL_7SegmentDecoder.vo\", \"YL_7SegmentDecoder_fast.vo YL_7SegmentDecoder_v.sdo YL_7SegmentDecoder_v_fast.sdo C:/opt/git/ELEC211_FPGA/Exp28_Decoder/simulation/modelsim/ simulation " "Generated files \"YL_7SegmentDecoder.vo\", \"YL_7SegmentDecoder_fast.vo\", \"YL_7SegmentDecoder_v.sdo\" and \"YL_7SegmentDecoder_v_fast.sdo\" in directory \"C:/opt/git/ELEC211_FPGA/Exp28_Decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204026 "Generated files \"%1!s!\", \"%2!s!\" and \"%3!s!\" in directory \"%4!s!\" for EDA %5!s! tool" 0 0 "Quartus II" 0 -1 1605758743076 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4529 " "Peak virtual memory: 4529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1605758743112 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 19 12:05:43 2020 " "Processing ended: Thu Nov 19 12:05:43 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1605758743112 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1605758743112 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1605758743112 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1605758743112 ""}

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Exp28_Decoder/db/YL_7SegmentDecoder.fit.qmsg
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Exp28_Decoder/db/YL_7SegmentDecoder.fnsim.cdb
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Exp28_Decoder/db/YL_7SegmentDecoder.hier_info
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@ -22,95 +22,95 @@ OUTPUT_G7 <= inst17.DB_MAX_OUTPUT_PORT_TYPE
|YL_7SegmentDecoder|7segment:inst_
i[0] => _~4.IN0
i[0] => b~1.IN3
i[0] => _~10.IN0
i[0] => a~6.IN3
i[0] => _~15.IN0
i[0] => a~8.IN3
i[0] => _~19.IN0
i[0] => a~12.IN3
i[0] => _~23.IN0
i[0] => a~16.IN3
i[0] => _~27.IN0
i[0] => c~2.IN3
i[0] => _~30.IN0
i[0] => b~6.IN3
i[0] => _~32.IN0
i[0] => a~24.IN3
i[1] => _~3.IN0
i[1] => _~7.IN0
i[0] => _.IN0
i[0] => b~0.IN3
i[0] => _.IN0
i[0] => a~2.IN3
i[0] => _.IN0
i[0] => a~3.IN3
i[0] => _.IN0
i[0] => a~5.IN3
i[0] => _.IN0
i[0] => a~7.IN3
i[0] => _.IN0
i[0] => c~0.IN3
i[0] => _.IN0
i[0] => b~2.IN3
i[0] => _.IN0
i[0] => a~11.IN3
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~1.IN2
i[1] => a~2.IN2
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~4.IN2
i[1] => a~6.IN2
i[1] => _~14.IN0
i[1] => _~17.IN0
i[1] => a~5.IN2
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~8.IN2
i[1] => c~0.IN2
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~10.IN2
i[1] => a~12.IN2
i[1] => _~22.IN0
i[1] => _~25.IN0
i[1] => a~18.IN2
i[1] => c~2.IN2
i[1] => _~29.IN0
i[1] => _~31.IN0
i[1] => a~22.IN2
i[1] => a~24.IN2
i[2] => _~2.IN0
i[2] => _~6.IN0
i[2] => _~9.IN0
i[2] => _~12.IN0
i[2] => b~4.IN1
i[2] => a~8.IN1
i[1] => a~11.IN2
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => b~1.IN1
i[2] => a~3.IN1
i[2] => a~4.IN1
i[2] => a~5.IN1
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => a~9.IN1
i[2] => b~2.IN1
i[2] => a~10.IN1
i[2] => a~12.IN1
i[2] => _~21.IN0
i[2] => _~24.IN0
i[2] => _~26.IN0
i[2] => _~28.IN0
i[2] => a~20.IN1
i[2] => b~6.IN1
i[2] => a~22.IN1
i[2] => a~24.IN1
i[3] => _~1.IN0
i[3] => _~5.IN0
i[3] => _~8.IN0
i[3] => _~11.IN0
i[3] => _~13.IN0
i[3] => _~16.IN0
i[3] => _~18.IN0
i[3] => _~20.IN0
i[3] => a~14.IN0
i[3] => a~16.IN0
i[3] => a~18.IN0
i[3] => c~2.IN0
i[3] => a~20.IN0
i[3] => b~6.IN0
i[3] => a~22.IN0
i[3] => a~24.IN0
a <= a~2.DB_MAX_OUTPUT_PORT_TYPE
b <= b~2.DB_MAX_OUTPUT_PORT_TYPE
c <= c~0.DB_MAX_OUTPUT_PORT_TYPE
d <= d~0.DB_MAX_OUTPUT_PORT_TYPE
e <= e~0.DB_MAX_OUTPUT_PORT_TYPE
f <= f~0.DB_MAX_OUTPUT_PORT_TYPE
g <= g~0.DB_MAX_OUTPUT_PORT_TYPE
i[2] => a~11.IN1
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => a~6.IN0
i[3] => a~7.IN0
i[3] => a~8.IN0
i[3] => c~0.IN0
i[3] => a~9.IN0
i[3] => b~2.IN0
i[3] => a~10.IN0
i[3] => a~11.IN0
a <= a.DB_MAX_OUTPUT_PORT_TYPE
b <= b.DB_MAX_OUTPUT_PORT_TYPE
c <= c.DB_MAX_OUTPUT_PORT_TYPE
d <= d.DB_MAX_OUTPUT_PORT_TYPE
e <= e.DB_MAX_OUTPUT_PORT_TYPE
f <= f.DB_MAX_OUTPUT_PORT_TYPE
g <= g.DB_MAX_OUTPUT_PORT_TYPE
|YL_7SegmentDecoder|dec_count:inst8
enc => _~2.IN0
enc => _~13.IN0
ent => _~2.IN1
ent => _~13.IN1
ent => rco~0.IN1
enc => _.IN0
enc => _.IN0
ent => _.IN1
ent => _.IN1
ent => rco.IN1
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clear => _~1.IN0
clear => _.IN0
value[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
value[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
value[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
value[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
rco <= rco~0.DB_MAX_OUTPUT_PORT_TYPE
rco <= rco.DB_MAX_OUTPUT_PORT_TYPE
|YL_7SegmentDecoder|sec_cnt:inst10
@ -140,98 +140,98 @@ clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
second <= second~2.DB_MAX_OUTPUT_PORT_TYPE
second <= second.DB_MAX_OUTPUT_PORT_TYPE
|YL_7SegmentDecoder|7segment:inst_12
i[0] => _~4.IN0
i[0] => b~1.IN3
i[0] => _~10.IN0
i[0] => a~6.IN3
i[0] => _~15.IN0
i[0] => a~8.IN3
i[0] => _~19.IN0
i[0] => a~12.IN3
i[0] => _~23.IN0
i[0] => a~16.IN3
i[0] => _~27.IN0
i[0] => c~2.IN3
i[0] => _~30.IN0
i[0] => b~6.IN3
i[0] => _~32.IN0
i[0] => a~24.IN3
i[1] => _~3.IN0
i[1] => _~7.IN0
i[0] => _.IN0
i[0] => b~0.IN3
i[0] => _.IN0
i[0] => a~2.IN3
i[0] => _.IN0
i[0] => a~3.IN3
i[0] => _.IN0
i[0] => a~5.IN3
i[0] => _.IN0
i[0] => a~7.IN3
i[0] => _.IN0
i[0] => c~0.IN3
i[0] => _.IN0
i[0] => b~2.IN3
i[0] => _.IN0
i[0] => a~11.IN3
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~1.IN2
i[1] => a~2.IN2
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~4.IN2
i[1] => a~6.IN2
i[1] => _~14.IN0
i[1] => _~17.IN0
i[1] => a~5.IN2
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~8.IN2
i[1] => c~0.IN2
i[1] => _.IN0
i[1] => _.IN0
i[1] => a~10.IN2
i[1] => a~12.IN2
i[1] => _~22.IN0
i[1] => _~25.IN0
i[1] => a~18.IN2
i[1] => c~2.IN2
i[1] => _~29.IN0
i[1] => _~31.IN0
i[1] => a~22.IN2
i[1] => a~24.IN2
i[2] => _~2.IN0
i[2] => _~6.IN0
i[2] => _~9.IN0
i[2] => _~12.IN0
i[2] => b~4.IN1
i[2] => a~8.IN1
i[1] => a~11.IN2
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => b~1.IN1
i[2] => a~3.IN1
i[2] => a~4.IN1
i[2] => a~5.IN1
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => _.IN0
i[2] => a~9.IN1
i[2] => b~2.IN1
i[2] => a~10.IN1
i[2] => a~12.IN1
i[2] => _~21.IN0
i[2] => _~24.IN0
i[2] => _~26.IN0
i[2] => _~28.IN0
i[2] => a~20.IN1
i[2] => b~6.IN1
i[2] => a~22.IN1
i[2] => a~24.IN1
i[3] => _~1.IN0
i[3] => _~5.IN0
i[3] => _~8.IN0
i[3] => _~11.IN0
i[3] => _~13.IN0
i[3] => _~16.IN0
i[3] => _~18.IN0
i[3] => _~20.IN0
i[3] => a~14.IN0
i[3] => a~16.IN0
i[3] => a~18.IN0
i[3] => c~2.IN0
i[3] => a~20.IN0
i[3] => b~6.IN0
i[3] => a~22.IN0
i[3] => a~24.IN0
a <= a~2.DB_MAX_OUTPUT_PORT_TYPE
b <= b~2.DB_MAX_OUTPUT_PORT_TYPE
c <= c~0.DB_MAX_OUTPUT_PORT_TYPE
d <= d~0.DB_MAX_OUTPUT_PORT_TYPE
e <= e~0.DB_MAX_OUTPUT_PORT_TYPE
f <= f~0.DB_MAX_OUTPUT_PORT_TYPE
g <= g~0.DB_MAX_OUTPUT_PORT_TYPE
i[2] => a~11.IN1
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => _.IN0
i[3] => a~6.IN0
i[3] => a~7.IN0
i[3] => a~8.IN0
i[3] => c~0.IN0
i[3] => a~9.IN0
i[3] => b~2.IN0
i[3] => a~10.IN0
i[3] => a~11.IN0
a <= a.DB_MAX_OUTPUT_PORT_TYPE
b <= b.DB_MAX_OUTPUT_PORT_TYPE
c <= c.DB_MAX_OUTPUT_PORT_TYPE
d <= d.DB_MAX_OUTPUT_PORT_TYPE
e <= e.DB_MAX_OUTPUT_PORT_TYPE
f <= f.DB_MAX_OUTPUT_PORT_TYPE
g <= g.DB_MAX_OUTPUT_PORT_TYPE
|YL_7SegmentDecoder|dec_count:inst11
enc => _~2.IN0
enc => _~13.IN0
ent => _~2.IN1
ent => _~13.IN1
ent => rco~0.IN1
enc => _.IN0
enc => _.IN0
ent => _.IN1
ent => _.IN1
ent => rco.IN1
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clear => _~1.IN0
clear => _.IN0
value[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
value[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
value[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
value[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
rco <= rco~0.DB_MAX_OUTPUT_PORT_TYPE
rco <= rco.DB_MAX_OUTPUT_PORT_TYPE

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Exp28_Decoder/db/YL_7SegmentDecoder.map.bpm
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Exp28_Decoder/db/YL_7SegmentDecoder.map.kpt
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Exp28_Decoder/db/YL_7SegmentDecoder.map.qmsg
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@ -1,18 +1,18 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588514795837 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588514795838 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 22:06:35 2020 " "Processing started: Sun May 03 22:06:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588514795838 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588514795838 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588514795838 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588514796633 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec_counter.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dec_count " "Found entity 1: dec_count" { } { { "YL_dec_counter.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_dec_counter.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514796737 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514796737 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_7SegmentDecoder " "Found entity 1: YL_7SegmentDecoder" { } { { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514796746 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514796746 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7segment " "Found entity 1: 7segment" { } { { "YL_7SegmentDecoder.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514796752 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514796752 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder2.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_7SegmentDecoder2 " "Found entity 1: YL_7SegmentDecoder2" { } { { "YL_7SegmentDecoder2.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder2.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514796756 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514796756 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_sec_cnt.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_sec_cnt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sec_cnt " "Found entity 1: sec_cnt" { } { { "YL_sec_cnt.tdf" "" { Text "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_sec_cnt.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514796766 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514796766 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_cascade.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_cascade.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_Cascade " "Found entity 1: YL_Cascade" { } { { "YL_Cascade.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_Cascade.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588514796771 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588514796771 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "YL_7SegmentDecoder " "Elaborating entity \"YL_7SegmentDecoder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588514796816 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7segment 7segment:inst_ " "Elaborating entity \"7segment\" for hierarchy \"7segment:inst_\"" { } { { "YL_7SegmentDecoder.bdf" "inst_" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 184 384 512 360 "inst_" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514796829 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst8 " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst8\"" { } { { "YL_7SegmentDecoder.bdf" "inst8" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 184 168 328 296 "inst8" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514796834 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sec_cnt sec_cnt:inst10 " "Elaborating entity \"sec_cnt\" for hierarchy \"sec_cnt:inst10\"" { } { { "YL_7SegmentDecoder.bdf" "inst10" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 16 120 264 96 "inst10" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514796840 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst11 " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst11\"" { } { { "YL_7SegmentDecoder.bdf" "inst11" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 424 160 320 536 "inst11" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588514796847 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1588514797766 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588514797766 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "88 " "Implemented 88 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1588514797819 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1588514797819 ""} { "Info" "ICUT_CUT_TM_LCELLS" "71 " "Implemented 71 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1588514797819 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1588514797819 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4608 " "Peak virtual memory: 4608 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514797856 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:06:37 2020 " "Processing ended: Sun May 03 22:06:37 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514797856 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514797856 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514797856 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588514797856 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1605758723875 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1605758723875 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 19 12:05:23 2020 " "Processing started: Thu Nov 19 12:05:23 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1605758723875 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1605758723875 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1605758723875 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1605758724439 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec_counter.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dec_count " "Found entity 1: dec_count" { } { { "YL_dec_counter.tdf" "" { Text "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_dec_counter.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1605758724520 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1605758724520 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_7SegmentDecoder " "Found entity 1: YL_7SegmentDecoder" { } { { "YL_7SegmentDecoder.bdf" "" { Schematic "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1605758724523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1605758724523 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7segment " "Found entity 1: 7segment" { } { { "YL_7SegmentDecoder.tdf" "" { Text "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1605758724532 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1605758724532 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_7segmentdecoder2.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_7segmentdecoder2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_7SegmentDecoder2 " "Found entity 1: YL_7SegmentDecoder2" { } { { "YL_7SegmentDecoder2.bdf" "" { Schematic "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder2.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1605758724539 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1605758724539 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_sec_cnt.tdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_sec_cnt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sec_cnt " "Found entity 1: sec_cnt" { } { { "YL_sec_cnt.tdf" "" { Text "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_sec_cnt.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1605758724547 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1605758724547 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_cascade.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_cascade.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_Cascade " "Found entity 1: YL_Cascade" { } { { "YL_Cascade.bdf" "" { Schematic "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_Cascade.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1605758724554 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1605758724554 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "YL_7SegmentDecoder " "Elaborating entity \"YL_7SegmentDecoder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1605758724627 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7segment 7segment:inst_ " "Elaborating entity \"7segment\" for hierarchy \"7segment:inst_\"" { } { { "YL_7SegmentDecoder.bdf" "inst_" { Schematic "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 184 384 512 360 "inst_" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1605758724645 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst8 " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst8\"" { } { { "YL_7SegmentDecoder.bdf" "inst8" { Schematic "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 184 168 328 296 "inst8" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1605758724660 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sec_cnt sec_cnt:inst10 " "Elaborating entity \"sec_cnt\" for hierarchy \"sec_cnt:inst10\"" { } { { "YL_7SegmentDecoder.bdf" "inst10" { Schematic "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 16 120 264 96 "inst10" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1605758724675 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_count dec_count:inst11 " "Elaborating entity \"dec_count\" for hierarchy \"dec_count:inst11\"" { } { { "YL_7SegmentDecoder.bdf" "inst11" { Schematic "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf" { { 424 160 320 536 "inst11" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1605758724693 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1605758725579 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1605758725579 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "88 " "Implemented 88 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1605758725696 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1605758725696 ""} { "Info" "ICUT_CUT_TM_LCELLS" "71 " "Implemented 71 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1605758725696 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1605758725696 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4608 " "Peak virtual memory: 4608 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1605758725717 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 19 12:05:25 2020 " "Processing ended: Thu Nov 19 12:05:25 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1605758725717 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1605758725717 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1605758725717 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1605758725717 ""}

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Exp28_Decoder/db/YL_7SegmentDecoder.smart_action.txt
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Exp28_Decoder/db/YL_7SegmentDecoder.sta.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588514809854 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588514809855 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 22:06:49 2020 " "Processing started: Sun May 03 22:06:49 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588514809855 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588514809855 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588514809856 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588514810018 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588514810232 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588514810321 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588514810321 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_7SegmentDecoder.sdc " "Synopsys Design Constraints File file not found: 'YL_7SegmentDecoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588514810515 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588514810516 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810517 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810517 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588514810522 ""}
{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588514810545 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588514810554 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.665 " "Worst-case setup slack is -3.665" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.665 -113.278 clk " " -3.665 -113.278 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810559 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.445 " "Worst-case hold slack is 0.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.445 0.000 clk " " 0.445 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810567 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810572 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810581 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -43.179 clk " " -1.631 -43.179 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810585 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588514810659 ""}
{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588514810663 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1588514810680 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.854 " "Worst-case setup slack is -0.854" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.854 -24.594 clk " " -0.854 -24.594 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810684 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " " 0.215 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810690 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810696 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588514810704 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -35.380 clk " " -1.380 -35.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1588514810710 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588514810765 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588514810798 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588514810799 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4545 " "Peak virtual memory: 4545 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588514810889 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 22:06:50 2020 " "Processing ended: Sun May 03 22:06:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588514810889 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1605758739833 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1605758739834 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 19 12:05:39 2020 " "Processing started: Thu Nov 19 12:05:39 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1605758739834 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1605758739834 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder " "Command: quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1605758739834 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1605758739978 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1605758740238 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1605758740274 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1605758740274 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_7SegmentDecoder.sdc " "Synopsys Design Constraints File file not found: 'YL_7SegmentDecoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1605758740411 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1605758740412 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740414 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740414 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1605758740420 ""}
{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1605758740439 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1605758740445 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.665 " "Worst-case setup slack is -3.665" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.665 -113.278 clk " " -3.665 -113.278 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1605758740447 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.445 " "Worst-case hold slack is 0.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.445 0.000 clk " " 0.445 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740450 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1605758740450 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1605758740453 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1605758740455 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740458 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740458 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -43.179 clk " " -1.631 -43.179 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740458 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1605758740458 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1605758740490 ""}
{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1605758740492 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1605758740507 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.854 " "Worst-case setup slack is -0.854" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.854 -24.594 clk " " -0.854 -24.594 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740510 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1605758740510 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " " 0.215 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740514 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1605758740514 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1605758740521 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1605758740525 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -35.380 clk " " -1.380 -35.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1605758740528 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1605758740528 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1605758740571 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1605758740592 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1605758740592 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4546 " "Peak virtual memory: 4546 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1605758740676 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 19 12:05:40 2020 " "Processing ended: Thu Nov 19 12:05:40 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1605758740676 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1605758740676 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1605758740676 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1605758740676 ""}

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Exp28_Decoder/db/YL_7SegmentDecoder.sta_cmp.7_slow.tdb
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Exp28_Decoder/db/YL_7SegmentDecoder.tmw_info
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@ -0,0 +1,7 @@
start_full_compilation:s
start_analysis_synthesis:s-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s-start_full_compilation
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation
start_eda_netlist_writer:s-start_full_compilation

119
Exp28_Decoder/db/prev_cmp_YL_7SegmentDecoder.qmsg
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Exp28_Decoder/incremental_db/compiled_partitions/YL_7SegmentDecoder.root_partition.cmp.cdb
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Exp28_Decoder/output_files/YL_7SegmentDecoder.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for YL_7SegmentDecoder
Sun May 03 22:06:48 2020
Thu Nov 19 12:05:38 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -10,8 +10,8 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.sof
6. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.pof
5. Assembler Device Options: C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.sof
6. Assembler Device Options: C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.pof
7. Assembler Messages
@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun May 03 22:06:48 2020 ;
; Assembler Status ; Successful - Thu Nov 19 12:05:38 2020 ;
; Revision Name ; YL_7SegmentDecoder ;
; Top-level Entity Name ; YL_7SegmentDecoder ;
; Family ; Cyclone II ;
@ -78,37 +78,37 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+----------+---------------+
+---------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------------------------------------+
; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.sof ;
; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.pof ;
+---------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------------------+
; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.sof ;
; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.pof ;
+---------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.sof ;
+----------------+------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------------------------------------+
; Device ; EP2C20F484C7 ;
; JTAG usercode ; 0x001BB8F7 ;
; Checksum ; 0x001BB8F7 ;
+----------------+------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.sof ;
+----------------+------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------------------+
; Device ; EP2C20F484C7 ;
; JTAG usercode ; 0x001BB8F7 ;
; Checksum ; 0x001BB8F7 ;
+----------------+------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.pof ;
+--------------------+--------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+--------------------------------------------------------------------------------------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1DD818A9 ;
; Compression Ratio ; 3 ;
+--------------------+--------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.pof ;
+--------------------+--------------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+--------------------------------------------------------------------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1DD818A9 ;
; Compression Ratio ; 3 ;
+--------------------+--------------------------------------------------------------------------------+
+--------------------+
@ -117,13 +117,13 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun May 03 22:06:46 2020
Info: Processing started: Thu Nov 19 12:05:36 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4552 megabytes
Info: Processing ended: Sun May 03 22:06:48 2020
Info: Processing ended: Thu Nov 19 12:05:38 2020
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

2
Exp28_Decoder/output_files/YL_7SegmentDecoder.done
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@ -1 +1 @@
Mon May 04 09:33:14 2020
Thu Nov 19 12:05:43 2020

30
Exp28_Decoder/output_files/YL_7SegmentDecoder.eda.rpt
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@ -1,5 +1,5 @@
EDA Netlist Writer report for YL_7SegmentDecoder
Sun May 03 22:06:52 2020
Thu Nov 19 12:05:43 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sun May 03 22:06:52 2020 ;
; EDA Netlist Writer Status ; Successful - Thu Nov 19 12:05:43 2020 ;
; Revision Name ; YL_7SegmentDecoder ;
; Top-level Entity Name ; YL_7SegmentDecoder ;
; Family ; Cyclone II ;
@ -66,16 +66,16 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+-----------------------------------------------------------------------------------------------------------+
; Generated Files ;
+-----------------------------------------------------------------------------------------------------------+
; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder.vo ;
; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_fast.vo ;
; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v.sdo ;
; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v_fast.sdo ;
+-----------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+-----------------------------------------------------------------------------------------+
; Generated Files ;
+-----------------------------------------------------------------------------------------+
; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder.vo ;
; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_fast.vo ;
; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v.sdo ;
; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v_fast.sdo ;
+-----------------------------------------------------------------------------------------+
+-----------------------------+
@ -84,12 +84,12 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun May 03 22:06:51 2020
Info: Processing started: Thu Nov 19 12:05:42 2020
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder
Info (204026): Generated files "YL_7SegmentDecoder.vo", "YL_7SegmentDecoder_fast.vo", "YL_7SegmentDecoder_v.sdo" and "YL_7SegmentDecoder_v_fast.sdo" in directory "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/simulation/modelsim/" for EDA simulation tool
Info (204026): Generated files "YL_7SegmentDecoder.vo", "YL_7SegmentDecoder_fast.vo", "YL_7SegmentDecoder_v.sdo" and "YL_7SegmentDecoder_v_fast.sdo" in directory "C:/opt/git/ELEC211_FPGA/Exp28_Decoder/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4529 megabytes
Info: Processing ended: Sun May 03 22:06:52 2020
Info: Processing ended: Thu Nov 19 12:05:43 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

28
Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.rpt
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@ -1,5 +1,5 @@
Fitter report for YL_7SegmentDecoder
Sun May 03 22:06:45 2020
Thu Nov 19 12:05:34 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -63,7 +63,7 @@ applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Sun May 03 22:06:45 2020 ;
; Fitter Status ; Successful - Thu Nov 19 12:05:34 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; YL_7SegmentDecoder ;
; Top-level Entity Name ; YL_7SegmentDecoder ;
@ -191,7 +191,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.pin.
The pin-out file can be found in C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.pin.
+---------------------------------------------------------------------+
@ -1314,19 +1314,19 @@ Info (176215): I/O bank details before I/O pin placement
Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available
Warning (15705): Ignored locations or region assignments to the following nodes
Warning (15706): Node "enc" is assigned to location or region, but does not exist in design
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y14 to location X11_Y27
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (11888): Total time spent on timing analysis during the Fitter is 0.30 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.11 seconds.
Info (306004): Started post-fitting delay annotation
Warning (306006): Found 14 output pins without output pin load capacitance assignment
Info (306007): Pin "OUTPUT_A" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
@ -1346,20 +1346,20 @@ Warning (306006): Found 14 output pins without output pin load capacitance assig
Info (306005): Delay annotation completed successfully
Info (306004): Started post-fitting delay annotation
Info (306005): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.smsg
Info (144001): Generated suppressed messages file C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 9 warnings
Info: Peak virtual memory: 4840 megabytes
Info: Processing ended: Sun May 03 22:06:45 2020
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:06
Info: Peak virtual memory: 4850 megabytes
Info: Processing ended: Thu Nov 19 12:05:34 2020
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:05
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.smsg.
The suppressed messages can be found in C:/opt/git/ELEC211_FPGA/Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.smsg.

2
Exp28_Decoder/output_files/YL_7SegmentDecoder.fit.summary
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@ -1,4 +1,4 @@
Fitter Status : Successful - Sun May 03 22:06:45 2020
Fitter Status : Successful - Thu Nov 19 12:05:34 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : YL_7SegmentDecoder
Top-level Entity Name : YL_7SegmentDecoder

26
Exp28_Decoder/output_files/YL_7SegmentDecoder.flow.rpt
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@ -1,5 +1,5 @@
Flow report for YL_7SegmentDecoder
Sun May 03 22:06:52 2020
Thu Nov 19 12:05:43 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,7 +40,7 @@ applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Sun May 03 22:06:52 2020 ;
; Flow Status ; Successful - Thu Nov 19 12:05:43 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; YL_7SegmentDecoder ;
; Top-level Entity Name ; YL_7SegmentDecoder ;
@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 05/03/2020 22:06:36 ;
; Start date & time ; 11/19/2020 12:05:24 ;
; Main task ; Compilation ;
; Revision Name ; YL_7SegmentDecoder ;
+-------------------+---------------------+
@ -75,7 +75,7 @@ applicable agreement for further details.
+-------------------------------------+------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 345052807169.158851479611888 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 345052807169.160575872416600 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
@ -93,12 +93,12 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4597 MB ; 00:00:02 ;
; Fitter ; 00:00:07 ; 1.0 ; 4840 MB ; 00:00:06 ;
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4597 MB ; 00:00:01 ;
; Fitter ; 00:00:08 ; 1.0 ; 4850 MB ; 00:00:05 ;
; Assembler ; 00:00:02 ; 1.0 ; 4552 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4545 MB ; 00:00:01 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4546 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4518 MB ; 00:00:01 ;
; Total ; 00:00:13 ; -- ; -- ; 00:00:12 ;
; Total ; 00:00:14 ; -- ; -- ; 00:00:10 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
@ -107,11 +107,11 @@ applicable agreement for further details.
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; Yimian-PC ; Windows 7 ; 6.2 ; x86_64 ;
; Analysis & Synthesis ; Ushio ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; Ushio ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; Ushio ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; Ushio ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; Ushio ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+

28
Exp28_Decoder/output_files/YL_7SegmentDecoder.map.rpt
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Analysis & Synthesis report for YL_7SegmentDecoder
Sun May 03 22:06:37 2020
Thu Nov 19 12:05:25 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -41,7 +41,7 @@ applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun May 03 22:06:37 2020 ;
; Analysis & Synthesis Status ; Successful - Thu Nov 19 12:05:25 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; YL_7SegmentDecoder ;
; Top-level Entity Name ; YL_7SegmentDecoder ;
@ -154,16 +154,16 @@ Parallel compilation was disabled, but you have multiple processors available. E
+----------------------------+--------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+---------+
; YL_dec_counter.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_dec_counter.tdf ; ;
; YL_7SegmentDecoder.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf ; ;
; YL_7SegmentDecoder.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.tdf ; ;
; YL_sec_cnt.tdf ; yes ; User AHDL File ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_sec_cnt.tdf ; ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------+---------+
; YL_dec_counter.tdf ; yes ; User AHDL File ; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_dec_counter.tdf ; ;
; YL_7SegmentDecoder.bdf ; yes ; User Block Diagram/Schematic File ; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf ; ;
; YL_7SegmentDecoder.tdf ; yes ; User AHDL File ; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.tdf ; ;
; YL_sec_cnt.tdf ; yes ; User AHDL File ; C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_sec_cnt.tdf ; ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------+---------+
+-----------------------------------------------------+
@ -241,7 +241,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun May 03 22:06:35 2020
Info: Processing started: Thu Nov 19 12:05:23 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_7SegmentDecoder -c YL_7SegmentDecoder
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file yl_dec_counter.tdf
@ -269,7 +269,7 @@ Info (21057): Implemented 88 device resources after synthesis - the final resour
Info (21061): Implemented 71 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4608 megabytes
Info: Processing ended: Sun May 03 22:06:37 2020
Info: Processing ended: Thu Nov 19 12:05:25 2020
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

2
Exp28_Decoder/output_files/YL_7SegmentDecoder.map.summary
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Analysis & Synthesis Status : Successful - Sun May 03 22:06:37 2020
Analysis & Synthesis Status : Successful - Thu Nov 19 12:05:25 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : YL_7SegmentDecoder
Top-level Entity Name : YL_7SegmentDecoder

BIN
Exp28_Decoder/output_files/YL_7SegmentDecoder.sof
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Binary file not shown.

8
Exp28_Decoder/output_files/YL_7SegmentDecoder.sta.rpt
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TimeQuest Timing Analyzer report for YL_7SegmentDecoder
Sun May 03 22:06:50 2020
Thu Nov 19 12:05:40 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -1093,7 +1093,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun May 03 22:06:49 2020
Info: Processing started: Thu Nov 19 12:05:39 2020
Info: Command: quartus_sta YL_7SegmentDecoder -c YL_7SegmentDecoder
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
@ -1141,8 +1141,8 @@ Info (332001): The selected device family is not supported by the report_metasta
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 4545 megabytes
Info: Processing ended: Sun May 03 22:06:50 2020
Info: Peak virtual memory: 4546 megabytes
Info: Processing ended: Thu Nov 19 12:05:40 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

2
Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder.vo
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// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// DATE "05/03/2020 22:06:52"
// DATE "11/19/2020 12:05:43"
//
// Device: Altera EP2C20F484C7 Package FBGA484

2
Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_fast.vo
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// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// DATE "05/03/2020 22:06:52"
// DATE "11/19/2020 12:05:43"
//
// Device: Altera EP2C20F484C7 Package FBGA484

22
Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_modelsim.xrf
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@ -1,15 +1,15 @@
vendor_name = ModelSim
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_dec_counter.tdf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.bdf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.tdf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder.vwf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder2.bdf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder2.vwf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_sec_cnt.tdf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_7SegmentDecoder3.vwf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_Cascade.bdf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/YL_cascade.vwf
source_file = 1, C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28_Decoder/db/YL_7SegmentDecoder.cbx.xml
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_dec_counter.tdf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.bdf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.tdf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder.vwf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder2.bdf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder2.vwf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_sec_cnt.tdf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_7SegmentDecoder3.vwf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_Cascade.bdf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/YL_cascade.vwf
source_file = 1, C:/opt/git/ELEC211_FPGA/Exp28_Decoder/db/YL_7SegmentDecoder.cbx.xml
design_name = YL_7SegmentDecoder
instance = comp, \inst10|count[2] , inst10|count[2], YL_7SegmentDecoder, 1
instance = comp, \inst10|count[5] , inst10|count[5], YL_7SegmentDecoder, 1

2
Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v.sdo
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@ -24,7 +24,7 @@
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "YL_7SegmentDecoder")
(DATE "05/03/2020 22:06:52")
(DATE "11/19/2020 12:05:43")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition")

2
Exp28_Decoder/simulation/modelsim/YL_7SegmentDecoder_v_fast.sdo
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@ -24,7 +24,7 @@
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "YL_7SegmentDecoder")
(DATE "05/03/2020 22:06:52")
(DATE "11/19/2020 12:05:43")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition")

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