archieved

4 years ago · 8962599cde
commit 8962599cde
742 changed files with 64927 additions and 0 deletions
--- a/Exp28/YL_7448.vwf
+++ b/Exp28/YL_7448.vwf
@ -0,0 +1,367 @@
+/* Simulator = Quartus II Simulator */
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("INPUT_A")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_B")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_C")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_D")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_A")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_B")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_C")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_D")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_E")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_F")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_G")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("INPUT_A")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 10;
+			LEVEL 0 FOR 50.0;
+			LEVEL 1 FOR 50.0;
+		}
+	}
+}
+
+TRANSITION_LIST("INPUT_B")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 5;
+			LEVEL 0 FOR 100.0;
+			LEVEL 1 FOR 100.0;
+		}
+	}
+}
+
+TRANSITION_LIST("INPUT_C")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 2;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+		}
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("INPUT_D")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 400.0;
+		LEVEL 1 FOR 400.0;
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_A")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_B")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_C")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_D")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_E")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_F")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_G")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_A";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_B";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_C";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_D";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_A";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_B";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_C";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_D";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_E";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_F";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_G";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 0;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
--- a/Exp28/YL_7448.vwf.temp
+++ b/Exp28/YL_7448.vwf.temp
@ -0,0 +1,367 @@
+/* Simulator = Quartus II Simulator */
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("INPUT_A")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_B")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_C")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_D")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_A")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_B")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_C")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_D")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_E")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_F")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_G")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("INPUT_A")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 10;
+			LEVEL 0 FOR 50.0;
+			LEVEL 1 FOR 50.0;
+		}
+	}
+}
+
+TRANSITION_LIST("INPUT_B")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 5;
+			LEVEL 0 FOR 100.0;
+			LEVEL 1 FOR 100.0;
+		}
+	}
+}
+
+TRANSITION_LIST("INPUT_C")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 2;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+		}
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("INPUT_D")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 400.0;
+		LEVEL 1 FOR 400.0;
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_A")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_B")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_C")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_D")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_E")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_F")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_G")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_A";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_B";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_C";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_D";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_A";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_B";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_C";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_D";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_E";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_F";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_G";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 0;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
--- a/Exp28/YL_dec7748.bdf
+++ b/Exp28/YL_dec7748.bdf
@ -0,0 +1,403 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 320 240 488 256)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT_A" (rect 5 0 52 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 256 488 272)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT_B" (rect 5 0 51 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 272 488 288)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT_C" (rect 5 0 52 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 288 488 304)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT_D" (rect 5 0 52 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 776 240 952 256)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT_A" (rect 90 0 147 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 776 256 952 272)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT_B" (rect 90 0 146 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 776 272 952 288)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT_C" (rect 90 0 147 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 776 288 952 304)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT_D" (rect 90 0 147 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 776 304 952 320)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT_E" (rect 90 0 146 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 776 320 952 336)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT_F" (rect 90 0 146 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 776 336 952 352)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT_G" (rect 90 0 147 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(symbol
+	(rect 584 224 704 384)
+	(text "7448" (rect 45 0 78 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 3 149 18 159)(font "Arial" (font_size 6)))
+	(port
+		(pt 0 24)
+		(input)
+		(text "A" (rect 21 17 30 31)(font "Arial" (font_size 8)))
+		(text "A" (rect 21 17 30 31)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 16 24))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "C" (rect 21 49 29 63)(font "Arial" (font_size 8)))
+		(text "C" (rect 21 49 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "D" (rect 21 65 29 79)(font "Arial" (font_size 8)))
+		(text "D" (rect 21 65 29 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "B" (rect 21 33 29 47)(font "Arial" (font_size 8)))
+		(text "B" (rect 21 33 29 47)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "RBIN" (rect 21 97 48 111)(font "Arial" (font_size 8)))
+		(text "RBIN" (rect 21 97 48 111)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 8 104))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "BIN" (rect 21 113 39 127)(font "Arial" (font_size 8)))
+		(text "BIN" (rect 21 113 39 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 8 120))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "LTN" (rect 21 81 43 95)(font "Arial" (font_size 8)))
+		(text "LTN" (rect 21 81 43 95)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 8 88))
+	)
+	(port
+		(pt 120 56)
+		(output)
+		(text "OC" (rect 83 48 100 62)(font "Arial" (font_size 8)))
+		(text "OC" (rect 85 48 102 62)(font "Arial" (font_size 8)))
+		(line (pt 104 56)(pt 120 56))
+	)
+	(port
+		(pt 120 88)
+		(output)
+		(text "OE" (rect 83 80 99 94)(font "Arial" (font_size 8)))
+		(text "OE" (rect 86 80 102 94)(font "Arial" (font_size 8)))
+		(line (pt 104 88)(pt 120 88))
+	)
+	(port
+		(pt 120 72)
+		(output)
+		(text "OD" (rect 83 64 100 78)(font "Arial" (font_size 8)))
+		(text "OD" (rect 85 64 102 78)(font "Arial" (font_size 8)))
+		(line (pt 104 72)(pt 120 72))
+	)
+	(port
+		(pt 120 104)
+		(output)
+		(text "OF" (rect 83 96 99 110)(font "Arial" (font_size 8)))
+		(text "OF" (rect 86 96 102 110)(font "Arial" (font_size 8)))
+		(line (pt 104 104)(pt 120 104))
+	)
+	(port
+		(pt 120 120)
+		(output)
+		(text "OG" (rect 83 112 101 126)(font "Arial" (font_size 8)))
+		(text "OG" (rect 84 112 102 126)(font "Arial" (font_size 8)))
+		(line (pt 104 120)(pt 120 120))
+	)
+	(port
+		(pt 120 40)
+		(output)
+		(text "OB" (rect 83 32 100 46)(font "Arial" (font_size 8)))
+		(text "OB" (rect 85 32 102 46)(font "Arial" (font_size 8)))
+		(line (pt 104 40)(pt 120 40))
+	)
+	(port
+		(pt 120 24)
+		(output)
+		(text "OA" (rect 83 16 101 30)(font "Arial" (font_size 8)))
+		(text "OA" (rect 84 16 102 30)(font "Arial" (font_size 8)))
+		(line (pt 104 24)(pt 120 24))
+	)
+	(port
+		(pt 120 136)
+		(output)
+		(text "RBON" (rect 67 128 101 142)(font "Arial" (font_size 8)))
+		(text "RBON" (rect 79 128 113 142)(font "Arial" (font_size 8)))
+		(line (pt 112 136)(pt 120 136))
+	)
+	(drawing
+		(text "BCD TO 7SEG" (rect 29 145 109 159)(font "Arial" (font_size 8)))
+		(line (pt 16 16)(pt 104 16))
+		(line (pt 16 144)(pt 104 144))
+		(line (pt 104 144)(pt 104 16))
+		(line (pt 16 144)(pt 16 16))
+		(circle (rect 104 132 112 140))
+		(circle (rect 8 116 16 124))
+		(circle (rect 8 100 16 108))
+		(circle (rect 8 84 16 92))
+	)
+)
+(symbol
+	(rect 520 176 552 192)
+	(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
+	(text "inst1" (rect 3 5 26 17)(font "Arial" )(invisible))
+	(port
+		(pt 16 16)
+		(output)
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(line (pt 16 16)(pt 16 8))
+	)
+	(drawing
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(connector
+	(pt 488 264)
+	(pt 584 264)
+)
+(connector
+	(pt 584 280)
+	(pt 488 280)
+)
+(connector
+	(pt 584 248)
+	(pt 488 248)
+)
+(connector
+	(pt 704 264)
+	(pt 776 264)
+)
+(connector
+	(pt 704 280)
+	(pt 776 280)
+)
+(connector
+	(pt 776 296)
+	(pt 704 296)
+)
+(connector
+	(pt 704 312)
+	(pt 776 312)
+)
+(connector
+	(pt 776 328)
+	(pt 704 328)
+)
+(connector
+	(pt 704 344)
+	(pt 776 344)
+)
+(connector
+	(pt 584 296)
+	(pt 488 296)
+)
+(connector
+	(pt 704 248)
+	(pt 776 248)
+)
+(connector
+	(pt 536 344)
+	(pt 584 344)
+)
+(connector
+	(pt 584 312)
+	(pt 536 312)
+)
+(connector
+	(pt 536 192)
+	(pt 536 312)
+)
+(connector
+	(pt 584 328)
+	(pt 536 328)
+)
+(connector
+	(pt 536 312)
+	(pt 536 328)
+)
+(connector
+	(pt 536 328)
+	(pt 536 344)
+)
+(junction (pt 536 312))
+(junction (pt 536 328))
--- a/Exp28/YL_dec7748.qpf
+++ b/Exp28/YL_dec7748.qpf
@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 15:51:11  May 03, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "15:51:11  May 03, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "YL_dec7748"
--- a/Exp28/YL_dec7748.qsf
+++ b/Exp28/YL_dec7748.qsf
@ -0,0 +1,60 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 15:51:11  May 03, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		YL_dec7748_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY YL_dec7748
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:51:11  MAY 03, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name BDF_FILE YL_dec7748.bdf
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE YL_7448.vwf
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf"
--- a/Exp28/YL_dec7748.qws
+++ b/Exp28/YL_dec7748.qws
--- a/Exp28/db/YL_dec7748.(0).cnf.cdb
+++ b/Exp28/db/YL_dec7748.(0).cnf.cdb
--- a/Exp28/db/YL_dec7748.(0).cnf.hdb
+++ b/Exp28/db/YL_dec7748.(0).cnf.hdb
--- a/Exp28/db/YL_dec7748.(1).cnf.cdb
+++ b/Exp28/db/YL_dec7748.(1).cnf.cdb
--- a/Exp28/db/YL_dec7748.(1).cnf.hdb
+++ b/Exp28/db/YL_dec7748.(1).cnf.hdb
--- a/Exp28/db/YL_dec7748.asm.qmsg
+++ b/Exp28/db/YL_dec7748.asm.qmsg
@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588496425161 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588496425161 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 17:00:24 2020 " "Processing started: Sun May 03 17:00:24 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588496425161 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1588496425161 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1588496425162 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1588496426649 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1588496426722 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4558 " "Peak virtual memory: 4558 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588496427593 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 17:00:27 2020 " "Processing ended: Sun May 03 17:00:27 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588496427593 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588496427593 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588496427593 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1588496427593 ""}
--- a/Exp28/db/YL_dec7748.asm.rdb
+++ b/Exp28/db/YL_dec7748.asm.rdb
--- a/Exp28/db/YL_dec7748.asm_labs.ddb
+++ b/Exp28/db/YL_dec7748.asm_labs.ddb
--- a/Exp28/db/YL_dec7748.cbx.xml
+++ b/Exp28/db/YL_dec7748.cbx.xml
@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="YL_dec7748">
+	</PROJECT>
+</LOG_ROOT>
--- a/Exp28/db/YL_dec7748.cmp.bpm
+++ b/Exp28/db/YL_dec7748.cmp.bpm
--- a/Exp28/db/YL_dec7748.cmp.cdb
+++ b/Exp28/db/YL_dec7748.cmp.cdb
--- a/Exp28/db/YL_dec7748.cmp.hdb
+++ b/Exp28/db/YL_dec7748.cmp.hdb
--- a/Exp28/db/YL_dec7748.cmp.idb
+++ b/Exp28/db/YL_dec7748.cmp.idb
--- a/Exp28/db/YL_dec7748.cmp.kpt
+++ b/Exp28/db/YL_dec7748.cmp.kpt
--- a/Exp28/db/YL_dec7748.cmp.logdb
+++ b/Exp28/db/YL_dec7748.cmp.logdb
@ -0,0 +1 @@
+v1
--- a/Exp28/db/YL_dec7748.cmp.rdb
+++ b/Exp28/db/YL_dec7748.cmp.rdb
--- a/Exp28/db/YL_dec7748.cmp0.ddb
+++ b/Exp28/db/YL_dec7748.cmp0.ddb
--- a/Exp28/db/YL_dec7748.cmp1.ddb
+++ b/Exp28/db/YL_dec7748.cmp1.ddb
--- a/Exp28/db/YL_dec7748.cmp2.ddb
+++ b/Exp28/db/YL_dec7748.cmp2.ddb
--- a/Exp28/db/YL_dec7748.cmp_merge.kpt
+++ b/Exp28/db/YL_dec7748.cmp_merge.kpt
--- a/Exp28/db/YL_dec7748.db_info
+++ b/Exp28/db/YL_dec7748.db_info
@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Sun May 03 16:24:22 2020
--- a/Exp28/db/YL_dec7748.eds_overflow
+++ b/Exp28/db/YL_dec7748.eds_overflow
@ -0,0 +1 @@
+34
--- a/Exp28/db/YL_dec7748.fit.qmsg
+++ b/Exp28/db/YL_dec7748.fit.qmsg
--- a/Exp28/db/YL_dec7748.hier_info
+++ b/Exp28/db/YL_dec7748.hier_info
@ -0,0 +1,36 @@
+|YL_dec7748
+OUTPUT_A <= 7448:inst.OA
+INPUT_A => 7448:inst.A
+INPUT_C => 7448:inst.C
+INPUT_D => 7448:inst.D
+INPUT_B => 7448:inst.B
+OUTPUT_B <= 7448:inst.OB
+OUTPUT_C <= 7448:inst.OC
+OUTPUT_D <= 7448:inst.OD
+OUTPUT_E <= 7448:inst.OE
+OUTPUT_F <= 7448:inst.OF
+OUTPUT_G <= 7448:inst.OG
+
+
+|YL_dec7748|7448:inst
+OA <= 69.DB_MAX_OUTPUT_PORT_TYPE
+B => 27.IN0
+LTN => 27.IN1
+LTN => 25.IN1
+LTN => 29.IN1
+LTN => 13.IN5
+LTN => 38.IN3
+BIN => 37.IN0
+C => 25.IN0
+D => 14.IN0
+A => 29.IN0
+RBIN => 15.IN0
+OB <= 68.DB_MAX_OUTPUT_PORT_TYPE
+OC <= 70.DB_MAX_OUTPUT_PORT_TYPE
+OD <= 67.DB_MAX_OUTPUT_PORT_TYPE
+RBON <= 13.DB_MAX_OUTPUT_PORT_TYPE
+OE <= 71.DB_MAX_OUTPUT_PORT_TYPE
+OF <= 66.DB_MAX_OUTPUT_PORT_TYPE
+OG <= 72.DB_MAX_OUTPUT_PORT_TYPE
+
+
--- a/Exp28/db/YL_dec7748.hif
+++ b/Exp28/db/YL_dec7748.hif
--- a/Exp28/db/YL_dec7748.ipinfo
+++ b/Exp28/db/YL_dec7748.ipinfo
--- a/Exp28/db/YL_dec7748.lpc.html
+++ b/Exp28/db/YL_dec7748.lpc.html
@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
--- a/Exp28/db/YL_dec7748.lpc.rdb
+++ b/Exp28/db/YL_dec7748.lpc.rdb
--- a/Exp28/db/YL_dec7748.lpc.txt
+++ b/Exp28/db/YL_dec7748.lpc.txt
@ -0,0 +1,5 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
--- a/Exp28/db/YL_dec7748.map.ammdb
+++ b/Exp28/db/YL_dec7748.map.ammdb
--- a/Exp28/db/YL_dec7748.map.bpm
+++ b/Exp28/db/YL_dec7748.map.bpm
--- a/Exp28/db/YL_dec7748.map.cdb
+++ b/Exp28/db/YL_dec7748.map.cdb
--- a/Exp28/db/YL_dec7748.map.hdb
+++ b/Exp28/db/YL_dec7748.map.hdb
--- a/Exp28/db/YL_dec7748.map.kpt
+++ b/Exp28/db/YL_dec7748.map.kpt
--- a/Exp28/db/YL_dec7748.map.logdb
+++ b/Exp28/db/YL_dec7748.map.logdb
@ -0,0 +1 @@
+v1
--- a/Exp28/db/YL_dec7748.map.qmsg
+++ b/Exp28/db/YL_dec7748.map.qmsg
@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588496414068 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588496414069 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 17:00:13 2020 " "Processing started: Sun May 03 17:00:13 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588496414069 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588496414069 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off YL_dec7748 -c YL_dec7748 " "Command: quartus_map --read_settings_files=on --write_settings_files=off YL_dec7748 -c YL_dec7748" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588496414069 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588496414685 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yl_dec7748.bdf 1 1 " "Found 1 design units, including 1 entities, in source file yl_dec7748.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 YL_dec7748 " "Found entity 1: YL_dec7748" {  } { { "YL_dec7748.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_dec7748.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1588496414771 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1588496414771 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "YL_dec7748 " "Elaborating entity \"YL_dec7748\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1588496414828 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7448 7448:inst " "Elaborating entity \"7448\" for hierarchy \"7448:inst\"" {  } { { "YL_dec7748.bdf" "inst" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_dec7748.bdf" { { 224 584 704 384 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1588496414857 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "7448:inst " "Elaborated megafunction instantiation \"7448:inst\"" {  } { { "YL_dec7748.bdf" "" { Schematic "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_dec7748.bdf" { { 224 584 704 384 "inst" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588496414860 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1588496415604 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588496415604 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1588496415686 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1588496415686 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1588496415686 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1588496415686 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4604 " "Peak virtual memory: 4604 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588496415738 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 17:00:15 2020 " "Processing ended: Sun May 03 17:00:15 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588496415738 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588496415738 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588496415738 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588496415738 ""}
--- a/Exp28/db/YL_dec7748.map.rdb
+++ b/Exp28/db/YL_dec7748.map.rdb
--- a/Exp28/db/YL_dec7748.map_bb.cdb
+++ b/Exp28/db/YL_dec7748.map_bb.cdb
--- a/Exp28/db/YL_dec7748.map_bb.hdb
+++ b/Exp28/db/YL_dec7748.map_bb.hdb
--- a/Exp28/db/YL_dec7748.map_bb.logdb
+++ b/Exp28/db/YL_dec7748.map_bb.logdb
@ -0,0 +1 @@
+v1
--- a/Exp28/db/YL_dec7748.pre_map.hdb
+++ b/Exp28/db/YL_dec7748.pre_map.hdb
--- a/Exp28/db/YL_dec7748.pti_db_list.ddb
+++ b/Exp28/db/YL_dec7748.pti_db_list.ddb
--- a/Exp28/db/YL_dec7748.root_partition.map.reg_db.cdb
+++ b/Exp28/db/YL_dec7748.root_partition.map.reg_db.cdb
--- a/Exp28/db/YL_dec7748.routing.rdb
+++ b/Exp28/db/YL_dec7748.routing.rdb
--- a/Exp28/db/YL_dec7748.rtlv.hdb
+++ b/Exp28/db/YL_dec7748.rtlv.hdb
--- a/Exp28/db/YL_dec7748.rtlv_sg.cdb
+++ b/Exp28/db/YL_dec7748.rtlv_sg.cdb
--- a/Exp28/db/YL_dec7748.rtlv_sg_swap.cdb
+++ b/Exp28/db/YL_dec7748.rtlv_sg_swap.cdb
--- a/Exp28/db/YL_dec7748.sgdiff.cdb
+++ b/Exp28/db/YL_dec7748.sgdiff.cdb
--- a/Exp28/db/YL_dec7748.sgdiff.hdb
+++ b/Exp28/db/YL_dec7748.sgdiff.hdb
--- a/Exp28/db/YL_dec7748.sim.hdb
+++ b/Exp28/db/YL_dec7748.sim.hdb
--- a/Exp28/db/YL_dec7748.sim.qmsg
+++ b/Exp28/db/YL_dec7748.sim.qmsg
@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588496462869 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II 64-Bit " "Running Quartus II 64-Bit Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588496462870 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 17:01:02 2020 " "Processing started: Sun May 03 17:01:02 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588496462870 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588496462870 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --simulation_results_format=VWF YL_dec7748 -c YL_dec7748 " "Command: quartus_sim --simulation_results_format=VWF YL_dec7748 -c YL_dec7748" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588496462870 ""}
+{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf " "Using vector source file \"C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf\"" {  } {  } 0 324025 "Using vector source file \"%1!s!\"" 0 0 "Quartus II" 0 -1 1588496463297 ""}
+{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 310004 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "Quartus II" 0 -1 1588496463394 ""}  } {  } 0 310003 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "Quartus II" 0 -1 1588496463394 ""}
+{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Simulation partitioned into 1 sub-simulations" {  } {  } 0 310002 "Simulation partitioned into %1!d! sub-simulations" 0 0 "Quartus II" 0 -1 1588496463396 ""}
+{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "    100.00 % " "Simulation coverage is     100.00 %" {  } {  } 0 328053 "Simulation coverage is %1!s!" 0 0 "Quartus II" 0 -1 1588496463398 ""}
+{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "224 " "Number of transitions in simulation is 224" {  } {  } 0 328052 "Number of transitions in simulation is %1!s!" 0 0 "Quartus II" 0 -1 1588496463398 ""}
+{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "YL_dec7748.sim.vwf " "Vector file YL_dec7748.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 324045 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0 "Quartus II" 0 -1 1588496463400 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4484 " "Peak virtual memory: 4484 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588496463461 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 17:01:03 2020 " "Processing ended: Sun May 03 17:01:03 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588496463461 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588496463461 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588496463461 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588496463461 ""}
--- a/Exp28/db/YL_dec7748.sim.rdb
+++ b/Exp28/db/YL_dec7748.sim.rdb
--- a/Exp28/db/YL_dec7748.sim.vwf
+++ b/Exp28/db/YL_dec7748.sim.vwf
@ -0,0 +1,437 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 1000.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("INPUT_A")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_B")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_C")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("INPUT_D")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_A")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_B")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_C")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_D")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_E")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_F")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("OUTPUT_G")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("INPUT_A")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 10;
+			LEVEL 0 FOR 50.0;
+			LEVEL 1 FOR 50.0;
+		}
+	}
+}
+
+TRANSITION_LIST("INPUT_B")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 5;
+			LEVEL 0 FOR 100.0;
+			LEVEL 1 FOR 100.0;
+		}
+	}
+}
+
+TRANSITION_LIST("INPUT_C")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 2;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+		}
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("INPUT_D")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 400.0;
+		LEVEL 1 FOR 400.0;
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_A")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 63.26;
+		LEVEL 0 FOR 49.803;
+		LEVEL 1 FOR 100.069;
+		LEVEL 0 FOR 50.128;
+		LEVEL 1 FOR 50.0;
+		LEVEL 0 FOR 50.0;
+		LEVEL 1 FOR 49.29;
+		LEVEL 0 FOR 0.582;
+		LEVEL 1 FOR 99.931;
+		LEVEL 0 FOR 150.197;
+		LEVEL 1 FOR 49.803;
+		LEVEL 0 FOR 99.487;
+		LEVEL 1 FOR 50.71;
+		LEVEL 0 FOR 49.803;
+		LEVEL 1 FOR 86.937;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_B")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 261.167;
+		LEVEL 0 FOR 100.0;
+		LEVEL 1 FOR 49.3;
+		LEVEL 0 FOR 0.7;
+		LEVEL 1 FOR 99.794;
+		LEVEL 0 FOR 100.0;
+		LEVEL 1 FOR 50.206;
+		LEVEL 0 FOR 149.3;
+		LEVEL 1 FOR 189.533;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_C")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 111.414;
+		LEVEL 0 FOR 50.0;
+		LEVEL 1 FOR 249.297;
+		LEVEL 0 FOR 0.582;
+		LEVEL 1 FOR 100.121;
+		LEVEL 0 FOR 50.0;
+		LEVEL 1 FOR 49.879;
+		LEVEL 0 FOR 199.418;
+		LEVEL 1 FOR 100.703;
+		LEVEL 0 FOR 50.0;
+		LEVEL 1 FOR 38.586;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_D")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 61.576;
+		NODE
+		{
+			REPEAT = 2;
+			LEVEL 0 FOR 49.765;
+			LEVEL 1 FOR 100.114;
+			LEVEL 0 FOR 50.121;
+			LEVEL 1 FOR 100.0;
+			LEVEL 0 FOR 49.879;
+			LEVEL 1 FOR 50.121;
+		}
+		LEVEL 0 FOR 49.765;
+		LEVEL 1 FOR 88.659;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_E")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 61.915;
+		NODE
+		{
+			REPEAT = 2;
+			LEVEL 0 FOR 50.0;
+			LEVEL 1 FOR 50.0;
+			LEVEL 0 FOR 150.0;
+			LEVEL 1 FOR 50.0;
+			LEVEL 0 FOR 49.923;
+			LEVEL 1 FOR 50.077;
+		}
+		LEVEL 0 FOR 50.0;
+		LEVEL 1 FOR 50.0;
+		LEVEL 0 FOR 38.085;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_F")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 61.165;
+		LEVEL 0 FOR 150.0;
+		LEVEL 1 FOR 150.0;
+		LEVEL 0 FOR 49.802;
+		LEVEL 1 FOR 100.0;
+		LEVEL 0 FOR 100.0;
+		LEVEL 1 FOR 150.198;
+		LEVEL 0 FOR 49.802;
+		LEVEL 1 FOR 50.198;
+		LEVEL 0 FOR 138.835;
+	}
+}
+
+TRANSITION_LIST("OUTPUT_G")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 110.907;
+		LEVEL 1 FOR 250.227;
+		LEVEL 0 FOR 49.773;
+		LEVEL 1 FOR 350.227;
+		LEVEL 0 FOR 149.773;
+		LEVEL 1 FOR 89.093;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_A";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_B";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_C";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "INPUT_D";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_A";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_B";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_C";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_D";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_E";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_F";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "OUTPUT_G";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 0;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
--- a/Exp28/db/YL_dec7748.sld_design_entry.sci
+++ b/Exp28/db/YL_dec7748.sld_design_entry.sci
--- a/Exp28/db/YL_dec7748.sld_design_entry_dsc.sci
+++ b/Exp28/db/YL_dec7748.sld_design_entry_dsc.sci
--- a/Exp28/db/YL_dec7748.smart_action.txt
+++ b/Exp28/db/YL_dec7748.smart_action.txt
@ -0,0 +1 @@
+DONE
--- a/Exp28/db/YL_dec7748.sta.qmsg
+++ b/Exp28/db/YL_dec7748.sta.qmsg
@ -0,0 +1,34 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588496429018 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 17:00:28 2020 " "Processing started: Sun May 03 17:00:28 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_dec7748 -c YL_dec7748 " "Command: quartus_sta YL_dec7748 -c YL_dec7748" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588496429021 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588496429176 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1588496429471 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588496429510 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1588496429510 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "YL_dec7748.sdc " "Synopsys Design Constraints File file not found: 'YL_dec7748.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1588496429605 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588496429606 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1588496429606 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1588496429607 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1588496429609 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1588496429623 ""}
+{ "Info" "0" "" "Analyzing Slow Model" {  } {  } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1588496429626 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429627 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429653 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429656 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429661 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429666 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429668 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588496429680 ""}
+{ "Info" "0" "" "Analyzing Fast Model" {  } {  } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1588496429682 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1588496429695 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1588496429695 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1588496429698 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429702 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429704 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429708 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429711 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1588496429716 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1588496429726 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588496429761 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1588496429761 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4541 " "Peak virtual memory: 4541 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1588496429837 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 03 17:00:29 2020 " "Processing ended: Sun May 03 17:00:29 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1588496429837 ""}
--- a/Exp28/db/YL_dec7748.sta.rdb
+++ b/Exp28/db/YL_dec7748.sta.rdb
--- a/Exp28/db/YL_dec7748.sta_cmp.7_slow.tdb
+++ b/Exp28/db/YL_dec7748.sta_cmp.7_slow.tdb
--- a/Exp28/db/YL_dec7748.syn_hier_info
+++ b/Exp28/db/YL_dec7748.syn_hier_info
--- a/Exp28/db/YL_dec7748.tis_db_list.ddb
+++ b/Exp28/db/YL_dec7748.tis_db_list.ddb
--- a/Exp28/db/YL_dec7748.vpr.ammdb
+++ b/Exp28/db/YL_dec7748.vpr.ammdb
--- a/Exp28/db/logic_util_heursitic.dat
+++ b/Exp28/db/logic_util_heursitic.dat
--- a/Exp28/db/prev_cmp_YL_dec7748.qmsg
+++ b/Exp28/db/prev_cmp_YL_dec7748.qmsg
@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1588496390484 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1588496390485 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 03 16:59:49 2020 " "Processing started: Sun May 03 16:59:49 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1588496390485 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1588496390485 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta YL_dec7748 -c YL_dec7748 " "Command: quartus_sta YL_dec7748 -c YL_dec7748" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1588496390485 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1588496390718 ""}
+{ "Error" "0" "" "Can't run TimeQuest Timing Analyzer (quartus_sta) -- Fitter (quartus_fit) failed or was not run. Run the Fitter (quartus_fit) successfully before running the TimeQuest analyzer (create_timing_netlist)." {  } {  } 0 0 "Can't run TimeQuest Timing Analyzer (quartus_sta) -- Fitter (quartus_fit) failed or was not run. Run the Fitter (quartus_fit) successfully before running the TimeQuest analyzer (create_timing_netlist)." 0 0 "Quartus II" 0 0 1588496390735 ""}
--- a/Exp28/incremental_db/README
+++ b/Exp28/incremental_db/README
@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.db_info
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.db_info
@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Sun May 03 16:24:35 2020
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.ammdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.ammdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.cdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.cdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.dfp
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.dfp
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.hdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.hdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.kpt
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.kpt
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.logdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.logdb
@ -0,0 +1 @@
+v1
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.rcfdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.cmp.rcfdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.cdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.cdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.dpi
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.dpi
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.cdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.cdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.hb_info
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.hb_info
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.hdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.hdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.sig
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hbdb.sig
@ -0,0 +1 @@
+9a9b3e9d06db00b9dc03feca87af856c
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hdb
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.hdb
--- a/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.kpt
+++ b/Exp28/incremental_db/compiled_partitions/YL_dec7748.root_partition.map.kpt
--- a/Exp28/output_files/YL_dec7748.asm.rpt
+++ b/Exp28/output_files/YL_dec7748.asm.rpt
@ -0,0 +1,130 @@
+Assembler report for YL_dec7748
+Sun May 03 17:00:27 2020
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.sof
+  6. Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
+---------------------------------------------------------------+
+; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Sun May 03 17:00:27 2020 ;
+; Revision Name         ; YL_dec7748                            ;
+; Top-level Entity Name ; YL_dec7748                            ;
+; Family                ; Cyclone II                            ;
+; Device                ; EP2C20F484C7                          ;
+-----------------------+---------------------------------------+
+
+
+--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
+-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Maintain Compatibility with All Cyclone II M4K Versions                     ; On       ; On            ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
+-----------------------------------------------------------------------------+----------+---------------+
+
+
+-----------------------------------------------------------------------------+
+; Assembler Generated Files                                                   ;
+-----------------------------------------------------------------------------+
+; File Name                                                                   ;
+-----------------------------------------------------------------------------+
+; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.sof ;
+; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.pof ;
+-----------------------------------------------------------------------------+
+
+
+-------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.sof ;
+----------------+--------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                              ;
+----------------+--------------------------------------------------------------------------------------+
+; Device         ; EP2C20F484C7                                                                         ;
+; JTAG usercode  ; 0x001B207A                                                                           ;
+; Checksum       ; 0x001B207A                                                                           ;
+----------------+--------------------------------------------------------------------------------------+
+
+
+-------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/output_files/YL_dec7748.pof ;
+--------------------+----------------------------------------------------------------------------------+
+; Option             ; Setting                                                                          ;
+--------------------+----------------------------------------------------------------------------------+
+; Device             ; EPCS16                                                                           ;
+; JTAG usercode      ; 0x00000000                                                                       ;
+; Checksum           ; 0x1DD9CD2A                                                                       ;
+; Compression Ratio  ; 3                                                                                ;
+--------------------+----------------------------------------------------------------------------------+
+
+
+--------------------+
+; Assembler Messages ;
+--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Sun May 03 17:00:24 2020
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 4558 megabytes
+    Info: Processing ended: Sun May 03 17:00:27 2020
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:02
+
+
--- a/Exp28/output_files/YL_dec7748.done
+++ b/Exp28/output_files/YL_dec7748.done
@ -0,0 +1 @@
+Sun May 03 17:00:30 2020
--- a/Exp28/output_files/YL_dec7748.fit.rpt
+++ b/Exp28/output_files/YL_dec7748.fit.rpt
--- a/Exp28/output_files/YL_dec7748.fit.smsg
+++ b/Exp28/output_files/YL_dec7748.fit.smsg
@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
--- a/Exp28/output_files/YL_dec7748.fit.summary
+++ b/Exp28/output_files/YL_dec7748.fit.summary
@ -0,0 +1,16 @@
+Fitter Status : Successful - Sun May 03 17:00:23 2020
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : YL_dec7748
+Top-level Entity Name : YL_dec7748
+Family : Cyclone II
+Device : EP2C20F484C7
+Timing Models : Final
+Total logic elements : 7 / 18,752 ( < 1 % )
+    Total combinational functions : 7 / 18,752 ( < 1 % )
+    Dedicated logic registers : 0 / 18,752 ( 0 % )
+Total registers : 0
+Total pins : 11 / 315 ( 3 % )
+Total virtual pins : 0
+Total memory bits : 0 / 239,616 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
--- a/Exp28/output_files/YL_dec7748.flow.rpt
+++ b/Exp28/output_files/YL_dec7748.flow.rpt
@ -0,0 +1,122 @@
+Flow report for YL_dec7748
+Sun May 03 17:00:29 2020
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
+--------------------------------------------------------------------------------------+
+; Flow Summary                                                                         ;
+------------------------------------+-------------------------------------------------+
+; Flow Status                        ; Successful - Sun May 03 17:00:27 2020           ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name                      ; YL_dec7748                                      ;
+; Top-level Entity Name              ; YL_dec7748                                      ;
+; Family                             ; Cyclone II                                      ;
+; Device                             ; EP2C20F484C7                                    ;
+; Timing Models                      ; Final                                           ;
+; Total logic elements               ; 7 / 18,752 ( < 1 % )                            ;
+;     Total combinational functions  ; 7 / 18,752 ( < 1 % )                            ;
+;     Dedicated logic registers      ; 0 / 18,752 ( 0 % )                              ;
+; Total registers                    ; 0                                               ;
+; Total pins                         ; 11 / 315 ( 3 % )                                ;
+; Total virtual pins                 ; 0                                               ;
+; Total memory bits                  ; 0 / 239,616 ( 0 % )                             ;
+; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                   ;
+------------------------------------+-------------------------------------------------+
+
+
+-----------------------------------------+
+; Flow Settings                           ;
+-------------------+---------------------+
+; Option            ; Setting             ;
+-------------------+---------------------+
+; Start date & time ; 05/03/2020 17:00:14 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; YL_dec7748          ;
+-------------------+---------------------+
+
+
+---------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                              ;
+-------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                        ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 345052807169.158849641411336 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                            ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                     ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING        ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                       ; --            ; --          ; Top        ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                 ; --            ; --          ; --         ;
+-------------------------------------+------------------------------+---------------+-------------+------------+
+
+
+-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 4593 MB             ; 00:00:01                           ;
+; Fitter                    ; 00:00:07     ; 1.0                     ; 4848 MB             ; 00:00:06                           ;
+; Assembler                 ; 00:00:03     ; 1.0                     ; 4558 MB             ; 00:00:02                           ;
+; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 4541 MB             ; 00:00:01                           ;
+; Total                     ; 00:00:13     ; --                      ; --                  ; 00:00:10                           ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
+----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
+---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; Yimian-PC        ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; Yimian-PC        ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; Yimian-PC        ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; Yimian-PC        ; Windows 7 ; 6.2        ; x86_64         ;
+---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off YL_dec7748 -c YL_dec7748
+quartus_fit --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748
+quartus_asm --read_settings_files=off --write_settings_files=off YL_dec7748 -c YL_dec7748
+quartus_sta YL_dec7748 -c YL_dec7748
+
+
+
--- a/Exp28/output_files/YL_dec7748.jdi
+++ b/Exp28/output_files/YL_dec7748.jdi
@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="3a4068e6522c6cf42c2b"/>
+  </project>
+  <file_info>
+    <file device="EP2C20F484C7" path="YL_dec7748.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
--- a/Exp28/output_files/YL_dec7748.map.rpt
+++ b/Exp28/output_files/YL_dec7748.map.rpt
@ -0,0 +1,258 @@
+Analysis & Synthesis report for YL_dec7748
+Sun May 03 17:00:15 2020
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
+--------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                         ;
+------------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Sun May 03 17:00:15 2020           ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name                      ; YL_dec7748                                      ;
+; Top-level Entity Name              ; YL_dec7748                                      ;
+; Family                             ; Cyclone II                                      ;
+; Total logic elements               ; 7                                               ;
+;     Total combinational functions  ; 7                                               ;
+;     Dedicated logic registers      ; 0                                               ;
+; Total registers                    ; 0                                               ;
+; Total pins                         ; 11                                              ;
+; Total virtual pins                 ; 0                                               ;
+; Total memory bits                  ; 0                                               ;
+; Embedded Multiplier 9-bit elements ; 0                                               ;
+; Total PLLs                         ; 0                                               ;
+------------------------------------+-------------------------------------------------+
+
+
+----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP2C20F484C7       ;                    ;
+; Top-level entity name                                                      ; YL_dec7748         ; YL_dec7748         ;
+; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
+; Parallel Compilation                ;
+----------------------------+--------+
+; Processors                 ; Number ;
+----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
+----------------------------+--------+
+
+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                             ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                   ; Library ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+
+; YL_dec7748.bdf                   ; yes             ; User Block Diagram/Schematic File  ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_dec7748.bdf ;         ;
+; 7448.bdf                         ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/others/maxplus2/7448.bdf   ;         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+
+
+
+-------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
+; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
+; Estimated Total logic elements              ; 7       ;
+;                                             ;         ;
+; Total combinational functions               ; 7       ;
+; Logic element usage by number of LUT inputs ;         ;
+;     -- 4 input functions                    ; 5       ;
+;     -- 3 input functions                    ; 2       ;
+;     -- <=2 input functions                  ; 0       ;
+;                                             ;         ;
+; Logic elements by mode                      ;         ;
+;     -- normal mode                          ; 7       ;
+;     -- arithmetic mode                      ; 0       ;
+;                                             ;         ;
+; Total registers                             ; 0       ;
+;     -- Dedicated logic registers            ; 0       ;
+;     -- I/O registers                        ; 0       ;
+;                                             ;         ;
+; I/O pins                                    ; 11      ;
+; Embedded Multiplier 9-bit elements          ; 0       ;
+; Maximum fan-out node                        ; INPUT_B ;
+; Maximum fan-out                             ; 7       ;
+; Total fan-out                               ; 33      ;
+; Average fan-out                             ; 1.83    ;
+---------------------------------------------+---------+
+
+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name   ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+
+; |YL_dec7748                ; 7 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 11   ; 0            ; |YL_dec7748           ; work         ;
+;    |7448:inst|             ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |YL_dec7748|7448:inst ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+------------------------------------------------------+
+; General Register Statistics                          ;
+----------------------------------------------+-------+
+; Statistic                                    ; Value ;
+----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+
+
+
+-------------------------------+
+; Elapsed Time Per Partition    ;
+----------------+--------------+
+; Partition Name ; Elapsed Time ;
+----------------+--------------+
+; Top            ; 00:00:00     ;
+----------------+--------------+
+
+
+-------------------------------+
+; Analysis & Synthesis Messages ;
+-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Sun May 03 17:00:13 2020
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off YL_dec7748 -c YL_dec7748
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file yl_dec7748.bdf
+    Info (12023): Found entity 1: YL_dec7748
+Info (12127): Elaborating entity "YL_dec7748" for the top level hierarchy
+Info (12128): Elaborating entity "7448" for hierarchy "7448:inst"
+Info (12130): Elaborated megafunction instantiation "7448:inst"
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 4 input pins
+    Info (21059): Implemented 7 output pins
+    Info (21061): Implemented 7 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4604 megabytes
+    Info: Processing ended: Sun May 03 17:00:15 2020
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
--- a/Exp28/output_files/YL_dec7748.map.summary
+++ b/Exp28/output_files/YL_dec7748.map.summary
@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Sun May 03 17:00:15 2020
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : YL_dec7748
+Top-level Entity Name : YL_dec7748
+Family : Cyclone II
+Total logic elements : 7
+    Total combinational functions : 7
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 11
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
--- a/Exp28/output_files/YL_dec7748.pin
+++ b/Exp28/output_files/YL_dec7748.pin
@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		3.3V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+CHIP  "YL_dec7748"  ASSIGNED TO AN: EP2C20F484C7
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO3                       : A2        : power  :                   : 3.3V    : 3         :                
+GND*                         : A3        :        :                   :         : 3         :                
+GND*                         : A4        :        :                   :         : 3         :                
+GND*                         : A5        :        :                   :         : 3         :                
+GND*                         : A6        :        :                   :         : 3         :                
+GND*                         : A7        :        :                   :         : 3         :                
+GND*                         : A8        :        :                   :         : 3         :                
+GND*                         : A9        :        :                   :         : 3         :                
+GND*                         : A10       :        :                   :         : 3         :                
+GND*                         : A11       :        :                   :         : 3         :                
+GND+                         : A12       :        :                   :         : 4         :                
+GND*                         : A13       :        :                   :         : 4         :                
+GND*                         : A14       :        :                   :         : 4         :                
+GND*                         : A15       :        :                   :         : 4         :                
+GND*                         : A16       :        :                   :         : 4         :                
+GND*                         : A17       :        :                   :         : 4         :                
+GND*                         : A18       :        :                   :         : 4         :                
+GND*                         : A19       :        :                   :         : 4         :                
+GND*                         : A20       :        :                   :         : 4         :                
+VCCIO4                       : A21       : power  :                   : 3.3V    : 4         :                
+GND                          : A22       : gnd    :                   :         :           :                
+VCCIO1                       : AA1       : power  :                   : 3.3V    : 1         :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND*                         : AA3       :        :                   :         : 8         :                
+GND*                         : AA4       :        :                   :         : 8         :                
+GND*                         : AA5       :        :                   :         : 8         :                
+GND*                         : AA6       :        :                   :         : 8         :                
+GND*                         : AA7       :        :                   :         : 8         :                
+GND*                         : AA8       :        :                   :         : 8         :                
+GND*                         : AA9       :        :                   :         : 8         :                
+INPUT_B                      : AA10      : input  : 3.3-V LVTTL       :         : 8         : N              
+OUTPUT_D                     : AA11      : output : 3.3-V LVTTL       :         : 8         : N              
+GND*                         : AA12      :        :                   :         : 7         :                
+OUTPUT_B                     : AA13      : output : 3.3-V LVTTL       :         : 7         : N              
+GND*                         : AA14      :        :                   :         : 7         :                
+GND*                         : AA15      :        :                   :         : 7         :                
+GND*                         : AA16      :        :                   :         : 7         :                
+GND*                         : AA17      :        :                   :         : 7         :                
+GND*                         : AA18      :        :                   :         : 7         :                
+GND*                         : AA19      :        :                   :         : 7         :                
+GND*                         : AA20      :        :                   :         : 7         :                
+GND                          : AA21      : gnd    :                   :         :           :                
+VCCIO6                       : AA22      : power  :                   : 3.3V    : 6         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO8                       : AB2       : power  :                   : 3.3V    : 8         :                
+GND*                         : AB3       :        :                   :         : 8         :                
+GND*                         : AB4       :        :                   :         : 8         :                
+GND*                         : AB5       :        :                   :         : 8         :                
+GND*                         : AB6       :        :                   :         : 8         :                
+GND*                         : AB7       :        :                   :         : 8         :                
+GND*                         : AB8       :        :                   :         : 8         :                
+GND*                         : AB9       :        :                   :         : 8         :                
+GND*                         : AB10      :        :                   :         : 8         :                
+GND*                         : AB11      :        :                   :         : 8         :                
+OUTPUT_F                     : AB12      : output : 3.3-V LVTTL       :         : 7         : N              
+INPUT_D                      : AB13      : input  : 3.3-V LVTTL       :         : 7         : N              
+GND*                         : AB14      :        :                   :         : 7         :                
+GND*                         : AB15      :        :                   :         : 7         :                
+GND*                         : AB16      :        :                   :         : 7         :                
+GND*                         : AB17      :        :                   :         : 7         :                
+GND*                         : AB18      :        :                   :         : 7         :                
+GND*                         : AB19      :        :                   :         : 7         :                
+GND*                         : AB20      :        :                   :         : 7         :                
+VCCIO7                       : AB21      : power  :                   : 3.3V    : 7         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+VCCIO2                       : B1        : power  :                   : 3.3V    : 2         :                
+GND                          : B2        : gnd    :                   :         :           :                
+GND*                         : B3        :        :                   :         : 3         :                
+GND*                         : B4        :        :                   :         : 3         :                
+GND*                         : B5        :        :                   :         : 3         :                
+GND*                         : B6        :        :                   :         : 3         :                
+GND*                         : B7        :        :                   :         : 3         :                
+GND*                         : B8        :        :                   :         : 3         :                
+GND*                         : B9        :        :                   :         : 3         :                
+GND*                         : B10       :        :                   :         : 3         :                
+GND*                         : B11       :        :                   :         : 3         :                
+GND+                         : B12       :        :                   :         : 4         :                
+GND*                         : B13       :        :                   :         : 4         :                
+OUTPUT_A                     : B14       : output : 3.3-V LVTTL       :         : 4         : N              
+GND*                         : B15       :        :                   :         : 4         :                
+GND*                         : B16       :        :                   :         : 4         :                
+GND*                         : B17       :        :                   :         : 4         :                
+GND*                         : B18       :        :                   :         : 4         :                
+GND*                         : B19       :        :                   :         : 4         :                
+GND*                         : B20       :        :                   :         : 4         :                
+GND                          : B21       : gnd    :                   :         :           :                
+VCCIO5                       : B22       : power  :                   : 3.3V    : 5         :                
+GND*                         : C1        :        :                   :         : 2         :                
+GND*                         : C2        :        :                   :         : 2         :                
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3        : input  : 3.3-V LVTTL       :         : 2         : N              
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4        : input  : 3.3-V LVTTL       :         : 2         : N              
+GND                          : C5        : gnd    :                   :         :           :                
+VCCIO3                       : C6        : power  :                   : 3.3V    : 3         :                
+GND*                         : C7        :        :                   :         : 3         :                
+GND                          : C8        : gnd    :                   :         :           :                
+GND*                         : C9        :        :                   :         : 3         :                
+GND*                         : C10       :        :                   :         : 3         :                
+VCCIO3                       : C11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : C12       : power  :                   : 3.3V    : 4         :                
+GND*                         : C13       :        :                   :         : 4         :                
+GND*                         : C14       :        :                   :         : 4         :                
+GND                          : C15       : gnd    :                   :         :           :                
+GND*                         : C16       :        :                   :         : 4         :                
+GND*                         : C17       :        :                   :         : 4         :                
+GND*                         : C18       :        :                   :         : 4         :                
+GND*                         : C19       :        :                   :         : 5         :                
+GND*                         : C20       :        :                   :         : 5         :                
+GND*                         : C21       :        :                   :         : 5         :                
+GND*                         : C22       :        :                   :         : 5         :                
+GND*                         : D1        :        :                   :         : 2         :                
+GND*                         : D2        :        :                   :         : 2         :                
+GND*                         : D3        :        :                   :         : 2         :                
+GND*                         : D4        :        :                   :         : 2         :                
+GND*                         : D5        :        :                   :         : 2         :                
+GND*                         : D6        :        :                   :         : 2         :                
+GND*                         : D7        :        :                   :         : 3         :                
+GND*                         : D8        :        :                   :         : 3         :                
+GND*                         : D9        :        :                   :         : 3         :                
+GND                          : D10       : gnd    :                   :         :           :                
+GND*                         : D11       :        :                   :         : 3         :                
+GND+                         : D12       :        :                   :         : 3         :                
+GND                          : D13       : gnd    :                   :         :           :                
+GND*                         : D14       :        :                   :         : 4         :                
+GND*                         : D15       :        :                   :         : 4         :                
+GND*                         : D16       :        :                   :         : 4         :                
+VCCIO4                       : D17       : power  :                   : 3.3V    : 4         :                
+GND                          : D18       : gnd    :                   :         :           :                
+GND*                         : D19       :        :                   :         : 5         :                
+GND*                         : D20       :        :                   :         : 5         :                
+GND*                         : D21       :        :                   :         : 5         :                
+GND*                         : D22       :        :                   :         : 5         :                
+GND*                         : E1        :        :                   :         : 2         :                
+GND*                         : E2        :        :                   :         : 2         :                
+GND*                         : E3        :        :                   :         : 2         :                
+GND*                         : E4        :        :                   :         : 2         :                
+VCCD_PLL3                    : E5        : power  :                   : 1.2V    :           :                
+VCCA_PLL3                    : E6        : power  :                   : 1.2V    :           :                
+GND*                         : E7        :        :                   :         : 3         :                
+GND*                         : E8        :        :                   :         : 3         :                
+GND*                         : E9        :        :                   :         : 3         :                
+VCCIO3                       : E10       : power  :                   : 3.3V    : 3         :                
+GND*                         : E11       :        :                   :         : 3         :                
+GND+                         : E12       :        :                   :         : 3         :                
+VCCIO4                       : E13       : power  :                   : 3.3V    : 4         :                
+GND*                         : E14       :        :                   :         : 4         :                
+GND*                         : E15       :        :                   :         : 4         :                
+GNDA_PLL2                    : E16       : gnd    :                   :         :           :                
+GND_PLL2                     : E17       : gnd    :                   :         :           :                
+GND*                         : E18       :        :                   :         : 5         :                
+GND*                         : E19       :        :                   :         : 5         :                
+GND*                         : E20       :        :                   :         : 5         :                
+GND*                         : E21       :        :                   :         : 5         :                
+GND*                         : E22       :        :                   :         : 5         :                
+GND*                         : F1        :        :                   :         : 2         :                
+GND*                         : F2        :        :                   :         : 2         :                
+GND*                         : F3        :        :                   :         : 2         :                
+GND*                         : F4        :        :                   :         : 2         :                
+GND_PLL3                     : F5        : gnd    :                   :         :           :                
+GND_PLL3                     : F6        : gnd    :                   :         :           :                
+GNDA_PLL3                    : F7        : gnd    :                   :         :           :                
+GND*                         : F8        :        :                   :         : 3         :                
+GND*                         : F9        :        :                   :         : 3         :                
+GND*                         : F10       :        :                   :         : 3         :                
+GND*                         : F11       :        :                   :         : 3         :                
+INPUT_C                      : F12       : input  : 3.3-V LVTTL       :         : 4         : N              
+GND*                         : F13       :        :                   :         : 4         :                
+GND*                         : F14       :        :                   :         : 4         :                
+GND*                         : F15       :        :                   :         : 4         :                
+VCCA_PLL2                    : F16       : power  :                   : 1.2V    :           :                
+VCCD_PLL2                    : F17       : power  :                   : 1.2V    :           :                
+GND_PLL2                     : F18       : gnd    :                   :         :           :                
+GND                          : F19       : gnd    :                   :         :           :                
+GND*                         : F20       :        :                   :         : 5         :                
+GND*                         : F21       :        :                   :         : 5         :                
+GND*                         : F22       :        :                   :         : 5         :                
+NC                           : G1        :        :                   :         :           :                
+NC                           : G2        :        :                   :         :           :                
+GND*                         : G3        :        :                   :         : 2         :                
+GND                          : G4        : gnd    :                   :         :           :                
+GND*                         : G5        :        :                   :         : 2         :                
+GND*                         : G6        :        :                   :         : 2         :                
+GND*                         : G7        :        :                   :         : 3         :                
+GND*                         : G8        :        :                   :         : 3         :                
+VCCIO3                       : G9        : power  :                   : 3.3V    : 3         :                
+GND                          : G10       : gnd    :                   :         :           :                
+GND*                         : G11       :        :                   :         : 3         :                
+GND*                         : G12       :        :                   :         : 4         :                
+GND                          : G13       : gnd    :                   :         :           :                
+VCCIO4                       : G14       : power  :                   : 3.3V    : 4         :                
+GND*                         : G15       :        :                   :         : 4         :                
+GND*                         : G16       :        :                   :         : 4         :                
+GND*                         : G17       :        :                   :         : 5         :                
+GND*                         : G18       :        :                   :         : 5         :                
+VCCIO5                       : G19       : power  :                   : 3.3V    : 5         :                
+GND*                         : G20       :        :                   :         : 5         :                
+GND*                         : G21       :        :                   :         : 5         :                
+GND*                         : G22       :        :                   :         : 5         :                
+GND*                         : H1        :        :                   :         : 2         :                
+GND*                         : H2        :        :                   :         : 2         :                
+GND*                         : H3        :        :                   :         : 2         :                
+GND*                         : H4        :        :                   :         : 2         :                
+GND*                         : H5        :        :                   :         : 2         :                
+GND*                         : H6        :        :                   :         : 2         :                
+GND*                         : H7        :        :                   :         : 3         :                
+GND*                         : H8        :        :                   :         : 3         :                
+GND*                         : H9        :        :                   :         : 3         :                
+GND*                         : H10       :        :                   :         : 3         :                
+GND*                         : H11       :        :                   :         : 3         :                
+INPUT_A                      : H12       : input  : 3.3-V LVTTL       :         : 4         : N              
+GND*                         : H13       :        :                   :         : 4         :                
+GND*                         : H14       :        :                   :         : 4         :                
+GND*                         : H15       :        :                   :         : 4         :                
+GND*                         : H16       :        :                   :         : 5         :                
+GND*                         : H17       :        :                   :         : 5         :                
+GND*                         : H18       :        :                   :         : 5         :                
+GND*                         : H19       :        :                   :         : 5         :                
+GND                          : H20       : gnd    :                   :         :           :                
+NC                           : H21       :        :                   :         :           :                
+NC                           : H22       :        :                   :         :           :                
+GND*                         : J1        :        :                   :         : 2         :                
+GND*                         : J2        :        :                   :         : 2         :                
+NC                           : J3        :        :                   :         :           :                
+GND*                         : J4        :        :                   :         : 2         :                
+NC                           : J5        :        :                   :         :           :                
+NC                           : J6        :        :                   :         :           :                
+VCCIO2                       : J7        : power  :                   : 3.3V    : 2         :                
+NC                           : J8        :        :                   :         :           :                
+NC                           : J9        :        :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+GND*                         : J14       :        :                   :         : 4         :                
+GND*                         : J15       :        :                   :         : 5         :                
+VCCIO5                       : J16       : power  :                   : 3.3V    : 5         :                
+GND*                         : J17       :        :                   :         : 5         :                
+GND*                         : J18       :        :                   :         : 5         :                
+GND*                         : J19       :        :                   :         : 5         :                
+GND*                         : J20       :        :                   :         : 5         :                
+GND*                         : J21       :        :                   :         : 5         :                
+GND*                         : J22       :        :                   :         : 5         :                
+nCE                          : K1        :        :                   :         : 2         :                
+TCK                          : K2        : input  :                   :         : 2         :                
+GND                          : K3        : gnd    :                   :         :           :                
+DATA0                        : K4        : input  :                   :         : 2         :                
+TDI                          : K5        : input  :                   :         : 2         :                
+TMS                          : K6        : input  :                   :         : 2         :                
+GND                          : K7        : gnd    :                   :         :           :                
+NC                           : K8        :        :                   :         :           :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+NC                           : K15       :        :                   :         :           :                
+GND                          : K16       : gnd    :                   :         :           :                
+NC                           : K17       :        :                   :         :           :                
+NC                           : K18       :        :                   :         :           :                
+GND                          : K19       : gnd    :                   :         :           :                
+GND*                         : K20       :        :                   :         : 5         :                
+GND*                         : K21       :        :                   :         : 5         :                
+GND*                         : K22       :        :                   :         : 5         :                
+GND+                         : L1        :        :                   :         : 2         :                
+GND+                         : L2        :        :                   :         : 2         :                
+VCCIO2                       : L3        : power  :                   : 3.3V    : 2         :                
+nCONFIG                      : L4        :        :                   :         : 2         :                
+TDO                          : L5        : output :                   :         : 2         :                
+DCLK                         : L6        :        :                   :         : 2         :                
+NC                           : L7        :        :                   :         :           :                
+GND*                         : L8        :        :                   :         : 2         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+NC                           : L15       :        :                   :         :           :                
+NC                           : L16       :        :                   :         :           :                
+NC                           : L17       :        :                   :         :           :                
+GND*                         : L18       :        :                   :         : 5         :                
+GND*                         : L19       :        :                   :         : 5         :                
+VCCIO5                       : L20       : power  :                   : 3.3V    : 5         :                
+GND+                         : L21       :        :                   :         : 5         :                
+GND+                         : L22       :        :                   :         : 5         :                
+GND+                         : M1        :        :                   :         : 1         :                
+GND+                         : M2        :        :                   :         : 1         :                
+VCCIO1                       : M3        : power  :                   : 3.3V    : 1         :                
+GND                          : M4        : gnd    :                   :         :           :                
+GND*                         : M5        :        :                   :         : 1         :                
+GND*                         : M6        :        :                   :         : 1         :                
+NC                           : M7        :        :                   :         :           :                
+NC                           : M8        :        :                   :         :           :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+NC                           : M15       :        :                   :         :           :                
+NC                           : M16       :        :                   :         :           :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+GND*                         : M18       :        :                   :         : 6         :                
+GND*                         : M19       :        :                   :         : 6         :                
+VCCIO6                       : M20       : power  :                   : 3.3V    : 6         :                
+GND+                         : M21       :        :                   :         : 6         :                
+GND+                         : M22       :        :                   :         : 6         :                
+GND*                         : N1        :        :                   :         : 1         :                
+GND*                         : N2        :        :                   :         : 1         :                
+GND*                         : N3        :        :                   :         : 1         :                
+GND*                         : N4        :        :                   :         : 1         :                
+NC                           : N5        :        :                   :         :           :                
+GND*                         : N6        :        :                   :         : 1         :                
+GND                          : N7        : gnd    :                   :         :           :                
+NC                           : N8        :        :                   :         :           :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCCINT                       : N14       : power  :                   : 1.2V    :           :                
+GND*                         : N15       :        :                   :         : 6         :                
+GND                          : N16       : gnd    :                   :         :           :                
+MSEL1                        : N17       :        :                   :         : 6         :                
+CONF_DONE                    : N18       :        :                   :         : 6         :                
+GND                          : N19       : gnd    :                   :         :           :                
+nSTATUS                      : N20       :        :                   :         : 6         :                
+GND*                         : N21       :        :                   :         : 6         :                
+GND*                         : N22       :        :                   :         : 6         :                
+GND*                         : P1        :        :                   :         : 1         :                
+GND*                         : P2        :        :                   :         : 1         :                
+GND*                         : P3        :        :                   :         : 1         :                
+NC                           : P4        :        :                   :         :           :                
+GND*                         : P5        :        :                   :         : 1         :                
+GND*                         : P6        :        :                   :         : 1         :                
+VCCIO1                       : P7        : power  :                   : 3.3V    : 1         :                
+GND*                         : P8        :        :                   :         : 8         :                
+GND*                         : P9        :        :                   :         : 8         :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+NC                           : P14       :        :                   :         :           :                
+GND*                         : P15       :        :                   :         : 6         :                
+VCCIO6                       : P16       : power  :                   : 3.3V    : 6         :                
+GND*                         : P17       :        :                   :         : 6         :                
+GND*                         : P18       :        :                   :         : 6         :                
+NC                           : P19       :        :                   :         :           :                
+NC                           : P20       :        :                   :         :           :                
+NC                           : P21       :        :                   :         :           :                
+NC                           : P22       :        :                   :         :           :                
+GND*                         : R1        :        :                   :         : 1         :                
+GND*                         : R2        :        :                   :         : 1         :                
+GND                          : R3        : gnd    :                   :         :           :                
+NC                           : R4        :        :                   :         :           :                
+GND*                         : R5        :        :                   :         : 1         :                
+GND*                         : R6        :        :                   :         : 1         :                
+GND*                         : R7        :        :                   :         : 1         :                
+GND*                         : R8        :        :                   :         : 1         :                
+GND*                         : R9        :        :                   :         : 8         :                
+GND*                         : R10       :        :                   :         : 8         :                
+OUTPUT_E                     : R11       : output : 3.3-V LVTTL       :         : 8         : N              
+GND*                         : R12       :        :                   :         : 7         :                
+GND*                         : R13       :        :                   :         : 7         :                
+GND*                         : R14       :        :                   :         : 7         :                
+GND*                         : R15       :        :                   :         : 7         :                
+GND*                         : R16       :        :                   :         : 7         :                
+GND*                         : R17       :        :                   :         : 6         :                
+GND*                         : R18       :        :                   :         : 6         :                
+GND*                         : R19       :        :                   :         : 6         :                
+GND*                         : R20       :        :                   :         : 6         :                
+GND*                         : R21       :        :                   :         : 6         :                
+GND*                         : R22       :        :                   :         : 6         :                
+GND*                         : T1        :        :                   :         : 1         :                
+GND*                         : T2        :        :                   :         : 1         :                
+GND*                         : T3        :        :                   :         : 1         :                
+VCCIO1                       : T4        : power  :                   : 3.3V    : 1         :                
+GND*                         : T5        :        :                   :         : 1         :                
+GND*                         : T6        :        :                   :         : 1         :                
+GND*                         : T7        :        :                   :         : 8         :                
+GND*                         : T8        :        :                   :         : 8         :                
+VCCIO8                       : T9        : power  :                   : 3.3V    : 8         :                
+GND                          : T10       : gnd    :                   :         :           :                
+GND*                         : T11       :        :                   :         : 8         :                
+OUTPUT_G                     : T12       : output : 3.3-V LVTTL       :         : 7         : N              
+GND                          : T13       : gnd    :                   :         :           :                
+VCCIO7                       : T14       : power  :                   : 3.3V    : 7         :                
+GND*                         : T15       :        :                   :         : 7         :                
+GND*                         : T16       :        :                   :         : 7         :                
+GND_PLL4                     : T17       : gnd    :                   :         :           :                
+GND*                         : T18       :        :                   :         : 6         :                
+VCCIO6                       : T19       : power  :                   : 3.3V    : 6         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND*                         : T21       :        :                   :         : 6         :                
+GND*                         : T22       :        :                   :         : 6         :                
+GND*                         : U1        :        :                   :         : 1         :                
+GND*                         : U2        :        :                   :         : 1         :                
+GND*                         : U3        :        :                   :         : 1         :                
+GND*                         : U4        :        :                   :         : 1         :                
+GND_PLL1                     : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+VCCA_PLL1                    : U7        : power  :                   : 1.2V    :           :                
+GND*                         : U8        :        :                   :         : 8         :                
+GND*                         : U9        :        :                   :         : 8         :                
+GND*                         : U10       :        :                   :         : 8         :                
+GND+                         : U11       :        :                   :         : 8         :                
+GND+                         : U12       :        :                   :         : 8         :                
+GND*                         : U13       :        :                   :         : 7         :                
+GND*                         : U14       :        :                   :         : 7         :                
+GND*                         : U15       :        :                   :         : 7         :                
+VCCA_PLL4                    : U16       : power  :                   : 1.2V    :           :                
+VCCD_PLL4                    : U17       : power  :                   : 1.2V    :           :                
+GND*                         : U18       :        :                   :         : 6         :                
+GND*                         : U19       :        :                   :         : 6         :                
+GND*                         : U20       :        :                   :         : 6         :                
+GND*                         : U21       :        :                   :         : 6         :                
+GND*                         : U22       :        :                   :         : 6         :                
+GND*                         : V1        :        :                   :         : 1         :                
+GND*                         : V2        :        :                   :         : 1         :                
+GND                          : V3        : gnd    :                   :         :           :                
+GND*                         : V4        :        :                   :         : 1         :                
+GND_PLL1                     : V5        : gnd    :                   :         :           :                
+GND                          : V6        : gnd    :                   :         :           :                
+GNDA_PLL1                    : V7        : gnd    :                   :         :           :                
+GND*                         : V8        :        :                   :         : 8         :                
+GND*                         : V9        :        :                   :         : 8         :                
+VCCIO8                       : V10       : power  :                   : 3.3V    : 8         :                
+GND*                         : V11       :        :                   :         : 8         :                
+GND+                         : V12       :        :                   :         : 7         :                
+VCCIO7                       : V13       : power  :                   : 3.3V    : 7         :                
+GND*                         : V14       :        :                   :         : 7         :                
+GND*                         : V15       :        :                   :         : 7         :                
+GNDA_PLL4                    : V16       : gnd    :                   :         :           :                
+GND                          : V17       : gnd    :                   :         :           :                
+GND_PLL4                     : V18       : gnd    :                   :         :           :                
+GND*                         : V19       :        :                   :         : 6         :                
+GND*                         : V20       :        :                   :         : 6         :                
+GND*                         : V21       :        :                   :         : 6         :                
+GND*                         : V22       :        :                   :         : 6         :                
+GND*                         : W1        :        :                   :         : 1         :                
+GND*                         : W2        :        :                   :         : 1         :                
+GND*                         : W3        :        :                   :         : 1         :                
+GND*                         : W4        :        :                   :         : 1         :                
+GND*                         : W5        :        :                   :         : 1         :                
+VCCIO8                       : W6        : power  :                   : 3.3V    : 8         :                
+GND*                         : W7        :        :                   :         : 8         :                
+GND*                         : W8        :        :                   :         : 8         :                
+GND*                         : W9        :        :                   :         : 8         :                
+GND                          : W10       : gnd    :                   :         :           :                
+GND*                         : W11       :        :                   :         : 8         :                
+GND+                         : W12       :        :                   :         : 7         :                
+GND                          : W13       : gnd    :                   :         :           :                
+GND*                         : W14       :        :                   :         : 7         :                
+GND*                         : W15       :        :                   :         : 7         :                
+GND*                         : W16       :        :                   :         : 7         :                
+VCCIO7                       : W17       : power  :                   : 3.3V    : 7         :                
+NC                           : W18       :        :                   :         :           :                
+GND                          : W19       : gnd    :                   :         :           :                
+~LVDS91p/nCEO~               : W20       : output : 3.3-V LVTTL       :         : 6         : N              
+GND*                         : W21       :        :                   :         : 6         :                
+GND*                         : W22       :        :                   :         : 6         :                
+GND*                         : Y1        :        :                   :         : 1         :                
+GND*                         : Y2        :        :                   :         : 1         :                
+GND*                         : Y3        :        :                   :         : 1         :                
+GND*                         : Y4        :        :                   :         : 1         :                
+GND*                         : Y5        :        :                   :         : 8         :                
+GND*                         : Y6        :        :                   :         : 8         :                
+GND*                         : Y7        :        :                   :         : 8         :                
+GND                          : Y8        : gnd    :                   :         :           :                
+GND*                         : Y9        :        :                   :         : 8         :                
+GND*                         : Y10       :        :                   :         : 8         :                
+VCCIO8                       : Y11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : Y12       : power  :                   : 3.3V    : 7         :                
+OUTPUT_C                     : Y13       : output : 3.3-V LVTTL       :         : 7         : N              
+GND*                         : Y14       :        :                   :         : 7         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND*                         : Y16       :        :                   :         : 7         :                
+GND*                         : Y17       :        :                   :         : 7         :                
+GND*                         : Y18       :        :                   :         : 6         :                
+GND*                         : Y19       :        :                   :         : 6         :                
+GND*                         : Y20       :        :                   :         : 6         :                
+GND*                         : Y21       :        :                   :         : 6         :                
+GND*                         : Y22       :        :                   :         : 6         :                
--- a/Exp28/output_files/YL_dec7748.pof
+++ b/Exp28/output_files/YL_dec7748.pof
--- a/Exp28/output_files/YL_dec7748.sim.rpt
+++ b/Exp28/output_files/YL_dec7748.sim.rpt
@ -0,0 +1,179 @@
+Simulator report for YL_dec7748
+Sun May 03 17:01:03 2020
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Simulator Summary
+  3. Simulator Settings
+  4. Simulation Waveforms
+  5. Coverage Summary
+  6. Complete 1/0-Value Coverage
+  7. Missing 1-Value Coverage
+  8. Missing 0-Value Coverage
+  9. Simulator INI Usage
+ 10. Simulator Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
+--------------------------------------------+
+; Simulator Summary                          ;
+-----------------------------+--------------+
+; Type                        ; Value        ;
+-----------------------------+--------------+
+; Simulation Start Time       ; 0 ps         ;
+; Simulation End Time         ; 1.0 us       ;
+; Simulation Netlist Size     ; 18 nodes     ;
+; Simulation Coverage         ;     100.00 % ;
+; Total Number of Transitions ; 224          ;
+; Simulation Breakpoints      ; 0            ;
+; Family                      ; Cyclone II   ;
+; Device                      ; EP2C20F484C7 ;
+-----------------------------+--------------+
+
+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Simulator Settings                                                                                                                                                       ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+
+; Option                                                                                     ; Setting                                                     ; Default Value ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+
+; Simulation mode                                                                            ; Timing                                                      ; Timing        ;
+; Start time                                                                                 ; 0 ns                                                        ; 0 ns          ;
+; Simulation results format                                                                  ; VWF                                                         ;               ;
+; Vector input source                                                                        ; C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf ;               ;
+; Add pins automatically to simulation output waveforms                                      ; On                                                          ; On            ;
+; Check outputs                                                                              ; Off                                                         ; Off           ;
+; Report simulation coverage                                                                 ; On                                                          ; On            ;
+; Display complete 1/0 value coverage report                                                 ; On                                                          ; On            ;
+; Display missing 1-value coverage report                                                    ; On                                                          ; On            ;
+; Display missing 0-value coverage report                                                    ; On                                                          ; On            ;
+; Detect setup and hold time violations                                                      ; Off                                                         ; Off           ;
+; Detect glitches                                                                            ; Off                                                         ; Off           ;
+; Disable timing delays in Timing Simulation                                                 ; Off                                                         ; Off           ;
+; Generate Signal Activity File                                                              ; Off                                                         ; Off           ;
+; Generate VCD File for PowerPlay Power Analyzer                                             ; Off                                                         ; Off           ;
+; Group bus channels in simulation results                                                   ; Off                                                         ; Off           ;
+; Preserve fewer signal transitions to reduce memory requirements                            ; On                                                          ; On            ;
+; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE                                                  ; INPUT_EDGE    ;
+; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                                                         ; Off           ;
+; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off                                                         ;               ;
+; Perform Glitch Filtering in Timing Simulation                                              ; Auto                                                        ; Auto          ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------+---------------+
+
+
+----------------------+
+; Simulation Waveforms ;
+----------------------+
+Waveform report data cannot be output to ASCII.
+Please use Quartus II 64-Bit to view the waveform report data.
+
+
+--------------------------------------------------------------------+
+; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
+; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
+; Total coverage as a percentage                      ;     100.00 % ;
+; Total nodes checked                                 ; 18           ;
+; Total output ports checked                          ; 18           ;
+; Total output ports with complete 1/0-value coverage ; 18           ;
+; Total output ports with no 1/0-value coverage       ; 0            ;
+; Total output ports with no 1-value coverage         ; 0            ;
+; Total output ports with no 0-value coverage         ; 0            ;
+-----------------------------------------------------+--------------+
+
+
+The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------+
+; Complete 1/0-Value Coverage                                                ;
+----------------------------+----------------------------+------------------+
+; Node Name                  ; Output Port Name           ; Output Port Type ;
+----------------------------+----------------------------+------------------+
+; |YL_dec7748|7448:inst|69~0 ; |YL_dec7748|7448:inst|69~0 ; combout          ;
+; |YL_dec7748|7448:inst|68~0 ; |YL_dec7748|7448:inst|68~0 ; combout          ;
+; |YL_dec7748|7448:inst|70   ; |YL_dec7748|7448:inst|70   ; combout          ;
+; |YL_dec7748|7448:inst|67~0 ; |YL_dec7748|7448:inst|67~0 ; combout          ;
+; |YL_dec7748|7448:inst|71   ; |YL_dec7748|7448:inst|71   ; combout          ;
+; |YL_dec7748|7448:inst|66~0 ; |YL_dec7748|7448:inst|66~0 ; combout          ;
+; |YL_dec7748|7448:inst|72   ; |YL_dec7748|7448:inst|72   ; combout          ;
+; |YL_dec7748|OUTPUT_A       ; |YL_dec7748|OUTPUT_A       ; padio            ;
+; |YL_dec7748|OUTPUT_B       ; |YL_dec7748|OUTPUT_B       ; padio            ;
+; |YL_dec7748|OUTPUT_C       ; |YL_dec7748|OUTPUT_C       ; padio            ;
+; |YL_dec7748|OUTPUT_D       ; |YL_dec7748|OUTPUT_D       ; padio            ;
+; |YL_dec7748|OUTPUT_E       ; |YL_dec7748|OUTPUT_E       ; padio            ;
+; |YL_dec7748|OUTPUT_F       ; |YL_dec7748|OUTPUT_F       ; padio            ;
+; |YL_dec7748|OUTPUT_G       ; |YL_dec7748|OUTPUT_G       ; padio            ;
+; |YL_dec7748|INPUT_B        ; |YL_dec7748|INPUT_B~corein ; combout          ;
+; |YL_dec7748|INPUT_D        ; |YL_dec7748|INPUT_D~corein ; combout          ;
+; |YL_dec7748|INPUT_C        ; |YL_dec7748|INPUT_C~corein ; combout          ;
+; |YL_dec7748|INPUT_A        ; |YL_dec7748|INPUT_A~corein ; combout          ;
+----------------------------+----------------------------+------------------+
+
+
+The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
+; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
+
+
+The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
+; Missing 0-Value Coverage                        ;
+-----------+------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
+
+
+---------------------+
+; Simulator INI Usage ;
+--------+------------+
+; Option ; Usage      ;
+--------+------------+
+
+
+--------------------+
+; Simulator Messages ;
+--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Simulator
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Sun May 03 17:01:02 2020
+Info: Command: quartus_sim --simulation_results_format=VWF YL_dec7748 -c YL_dec7748
+Info (324025): Using vector source file "C:/Users/ushio/OneDrive/study/uol/ELEC211/Exp28/YL_7448.vwf"
+Info (310003): Option to preserve fewer signal transitions to reduce memory requirements is enabled
+    Info (310004): Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
+Info (310002): Simulation partitioned into 1 sub-simulations
+Info (328053): Simulation coverage is     100.00 %
+Info (328052): Number of transitions in simulation is 224
+Info (324045): Vector file YL_dec7748.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
+Info: Quartus II 64-Bit Simulator was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 4484 megabytes
+    Info: Processing ended: Sun May 03 17:01:03 2020
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
--- a/Exp28/output_files/YL_dec7748.sof
+++ b/Exp28/output_files/YL_dec7748.sof
--- a/Exp28/output_files/YL_dec7748.sta.rpt
+++ b/Exp28/output_files/YL_dec7748.sta.rpt
@ -0,0 +1,444 @@
+TimeQuest Timing Analyzer report for YL_dec7748
+Sun May 03 17:00:29 2020
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow Model Fmax Summary
+  6. Slow Model Setup Summary
+  7. Slow Model Hold Summary
+  8. Slow Model Recovery Summary
+  9. Slow Model Removal Summary
+ 10. Slow Model Minimum Pulse Width Summary
+ 11. Propagation Delay
+ 12. Minimum Propagation Delay
+ 13. Fast Model Setup Summary
+ 14. Fast Model Hold Summary
+ 15. Fast Model Recovery Summary
+ 16. Fast Model Removal Summary
+ 17. Fast Model Minimum Pulse Width Summary
+ 18. Propagation Delay
+ 19. Minimum Propagation Delay
+ 20. Multicorner Timing Analysis Summary
+ 21. Progagation Delay
+ 22. Minimum Progagation Delay
+ 23. Clock Transfers
+ 24. Report TCCS
+ 25. Report RSKM
+ 26. Unconstrained Paths
+ 27. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
+----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
+; Revision Name      ; YL_dec7748                                                        ;
+; Device Family      ; Cyclone II                                                        ;
+; Device Name        ; EP2C20F484C7                                                      ;
+; Timing Models      ; Final                                                             ;
+; Delay Model        ; Combined                                                          ;
+; Rise/Fall Delays   ; Unavailable                                                       ;
+--------------------+-------------------------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
+; Parallel Compilation                ;
+----------------------------+--------+
+; Processors                 ; Number ;
+----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
+----------------------------+--------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+---------------------------
+; Slow Model Fmax Summary ;
+---------------------------
+No paths to report.
+
+
+----------------------------
+; Slow Model Setup Summary ;
+----------------------------
+No paths to report.
+
+
+---------------------------
+; Slow Model Hold Summary ;
+---------------------------
+No paths to report.
+
+
+-------------------------------
+; Slow Model Recovery Summary ;
+-------------------------------
+No paths to report.
+
+
+------------------------------
+; Slow Model Removal Summary ;
+------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow Model Minimum Pulse Width Summary ;
+------------------------------------------
+No paths to report.
+
+
+--------------------------------------------------------------+
+; Propagation Delay                                            ;
+------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
+; INPUT_A    ; OUTPUT_A    ; 13.260 ; 13.260 ; 13.260 ; 13.260 ;
+; INPUT_A    ; OUTPUT_B    ; 11.167 ; 11.167 ; 11.167 ; 11.167 ;
+; INPUT_A    ; OUTPUT_C    ; 11.414 ;        ;        ; 11.414 ;
+; INPUT_A    ; OUTPUT_D    ; 11.576 ; 11.576 ; 11.576 ; 11.576 ;
+; INPUT_A    ; OUTPUT_E    ;        ; 11.915 ; 11.915 ;        ;
+; INPUT_A    ; OUTPUT_F    ;        ; 11.165 ; 11.165 ;        ;
+; INPUT_A    ; OUTPUT_G    ;        ; 11.134 ; 11.134 ;        ;
+; INPUT_B    ; OUTPUT_A    ; 13.063 ; 13.063 ; 13.063 ; 13.063 ;
+; INPUT_B    ; OUTPUT_B    ; 10.961 ; 10.961 ; 10.961 ; 10.961 ;
+; INPUT_B    ; OUTPUT_C    ;        ; 11.208 ; 11.208 ;        ;
+; INPUT_B    ; OUTPUT_D    ; 11.341 ; 11.341 ; 11.341 ; 11.341 ;
+; INPUT_B    ; OUTPUT_E    ; 11.754 ;        ;        ; 11.754 ;
+; INPUT_B    ; OUTPUT_F    ;        ; 10.967 ; 10.967 ;        ;
+; INPUT_B    ; OUTPUT_G    ; 10.907 ; 10.907 ; 10.907 ; 10.907 ;
+; INPUT_C    ; OUTPUT_A    ; 13.132 ; 13.132 ; 13.132 ; 13.132 ;
+; INPUT_C    ; OUTPUT_B    ;        ; 11.046 ; 11.046 ;        ;
+; INPUT_C    ; OUTPUT_C    ; 11.293 ; 11.293 ; 11.293 ; 11.293 ;
+; INPUT_C    ; OUTPUT_D    ; 11.455 ; 11.455 ; 11.455 ; 11.455 ;
+; INPUT_C    ; OUTPUT_E    ;        ; 11.838 ; 11.838 ;        ;
+; INPUT_C    ; OUTPUT_F    ; 11.037 ;        ;        ; 11.037 ;
+; INPUT_C    ; OUTPUT_G    ; 11.006 ; 11.006 ; 11.006 ; 11.006 ;
+; INPUT_D    ; OUTPUT_A    ; 12.550 ; 12.550 ; 12.550 ; 12.550 ;
+; INPUT_D    ; OUTPUT_B    ;        ; 10.467 ; 10.467 ;        ;
+; INPUT_D    ; OUTPUT_C    ;        ; 10.711 ; 10.711 ;        ;
+; INPUT_D    ; OUTPUT_F    ; 10.455 ;        ;        ; 10.455 ;
+; INPUT_D    ; OUTPUT_G    ; 10.396 ;        ;        ; 10.396 ;
+------------+-------------+--------+--------+--------+--------+
+
+
+--------------------------------------------------------------+
+; Minimum Propagation Delay                                    ;
+------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
+; INPUT_A    ; OUTPUT_A    ; 13.260 ; 13.260 ; 13.260 ; 13.260 ;
+; INPUT_A    ; OUTPUT_B    ; 11.167 ; 11.167 ; 11.167 ; 11.167 ;
+; INPUT_A    ; OUTPUT_C    ; 11.414 ;        ;        ; 11.414 ;
+; INPUT_A    ; OUTPUT_D    ; 11.576 ; 11.576 ; 11.576 ; 11.576 ;
+; INPUT_A    ; OUTPUT_E    ;        ; 11.915 ; 11.915 ;        ;
+; INPUT_A    ; OUTPUT_F    ;        ; 11.165 ; 11.165 ;        ;
+; INPUT_A    ; OUTPUT_G    ;        ; 11.134 ; 11.134 ;        ;
+; INPUT_B    ; OUTPUT_A    ; 13.063 ; 13.063 ; 13.063 ; 13.063 ;
+; INPUT_B    ; OUTPUT_B    ; 10.961 ; 10.961 ; 10.961 ; 10.961 ;
+; INPUT_B    ; OUTPUT_C    ;        ; 11.208 ; 11.208 ;        ;
+; INPUT_B    ; OUTPUT_D    ; 11.341 ; 11.341 ; 11.341 ; 11.341 ;
+; INPUT_B    ; OUTPUT_E    ; 11.754 ;        ;        ; 11.754 ;
+; INPUT_B    ; OUTPUT_F    ;        ; 10.967 ; 10.967 ;        ;
+; INPUT_B    ; OUTPUT_G    ; 10.907 ; 10.907 ; 10.907 ; 10.907 ;
+; INPUT_C    ; OUTPUT_A    ; 13.132 ; 13.132 ; 13.132 ; 13.132 ;
+; INPUT_C    ; OUTPUT_B    ;        ; 11.046 ; 11.046 ;        ;
+; INPUT_C    ; OUTPUT_C    ; 11.293 ; 11.293 ; 11.293 ; 11.293 ;
+; INPUT_C    ; OUTPUT_D    ; 11.455 ; 11.455 ; 11.455 ; 11.455 ;
+; INPUT_C    ; OUTPUT_E    ;        ; 11.838 ; 11.838 ;        ;
+; INPUT_C    ; OUTPUT_F    ; 11.037 ;        ;        ; 11.037 ;
+; INPUT_C    ; OUTPUT_G    ; 11.006 ; 11.006 ; 11.006 ; 11.006 ;
+; INPUT_D    ; OUTPUT_A    ; 12.550 ; 12.550 ; 12.550 ; 12.550 ;
+; INPUT_D    ; OUTPUT_B    ;        ; 10.467 ; 10.467 ;        ;
+; INPUT_D    ; OUTPUT_C    ;        ; 10.711 ; 10.711 ;        ;
+; INPUT_D    ; OUTPUT_F    ; 10.455 ;        ;        ; 10.455 ;
+; INPUT_D    ; OUTPUT_G    ; 10.396 ;        ;        ; 10.396 ;
+------------+-------------+--------+--------+--------+--------+
+
+
+----------------------------
+; Fast Model Setup Summary ;
+----------------------------
+No paths to report.
+
+
+---------------------------
+; Fast Model Hold Summary ;
+---------------------------
+No paths to report.
+
+
+-------------------------------
+; Fast Model Recovery Summary ;
+-------------------------------
+No paths to report.
+
+
+------------------------------
+; Fast Model Removal Summary ;
+------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast Model Minimum Pulse Width Summary ;
+------------------------------------------
+No paths to report.
+
+
+----------------------------------------------------------+
+; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
+; INPUT_A    ; OUTPUT_A    ; 6.571 ; 6.571 ; 6.571 ; 6.571 ;
+; INPUT_A    ; OUTPUT_B    ; 5.726 ; 5.726 ; 5.726 ; 5.726 ;
+; INPUT_A    ; OUTPUT_C    ; 5.804 ;       ;       ; 5.804 ;
+; INPUT_A    ; OUTPUT_D    ; 5.915 ; 5.915 ; 5.915 ; 5.915 ;
+; INPUT_A    ; OUTPUT_E    ;       ; 5.997 ; 5.997 ;       ;
+; INPUT_A    ; OUTPUT_F    ;       ; 5.727 ; 5.727 ;       ;
+; INPUT_A    ; OUTPUT_G    ;       ; 5.695 ; 5.695 ;       ;
+; INPUT_B    ; OUTPUT_A    ; 6.383 ; 6.383 ; 6.383 ; 6.383 ;
+; INPUT_B    ; OUTPUT_B    ; 5.531 ; 5.531 ; 5.531 ; 5.531 ;
+; INPUT_B    ; OUTPUT_C    ;       ; 5.611 ; 5.611 ;       ;
+; INPUT_B    ; OUTPUT_D    ; 5.720 ; 5.720 ; 5.720 ; 5.720 ;
+; INPUT_B    ; OUTPUT_E    ; 5.802 ;       ;       ; 5.802 ;
+; INPUT_B    ; OUTPUT_F    ;       ; 5.541 ; 5.541 ;       ;
+; INPUT_B    ; OUTPUT_G    ; 5.510 ; 5.510 ; 5.510 ; 5.510 ;
+; INPUT_C    ; OUTPUT_A    ; 6.508 ; 6.508 ; 6.508 ; 6.508 ;
+; INPUT_C    ; OUTPUT_B    ;       ; 5.669 ; 5.669 ;       ;
+; INPUT_C    ; OUTPUT_C    ; 5.747 ; 5.747 ; 5.747 ; 5.747 ;
+; INPUT_C    ; OUTPUT_D    ; 5.857 ; 5.857 ; 5.857 ; 5.857 ;
+; INPUT_C    ; OUTPUT_E    ;       ; 5.940 ; 5.940 ;       ;
+; INPUT_C    ; OUTPUT_F    ; 5.661 ;       ;       ; 5.661 ;
+; INPUT_C    ; OUTPUT_G    ; 5.629 ; 5.629 ; 5.629 ; 5.629 ;
+; INPUT_D    ; OUTPUT_A    ; 6.185 ; 6.185 ; 6.185 ; 6.185 ;
+; INPUT_D    ; OUTPUT_B    ;       ; 5.349 ; 5.349 ;       ;
+; INPUT_D    ; OUTPUT_C    ;       ; 5.434 ; 5.434 ;       ;
+; INPUT_D    ; OUTPUT_F    ; 5.338 ;       ;       ; 5.338 ;
+; INPUT_D    ; OUTPUT_G    ; 5.310 ;       ;       ; 5.310 ;
+------------+-------------+-------+-------+-------+-------+
+
+
+----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
+; INPUT_A    ; OUTPUT_A    ; 6.571 ; 6.571 ; 6.571 ; 6.571 ;
+; INPUT_A    ; OUTPUT_B    ; 5.726 ; 5.726 ; 5.726 ; 5.726 ;
+; INPUT_A    ; OUTPUT_C    ; 5.804 ;       ;       ; 5.804 ;
+; INPUT_A    ; OUTPUT_D    ; 5.915 ; 5.915 ; 5.915 ; 5.915 ;
+; INPUT_A    ; OUTPUT_E    ;       ; 5.997 ; 5.997 ;       ;
+; INPUT_A    ; OUTPUT_F    ;       ; 5.727 ; 5.727 ;       ;
+; INPUT_A    ; OUTPUT_G    ;       ; 5.695 ; 5.695 ;       ;
+; INPUT_B    ; OUTPUT_A    ; 6.383 ; 6.383 ; 6.383 ; 6.383 ;
+; INPUT_B    ; OUTPUT_B    ; 5.531 ; 5.531 ; 5.531 ; 5.531 ;
+; INPUT_B    ; OUTPUT_C    ;       ; 5.611 ; 5.611 ;       ;
+; INPUT_B    ; OUTPUT_D    ; 5.720 ; 5.720 ; 5.720 ; 5.720 ;
+; INPUT_B    ; OUTPUT_E    ; 5.802 ;       ;       ; 5.802 ;
+; INPUT_B    ; OUTPUT_F    ;       ; 5.541 ; 5.541 ;       ;
+; INPUT_B    ; OUTPUT_G    ; 5.510 ; 5.510 ; 5.510 ; 5.510 ;
+; INPUT_C    ; OUTPUT_A    ; 6.508 ; 6.508 ; 6.508 ; 6.508 ;
+; INPUT_C    ; OUTPUT_B    ;       ; 5.669 ; 5.669 ;       ;
+; INPUT_C    ; OUTPUT_C    ; 5.747 ; 5.747 ; 5.747 ; 5.747 ;
+; INPUT_C    ; OUTPUT_D    ; 5.857 ; 5.857 ; 5.857 ; 5.857 ;
+; INPUT_C    ; OUTPUT_E    ;       ; 5.940 ; 5.940 ;       ;
+; INPUT_C    ; OUTPUT_F    ; 5.661 ;       ;       ; 5.661 ;
+; INPUT_C    ; OUTPUT_G    ; 5.629 ; 5.629 ; 5.629 ; 5.629 ;
+; INPUT_D    ; OUTPUT_A    ; 6.185 ; 6.185 ; 6.185 ; 6.185 ;
+; INPUT_D    ; OUTPUT_B    ;       ; 5.349 ; 5.349 ;       ;
+; INPUT_D    ; OUTPUT_C    ;       ; 5.434 ; 5.434 ;       ;
+; INPUT_D    ; OUTPUT_F    ; 5.338 ;       ;       ; 5.338 ;
+; INPUT_D    ; OUTPUT_G    ; 5.310 ;       ;       ; 5.310 ;
+------------+-------------+-------+-------+-------+-------+
+
+
+----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
+------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
+------------------+-------+------+----------+---------+---------------------+
+
+
+--------------------------------------------------------------+
+; Progagation Delay                                            ;
+------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
+; INPUT_A    ; OUTPUT_A    ; 13.260 ; 13.260 ; 13.260 ; 13.260 ;
+; INPUT_A    ; OUTPUT_B    ; 11.167 ; 11.167 ; 11.167 ; 11.167 ;
+; INPUT_A    ; OUTPUT_C    ; 11.414 ;        ;        ; 11.414 ;
+; INPUT_A    ; OUTPUT_D    ; 11.576 ; 11.576 ; 11.576 ; 11.576 ;
+; INPUT_A    ; OUTPUT_E    ;        ; 11.915 ; 11.915 ;        ;
+; INPUT_A    ; OUTPUT_F    ;        ; 11.165 ; 11.165 ;        ;
+; INPUT_A    ; OUTPUT_G    ;        ; 11.134 ; 11.134 ;        ;
+; INPUT_B    ; OUTPUT_A    ; 13.063 ; 13.063 ; 13.063 ; 13.063 ;
+; INPUT_B    ; OUTPUT_B    ; 10.961 ; 10.961 ; 10.961 ; 10.961 ;
+; INPUT_B    ; OUTPUT_C    ;        ; 11.208 ; 11.208 ;        ;
+; INPUT_B    ; OUTPUT_D    ; 11.341 ; 11.341 ; 11.341 ; 11.341 ;
+; INPUT_B    ; OUTPUT_E    ; 11.754 ;        ;        ; 11.754 ;
+; INPUT_B    ; OUTPUT_F    ;        ; 10.967 ; 10.967 ;        ;
+; INPUT_B    ; OUTPUT_G    ; 10.907 ; 10.907 ; 10.907 ; 10.907 ;
+; INPUT_C    ; OUTPUT_A    ; 13.132 ; 13.132 ; 13.132 ; 13.132 ;
+; INPUT_C    ; OUTPUT_B    ;        ; 11.046 ; 11.046 ;        ;
+; INPUT_C    ; OUTPUT_C    ; 11.293 ; 11.293 ; 11.293 ; 11.293 ;
+; INPUT_C    ; OUTPUT_D    ; 11.455 ; 11.455 ; 11.455 ; 11.455 ;
+; INPUT_C    ; OUTPUT_E    ;        ; 11.838 ; 11.838 ;        ;
+; INPUT_C    ; OUTPUT_F    ; 11.037 ;        ;        ; 11.037 ;
+; INPUT_C    ; OUTPUT_G    ; 11.006 ; 11.006 ; 11.006 ; 11.006 ;
+; INPUT_D    ; OUTPUT_A    ; 12.550 ; 12.550 ; 12.550 ; 12.550 ;
+; INPUT_D    ; OUTPUT_B    ;        ; 10.467 ; 10.467 ;        ;
+; INPUT_D    ; OUTPUT_C    ;        ; 10.711 ; 10.711 ;        ;
+; INPUT_D    ; OUTPUT_F    ; 10.455 ;        ;        ; 10.455 ;
+; INPUT_D    ; OUTPUT_G    ; 10.396 ;        ;        ; 10.396 ;
+------------+-------------+--------+--------+--------+--------+
+
+
+----------------------------------------------------------+
+; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
+; INPUT_A    ; OUTPUT_A    ; 6.571 ; 6.571 ; 6.571 ; 6.571 ;
+; INPUT_A    ; OUTPUT_B    ; 5.726 ; 5.726 ; 5.726 ; 5.726 ;
+; INPUT_A    ; OUTPUT_C    ; 5.804 ;       ;       ; 5.804 ;
+; INPUT_A    ; OUTPUT_D    ; 5.915 ; 5.915 ; 5.915 ; 5.915 ;
+; INPUT_A    ; OUTPUT_E    ;       ; 5.997 ; 5.997 ;       ;
+; INPUT_A    ; OUTPUT_F    ;       ; 5.727 ; 5.727 ;       ;
+; INPUT_A    ; OUTPUT_G    ;       ; 5.695 ; 5.695 ;       ;
+; INPUT_B    ; OUTPUT_A    ; 6.383 ; 6.383 ; 6.383 ; 6.383 ;
+; INPUT_B    ; OUTPUT_B    ; 5.531 ; 5.531 ; 5.531 ; 5.531 ;
+; INPUT_B    ; OUTPUT_C    ;       ; 5.611 ; 5.611 ;       ;
+; INPUT_B    ; OUTPUT_D    ; 5.720 ; 5.720 ; 5.720 ; 5.720 ;
+; INPUT_B    ; OUTPUT_E    ; 5.802 ;       ;       ; 5.802 ;
+; INPUT_B    ; OUTPUT_F    ;       ; 5.541 ; 5.541 ;       ;
+; INPUT_B    ; OUTPUT_G    ; 5.510 ; 5.510 ; 5.510 ; 5.510 ;
+; INPUT_C    ; OUTPUT_A    ; 6.508 ; 6.508 ; 6.508 ; 6.508 ;
+; INPUT_C    ; OUTPUT_B    ;       ; 5.669 ; 5.669 ;       ;
+; INPUT_C    ; OUTPUT_C    ; 5.747 ; 5.747 ; 5.747 ; 5.747 ;
+; INPUT_C    ; OUTPUT_D    ; 5.857 ; 5.857 ; 5.857 ; 5.857 ;
+; INPUT_C    ; OUTPUT_E    ;       ; 5.940 ; 5.940 ;       ;
+; INPUT_C    ; OUTPUT_F    ; 5.661 ;       ;       ; 5.661 ;
+; INPUT_C    ; OUTPUT_G    ; 5.629 ; 5.629 ; 5.629 ; 5.629 ;
+; INPUT_D    ; OUTPUT_A    ; 6.185 ; 6.185 ; 6.185 ; 6.185 ;
+; INPUT_D    ; OUTPUT_B    ;       ; 5.349 ; 5.349 ;       ;
+; INPUT_D    ; OUTPUT_C    ;       ; 5.434 ; 5.434 ;       ;
+; INPUT_D    ; OUTPUT_F    ; 5.338 ;       ;       ; 5.338 ;
+; INPUT_D    ; OUTPUT_G    ; 5.310 ;       ;       ; 5.310 ;
+------------+-------------+-------+-------+-------+-------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
+------------------------------------------------+
+; Unconstrained Paths                            ;
+---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 4     ; 4    ;
+; Unconstrained Input Port Paths  ; 26    ; 26   ;
+; Unconstrained Output Ports      ; 7     ; 7    ;
+; Unconstrained Output Port Paths ; 26    ; 26   ;
+---------------------------------+-------+------+
+
+
+------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Sun May 03 17:00:28 2020
+Info: Command: quartus_sta YL_dec7748 -c YL_dec7748
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'YL_dec7748.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info: Analyzing Fast Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 4541 megabytes
+    Info: Processing ended: Sun May 03 17:00:29 2020
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
--- a/Show More
+++ b/Show More